sbic.c revision 1.13
1 /* $NetBSD: sbic.c,v 1.13 2000/03/23 06:41:28 thorpej Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 #include "opt_ddb.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/kernel.h> /* For hz */ 61 #include <sys/disklabel.h> 62 #include <sys/dkstat.h> 63 #include <sys/buf.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <vm/vm.h> 70 #include <vm/vm_kern.h> 71 #include <vm/vm_page.h> 72 #include <vm/pmap.h> 73 74 #include <machine/pmap.h> 75 76 #include <mvme68k/mvme68k/isr.h> 77 #include <mvme68k/dev/dmavar.h> 78 #include <mvme68k/dev/sbicreg.h> 79 #include <mvme68k/dev/sbicvar.h> 80 81 82 /* 83 * Since I can't find this in any other header files 84 */ 85 #define SCSI_PHASE(reg) (reg&0x07) 86 87 /* 88 * SCSI delays 89 * In u-seconds, primarily for state changes on the SPC. 90 */ 91 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 92 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 93 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 94 95 /* 96 * Convenience macro for waiting for a particular sbic event 97 */ 98 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 99 100 extern paddr_t kvtop __P((caddr_t)); 101 102 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 103 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 104 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 105 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 106 int sbiccheckdmap __P((void *, u_long, u_long)); 107 u_char sbicselectbus __P((struct sbic_softc *)); 108 int sbicxfout __P((sbic_regmap_p, int, void *)); 109 int sbicxfin __P((sbic_regmap_p, int, void *)); 110 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 111 int sbictoscsiperiod __P((struct sbic_softc *, int)); 112 int sbicpoll __P((struct sbic_softc *)); 113 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 114 int sbicmsgin __P((struct sbic_softc *)); 115 int sbicabort __P((struct sbic_softc *, char *)); 116 void sbicxfdone __P((struct sbic_softc *)); 117 void sbicerror __P((struct sbic_softc *,u_char)); 118 void sbicreset __P((struct sbic_softc *)); 119 void sbic_scsidone __P((struct sbic_acb *, int)); 120 void sbic_sched __P((struct sbic_softc *)); 121 void sbic_save_ptrs __P((struct sbic_softc *)); 122 void sbic_load_ptrs __P((struct sbic_softc *)); 123 124 /* 125 * Synch xfer parameters, and timing conversions 126 */ 127 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 128 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 129 int sbic_cmd_wait = SBIC_CMD_WAIT; 130 int sbic_data_wait = SBIC_DATA_WAIT; 131 int sbic_init_wait = SBIC_INIT_WAIT; 132 133 /* 134 * was broken before.. now if you want this you get it for all drives 135 * on sbic controllers. 136 */ 137 u_char sbic_inhibit_sync[8]; 138 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 139 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 140 int sbic_parallel_operations = 1; /* Allow command queues */ 141 142 /* 143 * Some useful stuff for debugging purposes 144 */ 145 #ifdef DEBUG 146 int sbicdma_ops = 0; /* total DMA operations */ 147 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 148 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 149 int sbicdma_saves = 0; 150 151 #define QPRINTF(a) if (sbic_debug > 1) printf a 152 153 int sbic_debug = 0; /* Debug all chip related things */ 154 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 155 int reselect_debug = 0; /* Debug all reselection related things */ 156 int report_sense = 0; /* Always print Sense information */ 157 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 158 159 void sbictimeout __P((struct sbic_softc *dev)); 160 161 #else 162 #define QPRINTF(a) /* */ 163 #endif 164 165 166 /* 167 * default minphys routine for sbic based controllers 168 */ 169 void 170 sbic_minphys(bp) 171 struct buf *bp; 172 { 173 /* 174 * No max transfer at this level. 175 */ 176 minphys(bp); 177 } 178 179 180 /* 181 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 182 */ 183 void 184 sbic_save_ptrs(dev) 185 struct sbic_softc *dev; 186 { 187 sbic_regmap_p regs; 188 struct sbic_acb* acb; 189 int count, 190 asr, 191 s; 192 193 /* 194 * Only need to save pointers if DMA was active... 195 */ 196 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 197 return; 198 199 regs = dev->sc_sbicp; 200 201 s = splbio(); 202 203 /* 204 * Wait until WD chip is idle 205 */ 206 do { 207 GET_SBIC_asr(regs, asr); 208 if( asr & SBIC_ASR_DBR ) { 209 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 210 splx(s); 211 return; 212 } 213 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 214 215 216 /* 217 * Save important state. 218 * must be done before dmastop 219 */ 220 acb = dev->sc_nexus; 221 acb->sc_dmacmd = dev->sc_dmacmd; 222 223 /* 224 * Fetch the residual count 225 */ 226 SBIC_TC_GET(regs, count); 227 228 /* 229 * Shut down DMA 230 */ 231 dev->sc_dmastop(dev); 232 233 /* 234 * No longer in DMA 235 */ 236 dev->sc_flags &= ~SBICF_INDMA; 237 238 /* 239 * Ensure the WD chip is back in polled I/O mode, with nothing to 240 * transfer. 241 */ 242 SBIC_TC_PUT(regs, 0); 243 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 244 245 /* 246 * Update current count... 247 */ 248 acb->sc_tcnt = count; 249 250 /* 251 * Work out how many bytes were actually transferred 252 */ 253 count = dev->sc_tcnt - count; 254 dev->sc_tcnt = acb->sc_tcnt; 255 256 /* 257 * Fixup partial xfers 258 */ 259 acb->sc_kv.dc_addr += count; 260 acb->sc_kv.dc_count -= count; 261 acb->sc_pa.dc_addr += count; 262 acb->sc_pa.dc_count -= count >> 1; 263 264 #ifdef DEBUG 265 if ( data_pointer_debug ) 266 printf("save at (%p,%x):%x\n", 267 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 268 sbicdma_saves++; 269 #endif 270 271 splx(s); 272 } 273 274 275 /* 276 * DOES NOT RESTART DMA!!! 277 */ 278 void 279 sbic_load_ptrs(dev) 280 struct sbic_softc *dev; 281 { 282 struct sbic_acb *acb = dev->sc_nexus; 283 int s; 284 285 if ( acb->sc_kv.dc_count == 0 ) { 286 /* 287 * No data to xfer 288 */ 289 return; 290 } 291 292 s = splbio(); 293 294 /* 295 * Reset the Scatter-Gather chain 296 */ 297 dev->sc_last = dev->sc_cur = &acb->sc_pa; 298 299 /* 300 * Restore the Transfer Count and DMA specific data 301 */ 302 dev->sc_tcnt = acb->sc_tcnt; 303 dev->sc_dmacmd = acb->sc_dmacmd; 304 305 #ifdef DEBUG 306 sbicdma_ops++; 307 #endif 308 309 /* 310 * Need to fixup new segment? 311 */ 312 if ( dev->sc_tcnt == 0 ) { 313 /* 314 * sc_tcnt == 0 implies end of segment 315 */ 316 char *vaddr, *paddr; 317 int count; 318 319 /* 320 * do kvm to pa mappings 321 */ 322 vaddr = acb->sc_kv.dc_addr; 323 paddr = acb->sc_pa.dc_addr = (char *) kvtop((caddr_t)vaddr); 324 325 for (count = (NBPG - ((int)vaddr & PGOFSET)); 326 count < acb->sc_kv.dc_count && 327 (char*)kvtop((caddr_t)(vaddr + count + 4)) == paddr + count + 4; 328 count += NBPG) 329 ; /* Do nothing */ 330 331 /* 332 * If it's all contiguous... 333 */ 334 if ( count > acb->sc_kv.dc_count ) { 335 count = acb->sc_kv.dc_count; 336 #ifdef DEBUG 337 sbicdma_hits++; 338 #endif 339 } 340 #ifdef DEBUG 341 else 342 sbicdma_misses++; 343 #endif 344 345 acb->sc_tcnt = count; 346 acb->sc_pa.dc_count = count >> 1; 347 348 #ifdef DEBUG 349 if ( data_pointer_debug ) 350 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", acb->sc_kv.dc_addr, 351 acb->sc_kv.dc_count, 352 acb->sc_pa.dc_addr, 353 acb->sc_tcnt); 354 #endif 355 356 } 357 358 splx(s); 359 } 360 361 /* 362 * used by specific sbic controller 363 * 364 * it appears that the higher level code does nothing with LUN's 365 * so I will too. I could plug it in, however so could they 366 * in scsi_scsipi_cmd(). 367 */ 368 int 369 sbic_scsicmd(xs) 370 struct scsipi_xfer *xs; 371 { 372 struct scsipi_link *slp = xs->sc_link; 373 struct sbic_softc *dev = slp->adapter_softc; 374 struct sbic_acb *acb; 375 int flags = xs->xs_control, 376 s; 377 378 if ( flags & XS_CTL_DATA_UIO ) 379 panic("sbic: scsi data uio requested"); 380 381 if ( dev->sc_nexus && (flags & XS_CTL_POLL) ) 382 panic("sbic_scsicmd: busy"); 383 384 if ( slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target ) 385 return ESCAPE_NOT_SUPPORTED; 386 387 s = splbio(); 388 389 if ( (acb = dev->free_list.tqh_first) != NULL ) 390 TAILQ_REMOVE(&dev->free_list, acb, chain); 391 392 splx(s); 393 394 if ( acb == NULL ) { 395 #ifdef DEBUG 396 printf("sbic_scsicmd: unable to queue request for target %d\n", 397 slp->scsipi_scsi.target); 398 #ifdef DDB 399 Debugger(); 400 #endif 401 #endif 402 xs->error = XS_DRIVER_STUFFUP; 403 404 return(TRY_AGAIN_LATER); 405 } 406 407 if ( flags & XS_CTL_DATA_IN ) 408 acb->flags = ACB_ACTIVE | ACB_DATAIN; 409 else 410 acb->flags = ACB_ACTIVE; 411 412 acb->xs = xs; 413 acb->clen = xs->cmdlen; 414 acb->sc_kv.dc_addr = xs->data; 415 acb->sc_kv.dc_count = xs->datalen; 416 acb->pa_addr = xs->data ? (char *)kvtop((caddr_t)xs->data) : 0; 417 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 418 419 if ( flags & XS_CTL_POLL ) { 420 /* 421 * This has major side effects -- it locks up the machine 422 */ 423 int stat; 424 425 s = splbio(); 426 427 dev->sc_flags |= SBICF_ICMD; 428 429 do { 430 /* 431 * If we already had a nexus, while away the time until idle... 432 * This is likely only to happen if a reselection occurs between 433 * here and our earlier check for ICMD && sc_nexus (which would 434 * have resulted in a panic() had it been true). 435 */ 436 while ( dev->sc_nexus ) 437 sbicpoll(dev); 438 439 /* 440 * Fix up the new nexus 441 */ 442 dev->sc_nexus = acb; 443 dev->sc_xs = xs; 444 dev->target = slp->scsipi_scsi.target; 445 dev->lun = slp->scsipi_scsi.lun; 446 447 stat = sbicicmd(dev, &acb->cmd, acb->clen, 448 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 449 450 } while ( dev->sc_nexus != acb ); 451 452 sbic_scsidone(acb, stat); 453 454 splx(s); 455 456 return(COMPLETE); 457 } 458 459 s = splbio(); 460 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 461 462 /* 463 * If nothing is active, try to start it now. 464 */ 465 if ( dev->sc_nexus == NULL ) 466 sbic_sched(dev); 467 468 splx(s); 469 470 return(SUCCESSFULLY_QUEUED); 471 } 472 473 /* 474 * attempt to start the next available command 475 */ 476 void 477 sbic_sched(dev) 478 struct sbic_softc *dev; 479 { 480 struct scsipi_xfer *xs; 481 struct scsipi_link *slp = NULL; /* Gag the compiler */ 482 struct sbic_acb *acb; 483 int flags, 484 stat; 485 486 /* 487 * XXXSCW 488 * I'll keep this test here, even though I can't see any obvious way 489 * in which sbic_sched() could be called with sc_nexus non NULL 490 */ 491 if ( dev->sc_nexus ) 492 return; /* a command is current active */ 493 494 /* 495 * Loop through the ready list looking for work to do... 496 */ 497 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 498 int i, j; 499 500 slp = acb->xs->sc_link; 501 i = slp->scsipi_scsi.target; 502 j = 1 << slp->scsipi_scsi.lun; 503 504 /* 505 * We've found a potential command, but is the target/lun busy? 506 */ 507 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 508 /* 509 * Nope, it's not busy, so we can use it. 510 */ 511 dev->sc_tinfo[i].lubusy |= j; 512 TAILQ_REMOVE(&dev->ready_list, acb, chain); 513 dev->sc_nexus = acb; 514 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 515 break; 516 } 517 } 518 519 if ( acb == NULL ) { 520 QPRINTF(("sbicsched: no work\n")); 521 return; /* did not find an available command */ 522 } 523 524 #ifdef DEBUG 525 if ( data_pointer_debug > 1 ) 526 printf("sbic_sched(%d,%d)\n", slp->scsipi_scsi.target, 527 slp->scsipi_scsi.lun); 528 #endif 529 530 dev->sc_xs = xs = acb->xs; 531 flags = xs->xs_control; 532 533 if ( flags & XS_CTL_RESET ) 534 sbicreset(dev); 535 536 dev->sc_stat[0] = -1; 537 dev->target = slp->scsipi_scsi.target; 538 dev->lun = slp->scsipi_scsi.lun; 539 540 if ( flags & XS_CTL_POLL || (!sbic_parallel_operations && 541 (sbicdmaok(dev, xs) == 0)) ) 542 stat = sbicicmd(dev, &acb->cmd, acb->clen, 543 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 544 else 545 if ( sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT ) 546 return; 547 else 548 stat = dev->sc_stat[0]; 549 550 sbic_scsidone(acb, stat); 551 } 552 553 void 554 sbic_scsidone(acb, stat) 555 struct sbic_acb *acb; 556 int stat; 557 { 558 struct scsipi_xfer *xs = acb->xs; 559 struct scsipi_link *slp = xs->sc_link; 560 struct sbic_softc *dev = slp->adapter_softc; 561 int dosched = 0; 562 563 #ifdef DIAGNOSTIC 564 if ( acb == NULL || xs == NULL ) { 565 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); 566 #ifdef DDB 567 Debugger(); 568 #endif 569 return; 570 } 571 #endif 572 573 /* 574 * is this right? 575 */ 576 xs->status = stat; 577 578 #ifdef DEBUG 579 if ( data_pointer_debug > 1 ) 580 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", slp->scsipi_scsi.target, 581 slp->scsipi_scsi.lun, 582 dev->target, dev->lun, stat); 583 584 if ( xs->sc_link->scsipi_scsi.target == 585 dev->sc_link.scsipi_scsi.adapter_target ) 586 panic("target == hostid"); 587 #endif 588 589 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) == 0 ) { 590 591 if ( stat == SCSI_CHECK ) { 592 /* 593 * Schedule a REQUEST SENSE 594 */ 595 struct scsipi_sense *ss = (void *)&acb->cmd; 596 597 #ifdef DEBUG 598 if ( report_sense ) 599 printf("sbic_scsidone: autosense %02x targ %d lun %d", 600 acb->cmd.opcode, slp->scsipi_scsi.target, 601 slp->scsipi_scsi.lun); 602 #endif 603 604 bzero(ss, sizeof(*ss)); 605 606 ss->opcode = REQUEST_SENSE; 607 ss->byte2 = slp->scsipi_scsi.lun << 5; 608 ss->length = sizeof(struct scsipi_sense_data); 609 610 acb->clen = sizeof(*ss); 611 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 612 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 613 acb->pa_addr = (char *)kvtop((caddr_t)&xs->sense.scsi_sense); 614 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 615 616 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 617 618 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 619 ~(1 << slp->scsipi_scsi.lun); 620 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 621 622 if ( dev->sc_nexus == acb ) { 623 dev->sc_nexus = NULL; 624 dev->sc_xs = NULL; 625 sbic_sched(dev); 626 } 627 return; 628 } 629 } 630 631 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) != 0 ) { 632 633 xs->error = XS_SENSE; 634 635 #ifdef DEBUG 636 if (report_sense) 637 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 638 xs->sense.scsi_sense.extra_bytes[3]); 639 #endif 640 641 } else { 642 xs->resid = 0; /* XXXX */ 643 } 644 645 xs->xs_status |= XS_STS_DONE; 646 647 /* 648 * Remove the ACB from whatever queue it's on. We have to do a bit of 649 * a hack to figure out which queue it's on. Note that it is *not* 650 * necessary to cdr down the ready queue, but we must cdr down the 651 * nexus queue and see if it's there, so we can mark the unit as no 652 * longer busy. This code is sickening, but it works. 653 */ 654 if ( acb == dev->sc_nexus ) { 655 656 dev->sc_nexus = NULL; 657 dev->sc_xs = NULL; 658 659 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 660 ~(1 << slp->scsipi_scsi.lun); 661 662 if ( dev->ready_list.tqh_first ) 663 dosched = 1; /* start next command */ 664 665 } else 666 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 667 668 TAILQ_REMOVE(&dev->ready_list, acb, chain); 669 670 } else { 671 672 struct sbic_acb *a; 673 674 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 675 if ( a == acb ) { 676 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 677 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 678 ~(1 << slp->scsipi_scsi.lun); 679 break; 680 } 681 } 682 683 if ( a ) 684 ; 685 else if ( acb->chain.tqe_next ) { 686 TAILQ_REMOVE(&dev->ready_list, acb, chain); 687 } else { 688 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 689 #ifdef DDB 690 Debugger(); 691 #endif 692 } 693 } 694 695 /* 696 * Put it on the free list. 697 */ 698 acb->flags = ACB_FREE; 699 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 700 701 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 702 703 scsipi_done(xs); 704 705 if ( dosched ) 706 sbic_sched(dev); 707 } 708 709 int 710 sbicdmaok(dev, xs) 711 struct sbic_softc *dev; 712 struct scsipi_xfer *xs; 713 { 714 if ( sbic_no_dma || xs->datalen == 0 || 715 xs->datalen & 0x03 || (int)xs->data & 0x03) 716 return(0); 717 718 /* 719 * controller supports dma to any addresses? 720 */ 721 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 722 return(1); 723 724 /* 725 * this address is ok for dma? 726 */ 727 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 728 return(1); 729 730 return(0); 731 } 732 733 int 734 sbicwait(regs, until, timeo, line) 735 sbic_regmap_p regs; 736 u_char until; 737 int timeo; 738 int line; 739 { 740 u_char val; 741 742 if ( timeo == 0 ) 743 timeo = 1000000; /* some large value.. */ 744 745 GET_SBIC_asr(regs, val); 746 747 while ( (val & until) == 0 ) { 748 749 if ( timeo-- == 0 ) { 750 int csr; 751 GET_SBIC_csr(regs, csr); 752 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 753 #if defined(DDB) && defined(DEBUG) 754 Debugger(); 755 #endif 756 return(val); /* Maybe I should abort */ 757 break; 758 } 759 760 DELAY(1); 761 GET_SBIC_asr(regs, val); 762 } 763 764 return(val); 765 } 766 767 int 768 sbicabort(dev, where) 769 struct sbic_softc *dev; 770 char *where; 771 { 772 sbic_regmap_p regs = dev->sc_sbicp; 773 u_char csr, 774 asr; 775 776 GET_SBIC_asr(regs, asr); 777 GET_SBIC_csr(regs, csr); 778 779 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 780 dev->sc_dev.dv_xname, where, csr, asr); 781 782 /* 783 * Clean up chip itself 784 */ 785 if ( dev->sc_flags & SBICF_SELECTED ) { 786 787 while ( asr & SBIC_ASR_DBR ) { 788 /* 789 * sbic is jammed w/data. need to clear it 790 * But we don't know what direction it needs to go 791 */ 792 GET_SBIC_data(regs, asr); 793 printf("%s: abort %s: clearing data buffer 0x%02x\n", 794 dev->sc_dev.dv_xname, where, asr); 795 GET_SBIC_asr(regs, asr); 796 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 797 SET_SBIC_data(regs, asr); 798 GET_SBIC_asr(regs, asr); 799 } 800 801 WAIT_CIP(regs); 802 803 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 804 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 805 WAIT_CIP(regs); 806 807 GET_SBIC_asr(regs, asr); 808 809 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 810 /* 811 * ok, get more drastic.. 812 */ 813 printf("%s: sbicabort - asr %x, trying to reset\n", 814 dev->sc_dev.dv_xname, asr); 815 sbicreset(dev); 816 dev->sc_flags &= ~SBICF_SELECTED; 817 return SBIC_STATE_ERROR; 818 } 819 820 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 821 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 822 823 do { 824 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 825 GET_SBIC_asr(regs, asr); 826 GET_SBIC_csr (regs, csr); 827 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 828 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 829 (csr != SBIC_CSR_CMD_INVALID) ); 830 831 /* 832 * lets just hope it worked.. 833 */ 834 dev->sc_flags &= ~SBICF_SELECTED; 835 } 836 837 return SBIC_STATE_ERROR; 838 } 839 840 841 /* 842 * Initialize driver-private structures 843 */ 844 void 845 sbicinit(dev) 846 struct sbic_softc *dev; 847 { 848 u_int i; 849 850 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 851 852 struct sbic_acb *acb; 853 854 TAILQ_INIT(&dev->ready_list); 855 TAILQ_INIT(&dev->nexus_list); 856 TAILQ_INIT(&dev->free_list); 857 callout_init(&dev->sc_timo_ch); 858 859 dev->sc_nexus = NULL; 860 dev->sc_xs = NULL; 861 862 acb = dev->sc_acb; 863 bzero(acb, sizeof(dev->sc_acb)); 864 865 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 866 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 867 acb++; 868 } 869 870 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 871 872 #ifdef DEBUG 873 /* 874 * make sure timeout is really not needed 875 */ 876 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 877 #endif 878 879 } else 880 panic("sbic: reinitializing driver!"); 881 882 dev->sc_flags |= SBICF_ALIVE; 883 dev->sc_flags &= ~SBICF_SELECTED; 884 885 /* 886 * initialize inhibit array 887 * Never enable Sync, since it just doesn't work on mvme147 :( 888 */ 889 for (i = 0; i < 8; ++i) 890 sbic_inhibit_sync[i] = 1; 891 892 sbicreset(dev); 893 } 894 895 void 896 sbicreset(dev) 897 struct sbic_softc *dev; 898 { 899 sbic_regmap_p regs = dev->sc_sbicp; 900 u_int my_id, 901 s; 902 u_char csr; 903 904 s = splbio(); 905 906 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 907 908 if (dev->sc_clkfreq < 110) 909 my_id |= SBIC_ID_FS_8_10; 910 else if (dev->sc_clkfreq < 160) 911 my_id |= SBIC_ID_FS_12_15; 912 else if (dev->sc_clkfreq < 210) 913 my_id |= SBIC_ID_FS_16_20; 914 915 SET_SBIC_myid(regs, my_id); 916 917 /* 918 * Reset the chip 919 */ 920 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 921 DELAY(25); 922 923 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 924 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 925 926 /* 927 * Set up various chip parameters 928 */ 929 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 930 931 /* 932 * don't allow Selection (SBIC_RID_ES) 933 * until we can handle target mode!! 934 */ 935 SET_SBIC_rselid(regs, SBIC_RID_ER); 936 937 /* 938 * Asynchronous for now 939 */ 940 SET_SBIC_syn(regs, 0); 941 942 /* 943 * Anything else was zeroed by reset 944 */ 945 splx(s); 946 947 dev->sc_flags &= ~SBICF_SELECTED; 948 } 949 950 void 951 sbicerror(dev, csr) 952 struct sbic_softc *dev; 953 u_char csr; 954 { 955 struct scsipi_xfer *xs = dev->sc_xs; 956 957 #ifdef DIAGNOSTIC 958 if ( xs == NULL ) 959 panic("sbicerror: dev->sc_xs == NULL"); 960 #endif 961 962 if ( xs->xs_control & XS_CTL_SILENT ) 963 return; 964 965 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 966 } 967 968 /* 969 * select the bus, return when selected or error. 970 * 971 * Returns the current CSR following selection and optionally MSG out phase. 972 * i.e. the returned CSR *should* indicate CMD phase... 973 * If the return value is 0, some error happened. 974 */ 975 u_char 976 sbicselectbus(dev) 977 struct sbic_softc *dev; 978 { 979 sbic_regmap_p regs = dev->sc_sbicp; 980 u_char target = dev->target, 981 lun = dev->lun, 982 asr, 983 csr, 984 id; 985 986 /* 987 * if we're already selected, return (XXXX panic maybe?) 988 */ 989 if ( dev->sc_flags & SBICF_SELECTED ) 990 return(0); 991 992 QPRINTF(("sbicselectbus %d: ", target)); 993 994 /* 995 * issue select 996 */ 997 SET_SBIC_selid(regs, target); 998 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 999 1000 GET_SBIC_asr(regs, asr); 1001 1002 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1003 /* 1004 * This means we got ourselves reselected upon 1005 */ 1006 QPRINTF(("WD busy (reselect?)\n")); 1007 return 0; 1008 } 1009 1010 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1011 1012 /* 1013 * wait for select (merged from seperate function may need 1014 * cleanup) 1015 */ 1016 WAIT_CIP(regs); 1017 1018 do { 1019 1020 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1021 1022 if ( asr & SBIC_ASR_LCI ) { 1023 QPRINTF(("late LCI: asr %02x\n", asr)); 1024 return 0; 1025 } 1026 1027 /* 1028 * Clear interrupt 1029 */ 1030 GET_SBIC_csr (regs, csr); 1031 1032 QPRINTF(("%02x ", csr)); 1033 1034 /* 1035 * Reselected from under our feet? 1036 */ 1037 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 1038 QPRINTF(("got reselected, asr %02x\n", asr)); 1039 /* 1040 * We need to handle this now so we don't lock up later 1041 */ 1042 sbicnextstate(dev, csr, asr); 1043 1044 return 0; 1045 } 1046 1047 /* 1048 * Whoops! 1049 */ 1050 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1051 panic("sbicselectbus: target issued select!"); 1052 return 0; 1053 } 1054 1055 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1056 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1057 csr != SBIC_CSR_SEL_TIMEO); 1058 1059 /* 1060 * Anyone at home? 1061 */ 1062 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1063 dev->sc_xs->error = XS_SELTIMEOUT; 1064 QPRINTF(("Selection Timeout\n")); 1065 return 0; 1066 } 1067 1068 QPRINTF(("Selection Complete\n")); 1069 1070 /* 1071 * Assume we're now selected 1072 */ 1073 GET_SBIC_selid(regs, id); 1074 dev->target = id; 1075 dev->lun = lun; 1076 dev->sc_flags |= SBICF_SELECTED; 1077 1078 /* 1079 * Enable (or not) reselection 1080 * XXXSCW This is probably not necessary since we don't use use the 1081 * Select-and-Xfer-with-ATN command to initiate a selection... 1082 */ 1083 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1084 SET_SBIC_rselid (regs, 0); 1085 else 1086 SET_SBIC_rselid (regs, SBIC_RID_ER); 1087 1088 /* 1089 * We only really need to do anything when the target goes to MSG out 1090 * If the device ignored ATN, it's probably old and brain-dead, 1091 * but we'll try to support it anyhow. 1092 * If it doesn't support message out, it definately doesn't 1093 * support synchronous transfers, so no point in even asking... 1094 */ 1095 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1096 /* 1097 * Send identify message (SCSI-2 requires an identify msg) 1098 */ 1099 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1100 /* 1101 * Handle drives that don't want to be asked 1102 * whether to go sync at all. 1103 */ 1104 dev->sc_sync[id].offset = 0; 1105 dev->sc_sync[id].period = sbic_min_period; 1106 dev->sc_sync[id].state = SYNC_DONE; 1107 } 1108 1109 /* 1110 * Do we need to negotiate Synchronous Xfers for this target? 1111 */ 1112 if ( dev->sc_sync[id].state != SYNC_START ) { 1113 /* 1114 * Nope, we've already negotiated. 1115 * Now see if we should allow the target to disconnect/reselect... 1116 */ 1117 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 1118 !sbic_enable_reselect ) 1119 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1120 else 1121 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1122 1123 } else { 1124 /* 1125 * try to initiate a sync transfer. 1126 * So compose the sync message we're going 1127 * to send to the target 1128 */ 1129 #ifdef DEBUG 1130 if ( sync_debug ) 1131 printf("\nSending sync request to target %d ... ", id); 1132 #endif 1133 /* 1134 * setup scsi message sync message request 1135 */ 1136 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1137 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1138 dev->sc_msg[2] = 3; 1139 dev->sc_msg[3] = MSG_SYNC_REQ; 1140 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1141 dev->sc_msg[5] = sbic_max_offset; 1142 1143 sbicxfout(regs, 6, dev->sc_msg); 1144 1145 dev->sc_sync[id].state = SYNC_SENT; 1146 #ifdef DEBUG 1147 if ( sync_debug ) 1148 printf ("sent\n"); 1149 #endif 1150 } 1151 1152 /* 1153 * There's one interrupt still to come: the change to CMD phase... 1154 */ 1155 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1156 GET_SBIC_csr(regs, csr); 1157 } 1158 1159 /* 1160 * set sync or async 1161 */ 1162 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1163 #ifdef DEBUG 1164 if ( sync_debug ) 1165 printf("select(%d): sync reg = 0x%02x\n", target, 1166 SBIC_SYN(dev->sc_sync[target].offset, 1167 dev->sc_sync[target].period)); 1168 #endif 1169 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1170 dev->sc_sync[target].period)); 1171 } else { 1172 #ifdef DEBUG 1173 if ( sync_debug ) 1174 printf("select(%d): sync reg = 0x%02x\n", target, 1175 SBIC_SYN(0,sbic_min_period)); 1176 #endif 1177 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1178 } 1179 1180 return csr; 1181 } 1182 1183 /* 1184 * Information Transfer *to* a Scsi Target. 1185 * 1186 * Note: Don't expect there to be an interrupt immediately after all 1187 * the data is transferred out. The WD spec sheet says that the Transfer- 1188 * Info command for non-MSG_IN phases only completes when the target 1189 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1190 * 1191 * This can have a nasty effect on commands which take a relatively long 1192 * time to complete, for example a START/STOP unit command may remain in 1193 * CMD phase until the disk has spun up. Only then will the target change 1194 * to STATUS phase. This is really only a problem for immediate commands 1195 * since we don't allow disconnection for them (yet). 1196 */ 1197 int 1198 sbicxfout(regs, len, bp) 1199 sbic_regmap_p regs; 1200 int len; 1201 void *bp; 1202 { 1203 int wait = sbic_data_wait; 1204 u_char asr, 1205 *buf = bp; 1206 1207 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1208 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1209 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1210 1211 /* 1212 * sigh.. WD-PROTO strikes again.. sending the command in one go 1213 * causes the chip to lock up if talking to certain (misbehaving?) 1214 * targets. Anyway, this procedure should work for all targets, but 1215 * it's slightly slower due to the overhead 1216 */ 1217 WAIT_CIP (regs); 1218 1219 SBIC_TC_PUT (regs, 0); 1220 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1221 SBIC_TC_PUT (regs, (unsigned)len); 1222 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1223 1224 /* 1225 * Loop for each byte transferred 1226 */ 1227 do { 1228 1229 GET_SBIC_asr (regs, asr); 1230 1231 if ( asr & SBIC_ASR_DBR ) { 1232 if ( len ) { 1233 SET_SBIC_data (regs, *buf); 1234 buf++; 1235 len--; 1236 } else { 1237 SET_SBIC_data (regs, 0); 1238 } 1239 wait = sbic_data_wait; 1240 } 1241 1242 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1243 1244 #ifdef DEBUG 1245 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1246 #endif 1247 1248 /* 1249 * Normally, an interrupt will be pending when this routing returns. 1250 */ 1251 return(len); 1252 } 1253 1254 /* 1255 * Information Transfer *from* a Scsi Target 1256 * returns # bytes left to read 1257 */ 1258 int 1259 sbicxfin(regs, len, bp) 1260 sbic_regmap_p regs; 1261 int len; 1262 void *bp; 1263 { 1264 int wait = sbic_data_wait; 1265 u_char *buf = bp; 1266 u_char asr; 1267 #ifdef DEBUG 1268 u_char *obp = bp; 1269 #endif 1270 1271 WAIT_CIP (regs); 1272 1273 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1274 SBIC_TC_PUT (regs, (unsigned)len); 1275 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1276 1277 /* 1278 * Loop for each byte transferred 1279 */ 1280 do { 1281 1282 GET_SBIC_asr (regs, asr); 1283 1284 if ( asr & SBIC_ASR_DBR ) { 1285 if ( len ) { 1286 GET_SBIC_data (regs, *buf); 1287 buf++; 1288 len--; 1289 } else { 1290 u_char foo; 1291 GET_SBIC_data (regs, foo); 1292 } 1293 wait = sbic_data_wait; 1294 } 1295 1296 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1297 1298 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1299 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1300 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1301 1302 SBIC_TC_PUT (regs, 0); 1303 1304 /* 1305 * this leaves with one csr to be read 1306 */ 1307 return len; 1308 } 1309 1310 /* 1311 * SCSI 'immediate' command: issue a command to some SCSI device 1312 * and get back an 'immediate' response (i.e., do programmed xfer 1313 * to get the response data). 'cbuf' is a buffer containing a scsi 1314 * command of length clen bytes. 'buf' is a buffer of length 'len' 1315 * bytes for data. The transfer direction is determined by the device 1316 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1317 * command must supply no data. 1318 * 1319 * Note that although this routine looks like it can handle disconnect/ 1320 * reselect, the fact is that it can't. There is still some work to be 1321 * done to clean this lot up. 1322 */ 1323 int 1324 sbicicmd(dev, cbuf, clen, buf, len) 1325 struct sbic_softc *dev; 1326 void *cbuf, 1327 *buf; 1328 int clen, 1329 len; 1330 { 1331 sbic_regmap_p regs = dev->sc_sbicp; 1332 struct sbic_acb *acb = dev->sc_nexus; 1333 u_char csr, 1334 asr; 1335 int still_busy = SBIC_STATE_RUNNING; 1336 1337 /* 1338 * Make sure pointers are OK 1339 */ 1340 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1341 dev->sc_tcnt = acb->sc_tcnt = 0; 1342 1343 acb->sc_dmacmd = 0; 1344 acb->sc_pa.dc_count = 0; /* No DMA */ 1345 acb->sc_kv.dc_addr = buf; 1346 acb->sc_kv.dc_count = len; 1347 1348 #ifdef DEBUG 1349 if ( data_pointer_debug > 1 ) 1350 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1351 #endif 1352 1353 /* 1354 * set the sbic into non-DMA mode 1355 */ 1356 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1357 1358 dev->sc_stat[0] = 0xff; 1359 dev->sc_msg[0] = 0xff; 1360 1361 /* 1362 * We're stealing the SCSI bus 1363 */ 1364 dev->sc_flags |= SBICF_ICMD; 1365 1366 do { 1367 GET_SBIC_asr (regs, asr); 1368 1369 /* 1370 * select the SCSI bus (it's an error if bus isn't free) 1371 */ 1372 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1373 still_busy != SBIC_STATE_DISCONNECT ) { 1374 if ( (csr = sbicselectbus(dev)) == 0 ) { 1375 dev->sc_flags &= ~SBICF_ICMD; 1376 return(-1); 1377 } 1378 } else 1379 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1380 GET_SBIC_csr(regs, csr); 1381 else 1382 csr = 0; 1383 1384 if ( csr ) { 1385 1386 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1387 1388 switch ( csr ) { 1389 1390 case SBIC_CSR_S_XFERRED: 1391 case SBIC_CSR_DISC: 1392 case SBIC_CSR_DISC_1: 1393 { 1394 u_char phase; 1395 1396 dev->sc_flags &= ~SBICF_SELECTED; 1397 GET_SBIC_cmd_phase (regs, phase); 1398 1399 if ( phase == 0x60 ) { 1400 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1401 still_busy = SBIC_STATE_DONE; /* done */ 1402 } else { 1403 #ifdef DEBUG 1404 if ( reselect_debug > 1 ) 1405 printf("sbicicmd: handling disconnect\n"); 1406 #endif 1407 still_busy = SBIC_STATE_DISCONNECT; 1408 } 1409 } 1410 break; 1411 1412 case SBIC_CSR_XFERRED | CMD_PHASE: 1413 case SBIC_CSR_MIS | CMD_PHASE: 1414 case SBIC_CSR_MIS_1 | CMD_PHASE: 1415 case SBIC_CSR_MIS_2 | CMD_PHASE: 1416 { 1417 if ( sbicxfout(regs, clen, cbuf) ) 1418 still_busy = sbicabort(dev, "icmd sending cmd"); 1419 } 1420 break; 1421 1422 case SBIC_CSR_XFERRED | STATUS_PHASE: 1423 case SBIC_CSR_MIS | STATUS_PHASE: 1424 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1425 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1426 { 1427 /* 1428 * The sbic does the status/cmd-complete reading ok, 1429 * so do this with its hi-level commands. 1430 */ 1431 #ifdef DEBUG 1432 if ( sbic_debug ) 1433 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1434 #endif 1435 SET_SBIC_cmd_phase(regs, 0x46); 1436 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1437 } 1438 break; 1439 1440 default: 1441 { 1442 still_busy = sbicnextstate(dev, csr, asr); 1443 } 1444 break; 1445 } 1446 1447 /* 1448 * make sure the last command was taken, 1449 * ie. we're not hunting after an ignored command.. 1450 */ 1451 GET_SBIC_asr(regs, asr); 1452 1453 /* 1454 * tapes may take a loooong time.. 1455 */ 1456 while (asr & SBIC_ASR_BSY ) { 1457 1458 if ( asr & SBIC_ASR_DBR ) { 1459 int i; 1460 1461 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1462 #ifdef DDB 1463 Debugger(); 1464 #endif 1465 /* 1466 * SBIC is jammed 1467 * DUNNO which direction 1468 * Try old direction 1469 */ 1470 GET_SBIC_data(regs, i); 1471 GET_SBIC_asr(regs, asr); 1472 1473 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1474 SET_SBIC_data(regs, i); 1475 } 1476 1477 GET_SBIC_asr(regs, asr); 1478 } 1479 } 1480 1481 /* 1482 * wait for last command to complete 1483 */ 1484 if ( asr & SBIC_ASR_LCI ) { 1485 printf("sbicicmd: last command ignored\n"); 1486 } 1487 else 1488 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1489 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1490 1491 /* 1492 * do it again 1493 */ 1494 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1495 1496 /* 1497 * Sometimes we need to do an extra read of the CSR 1498 */ 1499 GET_SBIC_csr(regs, csr); 1500 1501 #ifdef DEBUG 1502 if ( data_pointer_debug > 1 ) 1503 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1504 acb->sc_kv.dc_count, 1505 dev->sc_stat[0]); 1506 #endif 1507 1508 dev->sc_flags &= ~SBICF_ICMD; 1509 1510 return(dev->sc_stat[0]); 1511 } 1512 1513 /* 1514 * Finish SCSI xfer command: After the completion interrupt from 1515 * a read/write operation, sequence through the final phases in 1516 * programmed i/o. This routine is a lot like sbicicmd except we 1517 * skip (and don't allow) the select, cmd out and data in/out phases. 1518 */ 1519 void 1520 sbicxfdone(dev) 1521 struct sbic_softc *dev; 1522 { 1523 sbic_regmap_p regs = dev->sc_sbicp; 1524 u_char phase, 1525 csr; 1526 int s; 1527 1528 QPRINTF(("{")); 1529 s = splbio(); 1530 1531 /* 1532 * have the sbic complete on its own 1533 */ 1534 SBIC_TC_PUT(regs, 0); 1535 SET_SBIC_cmd_phase(regs, 0x46); 1536 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1537 1538 do { 1539 1540 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1541 GET_SBIC_csr (regs, csr); 1542 QPRINTF(("%02x:", csr)); 1543 1544 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1545 (csr != SBIC_CSR_S_XFERRED)); 1546 1547 dev->sc_flags &= ~SBICF_SELECTED; 1548 1549 GET_SBIC_cmd_phase (regs, phase); 1550 QPRINTF(("}%02x", phase)); 1551 1552 if ( phase == 0x60 ) 1553 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1554 else 1555 sbicerror(dev, csr); 1556 1557 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1558 1559 splx(s); 1560 } 1561 1562 /* 1563 * No DMA chains 1564 */ 1565 int 1566 sbicgo(dev, xs) 1567 struct sbic_softc *dev; 1568 struct scsipi_xfer *xs; 1569 { 1570 struct sbic_acb *acb = dev->sc_nexus; 1571 sbic_regmap_p regs = dev->sc_sbicp; 1572 int i, 1573 dmaflags, 1574 count, 1575 usedma; 1576 u_char csr, 1577 asr, 1578 *addr; 1579 1580 dev->target = xs->sc_link->scsipi_scsi.target; 1581 dev->lun = xs->sc_link->scsipi_scsi.lun; 1582 1583 usedma = sbicdmaok(dev, xs); 1584 1585 #ifdef DEBUG 1586 if ( data_pointer_debug > 1 ) 1587 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1588 #endif 1589 1590 /* 1591 * select the SCSI bus (it's an error if bus isn't free) 1592 */ 1593 if ( (csr = sbicselectbus(dev)) == 0 ) 1594 return(0); /* Not done: needs to be rescheduled */ 1595 1596 dev->sc_stat[0] = 0xff; 1597 1598 /* 1599 * Calculate DMA chains now 1600 */ 1601 if ( acb->flags & ACB_DATAIN ) 1602 dmaflags = DMAGO_READ; 1603 else 1604 dmaflags = 0; 1605 1606 addr = acb->sc_kv.dc_addr; 1607 count = acb->sc_kv.dc_count; 1608 1609 if ( count && ((char *)kvtop((caddr_t)addr) != acb->sc_pa.dc_addr) ) { 1610 printf("sbic: DMA buffer mapping changed %p->%lx\n", 1611 acb->sc_pa.dc_addr, kvtop((caddr_t)addr)); 1612 #ifdef DDB 1613 Debugger(); 1614 #endif 1615 } 1616 1617 #ifdef DEBUG 1618 ++sbicdma_ops; /* count total DMA operations */ 1619 #endif 1620 1621 /* 1622 * Allocate the DMA chain 1623 * Mark end of segment... 1624 */ 1625 acb->sc_tcnt = dev->sc_tcnt = 0; 1626 acb->sc_pa.dc_count = 0; 1627 1628 sbic_load_ptrs(dev); 1629 1630 /* 1631 * Enable interrupts but don't do any DMA 1632 * enintr() also enables interrupts for the sbic 1633 */ 1634 dev->sc_enintr(dev); 1635 1636 if ( usedma ) { 1637 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1638 acb->sc_pa.dc_count, dmaflags); 1639 #ifdef DEBUG 1640 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1641 #endif 1642 } else 1643 dev->sc_dmacmd = 0; /* Don't use DMA */ 1644 1645 acb->sc_dmacmd = dev->sc_dmacmd; 1646 1647 #ifdef DEBUG 1648 if ( data_pointer_debug > 1 ) { 1649 printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, 1650 dev->sc_cur->dc_addr, 1651 dev->sc_tcnt, 1652 dev->sc_dmacmd); 1653 } 1654 #endif 1655 1656 /* 1657 * Lets cycle a while then let the interrupt handler take over. 1658 */ 1659 GET_SBIC_asr(regs, asr); 1660 1661 do { 1662 1663 QPRINTF(("go ")); 1664 1665 /* 1666 * Handle the new phase 1667 */ 1668 i = sbicnextstate(dev, csr, asr); 1669 #if 0 1670 WAIT_CIP(regs); 1671 #endif 1672 if ( i == SBIC_STATE_RUNNING ) { 1673 GET_SBIC_asr(regs, asr); 1674 1675 if ( asr & SBIC_ASR_LCI ) 1676 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1677 1678 if ( asr & SBIC_ASR_INT ) 1679 GET_SBIC_csr(regs, csr); 1680 } 1681 1682 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1683 1684 if ( i == SBIC_STATE_DONE ) { 1685 if ( dev->sc_stat[0] == 0xff ) 1686 #if 0 1687 printf("sbicgo: done & stat = 0xff\n"); 1688 #else 1689 ; 1690 #endif 1691 else 1692 return 1; /* Did we really finish that fast? */ 1693 } 1694 1695 return 0; 1696 } 1697 1698 1699 int 1700 sbicintr(dev) 1701 struct sbic_softc *dev; 1702 { 1703 sbic_regmap_p regs = dev->sc_sbicp; 1704 u_char asr, 1705 csr; 1706 int i; 1707 1708 /* 1709 * pending interrupt? 1710 */ 1711 GET_SBIC_asr (regs, asr); 1712 if ( (asr & SBIC_ASR_INT) == 0 ) 1713 return(0); 1714 1715 GET_SBIC_csr(regs, csr); 1716 1717 do { 1718 1719 QPRINTF(("intr[0x%x]", csr)); 1720 1721 i = sbicnextstate(dev, csr, asr); 1722 #if 0 1723 WAIT_CIP(regs); 1724 #endif 1725 if ( i == SBIC_STATE_RUNNING ) { 1726 GET_SBIC_asr(regs, asr); 1727 1728 if ( asr & SBIC_ASR_LCI ) 1729 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1730 1731 if ( asr & SBIC_ASR_INT ) 1732 GET_SBIC_csr(regs, csr); 1733 } 1734 1735 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1736 1737 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1738 1739 return(1); 1740 } 1741 1742 /* 1743 * Run commands and wait for disconnect. 1744 * This is only ever called when a command is in progress, when we 1745 * want to busy wait for it to finish. 1746 */ 1747 int 1748 sbicpoll(dev) 1749 struct sbic_softc *dev; 1750 { 1751 sbic_regmap_p regs = dev->sc_sbicp; 1752 u_char asr, 1753 csr; 1754 int i; 1755 1756 /* 1757 * Wait for the next interrupt 1758 */ 1759 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1760 1761 do { 1762 GET_SBIC_asr (regs, asr); 1763 1764 if ( asr & SBIC_ASR_INT ) 1765 GET_SBIC_csr(regs, csr); 1766 1767 QPRINTF(("poll[0x%x]", csr)); 1768 1769 /* 1770 * Handle it 1771 */ 1772 i = sbicnextstate(dev, csr, asr); 1773 1774 WAIT_CIP(regs); 1775 GET_SBIC_asr(regs, asr); 1776 1777 /* 1778 * tapes may take a loooong time.. 1779 */ 1780 while ( asr & SBIC_ASR_BSY ) { 1781 u_char z = 0; 1782 1783 if ( asr & SBIC_ASR_DBR ) { 1784 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1785 #ifdef DDB 1786 Debugger(); 1787 #endif 1788 /* 1789 * SBIC is jammed 1790 * DUNNO which direction 1791 * Try old direction 1792 */ 1793 GET_SBIC_data(regs, z); 1794 GET_SBIC_asr(regs, asr); 1795 1796 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1797 SET_SBIC_data(regs, z); 1798 } 1799 1800 GET_SBIC_asr(regs, asr); 1801 } 1802 1803 if ( asr & SBIC_ASR_LCI ) 1804 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1805 else 1806 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1807 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1808 1809 } while ( i == SBIC_STATE_RUNNING ); 1810 1811 return(1); 1812 } 1813 1814 /* 1815 * Handle a single msgin 1816 */ 1817 int 1818 sbicmsgin(dev) 1819 struct sbic_softc *dev; 1820 { 1821 sbic_regmap_p regs = dev->sc_sbicp; 1822 int recvlen = 1; 1823 u_char asr, 1824 csr, 1825 *tmpaddr, 1826 *msgaddr; 1827 1828 tmpaddr = msgaddr = dev->sc_msg; 1829 1830 tmpaddr[0] = 0xff; 1831 tmpaddr[1] = 0xff; 1832 1833 GET_SBIC_asr(regs, asr); 1834 1835 #ifdef DEBUG 1836 if ( reselect_debug > 1 ) 1837 printf("sbicmsgin asr=%02x\n", asr); 1838 #endif 1839 1840 GET_SBIC_selid (regs, csr); 1841 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1842 1843 SBIC_TC_PUT(regs, 0); 1844 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1845 1846 do { 1847 while( recvlen-- ) { 1848 1849 /* 1850 * Fetch the next byte of the message 1851 */ 1852 RECV_BYTE(regs, *tmpaddr); 1853 1854 /* 1855 * get the command completion interrupt, or we 1856 * can't send a new command (LCI) 1857 */ 1858 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1859 GET_SBIC_csr(regs, csr); 1860 1861 #ifdef DEBUG 1862 if ( reselect_debug > 1 ) 1863 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1864 #endif 1865 1866 tmpaddr++; 1867 1868 if ( recvlen ) { 1869 /* 1870 * Clear ACK, and wait for the interrupt for the next byte 1871 */ 1872 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1873 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1874 GET_SBIC_csr(regs, csr); 1875 } 1876 } 1877 1878 if ( msgaddr[0] == 0xff ) { 1879 printf("sbicmsgin: sbic swallowed our message\n"); 1880 break; 1881 } 1882 1883 #ifdef DEBUG 1884 if ( sync_debug ) { 1885 GET_SBIC_asr(regs, asr); 1886 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1887 } 1888 #endif 1889 /* 1890 * test whether this is a reply to our sync 1891 * request 1892 */ 1893 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1894 1895 /* 1896 * Got IFFY msg -- ack it 1897 */ 1898 QPRINTF(("IFFY")); 1899 1900 } else 1901 if ( msgaddr[0] == MSG_REJECT && 1902 dev->sc_sync[dev->target].state == SYNC_SENT) { 1903 1904 /* 1905 * Target probably rejected our Sync negotiation. 1906 */ 1907 QPRINTF(("REJECT of SYN")); 1908 1909 #ifdef DEBUG 1910 if ( sync_debug ) 1911 printf("target %d rejected sync, going async\n", dev->target); 1912 #endif 1913 1914 dev->sc_sync[dev->target].period = sbic_min_period; 1915 dev->sc_sync[dev->target].offset = 0; 1916 dev->sc_sync[dev->target].state = SYNC_DONE; 1917 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1918 dev->sc_sync[dev->target].period)); 1919 1920 } else 1921 if ( msgaddr[0] == MSG_REJECT ) { 1922 1923 /* 1924 * we'll never REJECt a REJECT message.. 1925 */ 1926 QPRINTF(("REJECT")); 1927 1928 } else 1929 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1930 1931 /* 1932 * don't reject this either. 1933 */ 1934 QPRINTF(("MSG_SAVE_DATA_PTR")); 1935 1936 } else 1937 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1938 1939 /* 1940 * don't reject this either. 1941 */ 1942 QPRINTF(("MSG_RESTORE_PTR")); 1943 1944 } else 1945 if ( msgaddr[0] == MSG_DISCONNECT ) { 1946 1947 /* 1948 * Target is disconnecting... 1949 */ 1950 QPRINTF(("DISCONNECT")); 1951 1952 #ifdef DEBUG 1953 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1954 printf("sbicmsgin: got disconnect msg %s\n", 1955 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1956 #endif 1957 1958 if ( dev->sc_flags & SBICF_ICMD ) { 1959 /* 1960 * We're in immediate mode. Prevent disconnects. 1961 * prepare to reject the message, NACK 1962 */ 1963 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1964 WAIT_CIP(regs); 1965 } 1966 1967 } else 1968 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1969 1970 /* 1971 * !! KLUDGE ALERT !! quite a few drives don't seem to 1972 * really like the current way of sending the 1973 * sync-handshake together with the ident-message, and 1974 * they react by sending command-complete and 1975 * disconnecting right after returning the valid sync 1976 * handshake. So, all I can do is reselect the drive, 1977 * and hope it won't disconnect again. I don't think 1978 * this is valid behavior, but I can't help fixing a 1979 * problem that apparently exists. 1980 * 1981 * Note: we should not get here on `normal' command 1982 * completion, as that condition is handled by the 1983 * high-level sel&xfer resume command used to walk 1984 * thru status/cc-phase. 1985 */ 1986 QPRINTF(("CMD_COMPLETE")); 1987 1988 #ifdef DEBUG 1989 if ( sync_debug ) 1990 printf ("GOT MSG %d! target %d acting weird.." 1991 " waiting for disconnect...\n", msgaddr[0], dev->target); 1992 #endif 1993 1994 /* 1995 * Check to see if sbic is handling this 1996 */ 1997 GET_SBIC_asr(regs, asr); 1998 1999 /* 2000 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 2001 */ 2002 if ( asr & SBIC_ASR_BSY ) 2003 return SBIC_STATE_RUNNING; 2004 2005 /* 2006 * Let's try this: Assume it works and set status to 00 2007 */ 2008 dev->sc_stat[0] = 0; 2009 2010 } else 2011 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 2012 2013 /* 2014 * Target is sending us an extended message. We'll assume it's 2015 * the response to our Sync. negotiation. 2016 */ 2017 QPRINTF(("ExtMSG\n")); 2018 2019 /* 2020 * Read in whole extended message. First, negate ACK to accept 2021 * the MSG_EXT_MESSAGE byte... 2022 */ 2023 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2024 2025 /* 2026 * Wait for the interrupt for the next byte (length) 2027 */ 2028 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2029 GET_SBIC_csr(regs, csr); 2030 2031 #ifdef DEBUG 2032 QPRINTF(("CLR ACK csr %02x\n", csr)); 2033 #endif 2034 2035 /* 2036 * Read the length byte 2037 */ 2038 RECV_BYTE(regs, *tmpaddr); 2039 2040 /* 2041 * Wait for command completion IRQ 2042 */ 2043 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2044 GET_SBIC_csr(regs, csr); 2045 2046 /* 2047 * Reload the loop counter 2048 */ 2049 recvlen = *tmpaddr++; 2050 2051 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2052 2053 } else 2054 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2055 msgaddr[2] == MSG_SYNC_REQ ) { 2056 2057 /* 2058 * We've received the complete Extended Message Sync. Request... 2059 */ 2060 QPRINTF(("SYN")); 2061 2062 /* 2063 * Compute the required Transfer Period for the WD chip... 2064 */ 2065 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2066 dev->sc_sync[dev->target].offset = msgaddr[4]; 2067 dev->sc_sync[dev->target].state = SYNC_DONE; 2068 2069 /* 2070 * Put the WD chip in synchronous mode 2071 */ 2072 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2073 dev->sc_sync[dev->target].period)); 2074 #ifdef DEBUG 2075 if ( sync_debug ) 2076 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2077 SBIC_SYN(dev->sc_sync[dev->target].offset, 2078 dev->sc_sync[dev->target].period)); 2079 #endif 2080 2081 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2082 dev->sc_dev.dv_xname, dev->target, 2083 msgaddr[3] * 4, msgaddr[4]); 2084 2085 } else { 2086 2087 /* 2088 * We don't support whatever this message is... 2089 */ 2090 #ifdef DEBUG 2091 if ( sbic_debug || sync_debug ) 2092 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2093 #endif 2094 2095 /* 2096 * prepare to reject the message, NACK 2097 */ 2098 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2099 WAIT_CIP(regs); 2100 } 2101 2102 /* 2103 * Negate ACK to complete the transfer 2104 */ 2105 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2106 2107 /* 2108 * Wait for the interrupt for the next byte, or phase change. 2109 * Only read the CSR if we have more data to transfer. 2110 * XXXSCW: We should really verify that we're still in MSG IN phase 2111 * before blindly going back around this loop, but that would mean 2112 * we read the CSR... <sigh> 2113 */ 2114 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2115 if ( recvlen > 0 ) 2116 GET_SBIC_csr(regs, csr); 2117 2118 } while ( recvlen > 0 ); 2119 2120 /* 2121 * Should still have one CSR to read 2122 */ 2123 return SBIC_STATE_RUNNING; 2124 } 2125 2126 2127 /* 2128 * sbicnextstate() 2129 * return: 2130 * SBIC_STATE_DONE == done 2131 * SBIC_STATE_RUNNING == working 2132 * SBIC_STATE_DISCONNECT == disconnected 2133 * SBIC_STATE_ERROR == error 2134 */ 2135 int 2136 sbicnextstate(dev, csr, asr) 2137 struct sbic_softc *dev; 2138 u_char csr, 2139 asr; 2140 { 2141 sbic_regmap_p regs = dev->sc_sbicp; 2142 struct sbic_acb *acb = dev->sc_nexus; 2143 2144 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2145 2146 switch (csr) { 2147 2148 case SBIC_CSR_XFERRED | CMD_PHASE: 2149 case SBIC_CSR_MIS | CMD_PHASE: 2150 case SBIC_CSR_MIS_1 | CMD_PHASE: 2151 case SBIC_CSR_MIS_2 | CMD_PHASE: 2152 { 2153 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2154 goto abort; 2155 } 2156 break; 2157 2158 case SBIC_CSR_XFERRED | STATUS_PHASE: 2159 case SBIC_CSR_MIS | STATUS_PHASE: 2160 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2161 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2162 { 2163 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2164 2165 /* 2166 * this should be the normal i/o completion case. 2167 * get the status & cmd complete msg then let the 2168 * device driver look at what happened. 2169 */ 2170 sbicxfdone(dev); 2171 2172 #ifdef DEBUG 2173 dev->sc_dmatimo = 0; 2174 if ( data_pointer_debug > 1 ) 2175 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2176 dev->sc_cur->dc_addr, 2177 dev->sc_tcnt); 2178 #endif 2179 /* 2180 * Stop the DMA chip 2181 */ 2182 dev->sc_dmastop(dev); 2183 2184 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2185 2186 /* 2187 * Indicate to the upper layers that the command is done 2188 */ 2189 sbic_scsidone(acb, dev->sc_stat[0]); 2190 2191 return SBIC_STATE_DONE; 2192 } 2193 2194 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2195 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2196 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2197 case SBIC_CSR_MIS | DATA_IN_PHASE: 2198 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2199 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2200 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2201 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2202 { 2203 /* 2204 * Verify that we expected to transfer data... 2205 */ 2206 if ( acb->sc_kv.dc_count <= 0 ) { 2207 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2208 acb->sc_kv.dc_count, asr, csr); 2209 goto abort; 2210 } 2211 2212 /* 2213 * Should we transfer using PIO or DMA ? 2214 */ 2215 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2216 acb->sc_dmacmd == 0 ) { 2217 2218 /* 2219 * Do PIO transfer 2220 */ 2221 int i; 2222 2223 #ifdef DEBUG 2224 if ( data_pointer_debug > 1 ) 2225 printf("next PIO: %d(%p:%x)\n", dev->target, 2226 acb->sc_kv.dc_addr, 2227 acb->sc_kv.dc_count); 2228 #endif 2229 2230 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2231 /* 2232 * data in 2233 */ 2234 i = sbicxfin(regs, acb->sc_kv.dc_count, 2235 acb->sc_kv.dc_addr); 2236 else 2237 /* 2238 * data out 2239 */ 2240 i = sbicxfout(regs, acb->sc_kv.dc_count, 2241 acb->sc_kv.dc_addr); 2242 2243 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2244 acb->sc_kv.dc_count = i; 2245 2246 /* 2247 * Update current count... 2248 */ 2249 acb->sc_tcnt = dev->sc_tcnt = i; 2250 2251 dev->sc_flags &= ~SBICF_INDMA; 2252 2253 } else { 2254 2255 /* 2256 * Do DMA transfer 2257 * set next dma addr and dec count 2258 */ 2259 sbic_save_ptrs(dev); 2260 sbic_load_ptrs(dev); 2261 2262 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2263 SBIC_MACHINE_DMA_MODE); 2264 2265 #ifdef DEBUG 2266 dev->sc_dmatimo = 1; 2267 if ( data_pointer_debug > 1 ) 2268 printf("next DMA: %d(%p:%lx)\n", dev->target, 2269 dev->sc_cur->dc_addr, 2270 dev->sc_tcnt); 2271 #endif 2272 /* 2273 * Start the DMA chip going 2274 */ 2275 dev->sc_tcnt = dev->sc_dmanext(dev); 2276 2277 /* 2278 * Tell the WD chip how much to transfer this time around 2279 */ 2280 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2281 2282 /* 2283 * Start the transfer 2284 */ 2285 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2286 2287 /* 2288 * Indicate that we're in DMA mode 2289 */ 2290 dev->sc_flags |= SBICF_INDMA; 2291 } 2292 } 2293 break; 2294 2295 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2296 case SBIC_CSR_MIS | MESG_IN_PHASE: 2297 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2298 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2299 { 2300 sbic_save_ptrs(dev); 2301 2302 /* 2303 * Handle a single message in... 2304 */ 2305 return sbicmsgin(dev); 2306 } 2307 2308 case SBIC_CSR_MSGIN_W_ACK: 2309 { 2310 /* 2311 * We should never see this since it's handled in 'sbicmsgin()' 2312 * but just for the sake of paranoia... 2313 */ 2314 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2315 printf("Acking unknown msgin CSR:%02x",csr); 2316 } 2317 break; 2318 2319 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2320 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2321 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2322 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2323 { 2324 /* 2325 * We only ever handle a message out phase here for sending a 2326 * REJECT message. 2327 */ 2328 sbic_save_ptrs(dev); 2329 2330 #ifdef DEBUG 2331 if (sync_debug) 2332 printf ("sending REJECT msg to last msg.\n"); 2333 #endif 2334 2335 SEND_BYTE(regs, MSG_REJECT); 2336 WAIT_CIP(regs); 2337 } 2338 break; 2339 2340 case SBIC_CSR_DISC: 2341 case SBIC_CSR_DISC_1: 2342 { 2343 /* 2344 * Try to schedule another target 2345 */ 2346 sbic_save_ptrs(dev); 2347 2348 dev->sc_flags &= ~SBICF_SELECTED; 2349 2350 #ifdef DEBUG 2351 if ( reselect_debug > 1 ) 2352 printf("sbicnext target %d disconnected\n", dev->target); 2353 #endif 2354 2355 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2356 2357 ++dev->sc_tinfo[dev->target].dconns; 2358 2359 dev->sc_nexus = NULL; 2360 dev->sc_xs = NULL; 2361 2362 if ( acb->xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2363 !sbic_parallel_operations ) 2364 return SBIC_STATE_DISCONNECT; 2365 2366 QPRINTF(("sbicnext: calling sbic_sched\n")); 2367 2368 sbic_sched(dev); 2369 2370 QPRINTF(("sbicnext: sbic_sched returned\n")); 2371 2372 return SBIC_STATE_DISCONNECT; 2373 } 2374 2375 case SBIC_CSR_RSLT_NI: 2376 case SBIC_CSR_RSLT_IFY: 2377 { 2378 /* 2379 * A reselection. 2380 * Note that since we don't enable Advanced Features (assuming 2381 * the WD chip is at least the 'A' revision), we're only ever 2382 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2383 * hell of it, we'll handle it anyway, for all the extra code 2384 * it needs... 2385 */ 2386 u_char newtarget, 2387 newlun; 2388 2389 GET_SBIC_rselid(regs, newtarget); 2390 2391 /* 2392 * check SBIC_RID_SIV? 2393 */ 2394 newtarget &= SBIC_RID_MASK; 2395 2396 if ( csr == SBIC_CSR_RSLT_IFY ) { 2397 2398 /* 2399 * Read Identify msg to avoid lockup 2400 */ 2401 GET_SBIC_data(regs, newlun); 2402 WAIT_CIP(regs); 2403 newlun &= SBIC_TLUN_MASK; 2404 2405 } else { 2406 2407 /* 2408 * Need to read Identify message the hard way, assuming 2409 * the target even sends us one... 2410 */ 2411 for (newlun = 255; newlun; --newlun) { 2412 GET_SBIC_asr(regs, asr); 2413 if (asr & SBIC_ASR_INT) 2414 break; 2415 delay(10); 2416 } 2417 2418 /* 2419 * If we didn't get an interrupt, somethink's up 2420 */ 2421 if ( (asr & SBIC_ASR_INT) == 0 ) { 2422 printf("%s: Reselect without identify? asr %x\n", 2423 dev->sc_dev.dv_xname, asr); 2424 newlun = 0; /* XXXX */ 2425 } else { 2426 /* 2427 * We got an interrupt, verify that it's a change to 2428 * message in phase, and if so read the message. 2429 */ 2430 GET_SBIC_csr(regs,csr); 2431 2432 if ( csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2433 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2434 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE) ) { 2435 /* 2436 * Yup, gone to message in. Fetch the target LUN 2437 */ 2438 sbicmsgin(dev); 2439 newlun = dev->sc_msg[0] & 0x07; 2440 2441 } else { 2442 /* 2443 * Whoops! Target didn't go to message in phase!! 2444 */ 2445 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2446 newlun = 0; /* XXXSCW */ 2447 } 2448 } 2449 } 2450 2451 /* 2452 * Ok, we have the identity of the reselecting target. 2453 */ 2454 #ifdef DEBUG 2455 if ( reselect_debug > 1 || 2456 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2457 printf("sbicnext: reselect %s from targ %d lun %d\n", 2458 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2459 } 2460 #endif 2461 2462 if ( dev->sc_nexus ) { 2463 /* 2464 * Whoops! We've been reselected with an command in progress! 2465 * The best we can do is to put the current command back on the 2466 * ready list and hope for the best. 2467 */ 2468 #ifdef DEBUG 2469 if ( reselect_debug > 1 ) { 2470 printf("%s: reselect %s with active command\n", 2471 dev->sc_dev.dv_xname, 2472 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2473 } 2474 #endif 2475 2476 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2477 2478 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2479 2480 dev->sc_nexus = NULL; 2481 dev->sc_xs = NULL; 2482 } 2483 2484 /* 2485 * Reload sync values for this target 2486 */ 2487 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2488 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2489 dev->sc_sync[newtarget].period)); 2490 else 2491 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2492 2493 /* 2494 * Loop through the nexus list until we find the saved entry 2495 * for the reselecting target... 2496 */ 2497 for (acb = dev->nexus_list.tqh_first; acb; 2498 acb = acb->chain.tqe_next) { 2499 2500 if ( acb->xs->sc_link->scsipi_scsi.target == newtarget && 2501 acb->xs->sc_link->scsipi_scsi.lun == newlun) { 2502 /* 2503 * We've found the saved entry. Dequeue it, and 2504 * make it current again. 2505 */ 2506 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2507 2508 dev->sc_nexus = acb; 2509 dev->sc_xs = acb->xs; 2510 dev->sc_flags |= SBICF_SELECTED; 2511 dev->target = newtarget; 2512 dev->lun = newlun; 2513 break; 2514 } 2515 } 2516 2517 if ( acb == NULL ) { 2518 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2519 dev->sc_dev.dv_xname, 2520 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2521 &dev->nexus_list.tqh_first); 2522 panic("bad reselect in sbic"); 2523 } 2524 2525 if ( csr == SBIC_CSR_RSLT_IFY ) 2526 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2527 } 2528 break; 2529 2530 default: 2531 abort: 2532 { 2533 /* 2534 * Something unexpected happened -- deal with it. 2535 */ 2536 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2537 2538 #ifdef DDB 2539 Debugger(); 2540 #endif 2541 2542 #ifdef DEBUG 2543 dev->sc_dmatimo = 0; 2544 if ( data_pointer_debug > 1 ) 2545 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2546 dev->sc_cur->dc_addr, 2547 dev->sc_tcnt); 2548 #endif 2549 2550 dev->sc_dmastop(dev); 2551 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2552 if ( dev->sc_xs ) sbicerror(dev, csr); 2553 sbicabort(dev, "next"); 2554 2555 if ( dev->sc_flags & SBICF_INDMA ) { 2556 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2557 2558 #ifdef DEBUG 2559 dev->sc_dmatimo = 0; 2560 if ( data_pointer_debug > 1 ) 2561 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2562 dev->sc_cur->dc_addr, 2563 dev->sc_tcnt); 2564 #endif 2565 sbic_scsidone(acb, -1); 2566 } 2567 2568 return SBIC_STATE_ERROR; 2569 } 2570 } 2571 2572 return(SBIC_STATE_RUNNING); 2573 } 2574 2575 2576 /* 2577 * Check if DMA can not be used with specified buffer 2578 */ 2579 int 2580 sbiccheckdmap(bp, len, mask) 2581 void *bp; 2582 u_long len, 2583 mask; 2584 { 2585 u_char *buffer; 2586 u_long phy_buf; 2587 u_long phy_len; 2588 2589 buffer = bp; 2590 2591 if ( len == 0 ) 2592 return(1); 2593 2594 while ( len ) { 2595 2596 phy_buf = kvtop((caddr_t)buffer); 2597 phy_len = NBPG - ((int) buffer & PGOFSET); 2598 2599 if ( len < phy_len ) 2600 phy_len = len; 2601 2602 if ( phy_buf & mask ) 2603 return(1); 2604 2605 buffer += phy_len; 2606 len -= phy_len; 2607 } 2608 2609 return(0); 2610 } 2611 2612 int 2613 sbictoscsiperiod(dev, a) 2614 struct sbic_softc *dev; 2615 int a; 2616 { 2617 unsigned int fs; 2618 2619 /* 2620 * cycle = DIV / (2 * CLK) 2621 * DIV = FS + 2 2622 * best we can do is 200ns at 20Mhz, 2 cycles 2623 */ 2624 2625 GET_SBIC_myid(dev->sc_sbicp, fs); 2626 2627 fs = (fs >> 6) + 2; /* DIV */ 2628 2629 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2630 2631 if ( a < 2 ) 2632 a = 8; /* map to Cycles */ 2633 2634 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2635 } 2636 2637 int 2638 sbicfromscsiperiod(dev, p) 2639 struct sbic_softc *dev; 2640 int p; 2641 { 2642 unsigned fs, 2643 ret; 2644 2645 /* 2646 * Just the inverse of the above 2647 */ 2648 GET_SBIC_myid(dev->sc_sbicp, fs); 2649 2650 fs = (fs >> 6) + 2; /* DIV */ 2651 2652 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2653 2654 ret = p << 2; /* in ns units */ 2655 ret = ret / fs; /* in Cycles */ 2656 2657 if ( ret < sbic_min_period ) 2658 return(sbic_min_period); 2659 2660 /* 2661 * verify rounding 2662 */ 2663 if ( sbictoscsiperiod(dev, ret) < p ) 2664 ret++; 2665 2666 return( (ret >= 8) ? 0 : ret ); 2667 } 2668 2669 #ifdef DEBUG 2670 void 2671 sbictimeout(dev) 2672 struct sbic_softc *dev; 2673 { 2674 int s, 2675 asr; 2676 2677 s = splbio(); 2678 2679 if ( dev->sc_dmatimo ) { 2680 2681 if ( dev->sc_dmatimo > 1 ) { 2682 2683 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2684 dev->sc_dmatimo - 1); 2685 2686 GET_SBIC_asr(dev->sc_sbicp, asr); 2687 2688 if ( asr & SBIC_ASR_INT ) { 2689 /* 2690 * We need to service a missed IRQ 2691 */ 2692 sbicintr(dev); 2693 } else { 2694 (void) sbicabort(dev, "timeout"); 2695 splx(s); 2696 return; 2697 } 2698 } 2699 2700 dev->sc_dmatimo++; 2701 } 2702 2703 splx(s); 2704 2705 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 2706 } 2707 #endif 2708
Indexes created Tue Sep 30 11:09:46 GMT 2025