sbic.c revision 1.15
1 /* $NetBSD: sbic.c,v 1.15 2000/06/29 08:04:03 mrg Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 #include "opt_ddb.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/kernel.h> /* For hz */ 61 #include <sys/disklabel.h> 62 #include <sys/dkstat.h> 63 #include <sys/buf.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <uvm/uvm_extern.h> 70 71 #include <mvme68k/mvme68k/isr.h> 72 #include <mvme68k/dev/dmavar.h> 73 #include <mvme68k/dev/sbicreg.h> 74 #include <mvme68k/dev/sbicvar.h> 75 76 77 /* 78 * Since I can't find this in any other header files 79 */ 80 #define SCSI_PHASE(reg) (reg&0x07) 81 82 /* 83 * SCSI delays 84 * In u-seconds, primarily for state changes on the SPC. 85 */ 86 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 87 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 88 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 89 90 /* 91 * Convenience macro for waiting for a particular sbic event 92 */ 93 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 94 95 extern paddr_t kvtop __P((caddr_t)); 96 97 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 98 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 99 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 100 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 101 int sbiccheckdmap __P((void *, u_long, u_long)); 102 u_char sbicselectbus __P((struct sbic_softc *)); 103 int sbicxfout __P((sbic_regmap_p, int, void *)); 104 int sbicxfin __P((sbic_regmap_p, int, void *)); 105 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 106 int sbictoscsiperiod __P((struct sbic_softc *, int)); 107 int sbicpoll __P((struct sbic_softc *)); 108 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 109 int sbicmsgin __P((struct sbic_softc *)); 110 int sbicabort __P((struct sbic_softc *, char *)); 111 void sbicxfdone __P((struct sbic_softc *)); 112 void sbicerror __P((struct sbic_softc *,u_char)); 113 void sbicreset __P((struct sbic_softc *)); 114 void sbic_scsidone __P((struct sbic_acb *, int)); 115 void sbic_sched __P((struct sbic_softc *)); 116 void sbic_save_ptrs __P((struct sbic_softc *)); 117 void sbic_load_ptrs __P((struct sbic_softc *)); 118 119 /* 120 * Synch xfer parameters, and timing conversions 121 */ 122 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 123 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 124 int sbic_cmd_wait = SBIC_CMD_WAIT; 125 int sbic_data_wait = SBIC_DATA_WAIT; 126 int sbic_init_wait = SBIC_INIT_WAIT; 127 128 /* 129 * was broken before.. now if you want this you get it for all drives 130 * on sbic controllers. 131 */ 132 u_char sbic_inhibit_sync[8]; 133 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 134 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 135 int sbic_parallel_operations = 1; /* Allow command queues */ 136 137 /* 138 * Some useful stuff for debugging purposes 139 */ 140 #ifdef DEBUG 141 int sbicdma_ops = 0; /* total DMA operations */ 142 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 143 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 144 int sbicdma_saves = 0; 145 146 #define QPRINTF(a) if (sbic_debug > 1) printf a 147 148 int sbic_debug = 0; /* Debug all chip related things */ 149 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 150 int reselect_debug = 0; /* Debug all reselection related things */ 151 int report_sense = 0; /* Always print Sense information */ 152 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 153 154 void sbictimeout __P((struct sbic_softc *dev)); 155 156 #else 157 #define QPRINTF(a) /* */ 158 #endif 159 160 161 /* 162 * default minphys routine for sbic based controllers 163 */ 164 void 165 sbic_minphys(bp) 166 struct buf *bp; 167 { 168 /* 169 * No max transfer at this level. 170 */ 171 minphys(bp); 172 } 173 174 175 /* 176 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 177 */ 178 void 179 sbic_save_ptrs(dev) 180 struct sbic_softc *dev; 181 { 182 sbic_regmap_p regs; 183 struct sbic_acb* acb; 184 int count, 185 asr, 186 s; 187 188 /* 189 * Only need to save pointers if DMA was active... 190 */ 191 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 192 return; 193 194 regs = dev->sc_sbicp; 195 196 s = splbio(); 197 198 /* 199 * Wait until WD chip is idle 200 */ 201 do { 202 GET_SBIC_asr(regs, asr); 203 if( asr & SBIC_ASR_DBR ) { 204 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 205 splx(s); 206 return; 207 } 208 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 209 210 211 /* 212 * Save important state. 213 * must be done before dmastop 214 */ 215 acb = dev->sc_nexus; 216 acb->sc_dmacmd = dev->sc_dmacmd; 217 218 /* 219 * Fetch the residual count 220 */ 221 SBIC_TC_GET(regs, count); 222 223 /* 224 * Shut down DMA 225 */ 226 dev->sc_dmastop(dev); 227 228 /* 229 * No longer in DMA 230 */ 231 dev->sc_flags &= ~SBICF_INDMA; 232 233 /* 234 * Ensure the WD chip is back in polled I/O mode, with nothing to 235 * transfer. 236 */ 237 SBIC_TC_PUT(regs, 0); 238 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 239 240 /* 241 * Update current count... 242 */ 243 acb->sc_tcnt = count; 244 245 /* 246 * Work out how many bytes were actually transferred 247 */ 248 count = dev->sc_tcnt - count; 249 dev->sc_tcnt = acb->sc_tcnt; 250 251 /* 252 * Fixup partial xfers 253 */ 254 acb->sc_kv.dc_addr += count; 255 acb->sc_kv.dc_count -= count; 256 acb->sc_pa.dc_addr += count; 257 acb->sc_pa.dc_count -= count >> 1; 258 259 #ifdef DEBUG 260 if ( data_pointer_debug ) 261 printf("save at (%p,%x):%x\n", 262 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 263 sbicdma_saves++; 264 #endif 265 266 splx(s); 267 } 268 269 270 /* 271 * DOES NOT RESTART DMA!!! 272 */ 273 void 274 sbic_load_ptrs(dev) 275 struct sbic_softc *dev; 276 { 277 struct sbic_acb *acb = dev->sc_nexus; 278 int s; 279 280 if ( acb->sc_kv.dc_count == 0 ) { 281 /* 282 * No data to xfer 283 */ 284 return; 285 } 286 287 s = splbio(); 288 289 /* 290 * Reset the Scatter-Gather chain 291 */ 292 dev->sc_last = dev->sc_cur = &acb->sc_pa; 293 294 /* 295 * Restore the Transfer Count and DMA specific data 296 */ 297 dev->sc_tcnt = acb->sc_tcnt; 298 dev->sc_dmacmd = acb->sc_dmacmd; 299 300 #ifdef DEBUG 301 sbicdma_ops++; 302 #endif 303 304 /* 305 * Need to fixup new segment? 306 */ 307 if ( dev->sc_tcnt == 0 ) { 308 /* 309 * sc_tcnt == 0 implies end of segment 310 */ 311 char *vaddr, *paddr; 312 int count; 313 314 /* 315 * do kvm to pa mappings 316 */ 317 vaddr = acb->sc_kv.dc_addr; 318 paddr = acb->sc_pa.dc_addr = (char *) kvtop((caddr_t)vaddr); 319 320 for (count = (NBPG - ((int)vaddr & PGOFSET)); 321 count < acb->sc_kv.dc_count && 322 (char*)kvtop((caddr_t)(vaddr + count + 4)) == paddr + count + 4; 323 count += NBPG) 324 ; /* Do nothing */ 325 326 /* 327 * If it's all contiguous... 328 */ 329 if ( count > acb->sc_kv.dc_count ) { 330 count = acb->sc_kv.dc_count; 331 #ifdef DEBUG 332 sbicdma_hits++; 333 #endif 334 } 335 #ifdef DEBUG 336 else 337 sbicdma_misses++; 338 #endif 339 340 acb->sc_tcnt = count; 341 acb->sc_pa.dc_count = count >> 1; 342 343 #ifdef DEBUG 344 if ( data_pointer_debug ) 345 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", acb->sc_kv.dc_addr, 346 acb->sc_kv.dc_count, 347 acb->sc_pa.dc_addr, 348 acb->sc_tcnt); 349 #endif 350 351 } 352 353 splx(s); 354 } 355 356 /* 357 * used by specific sbic controller 358 * 359 * it appears that the higher level code does nothing with LUN's 360 * so I will too. I could plug it in, however so could they 361 * in scsi_scsipi_cmd(). 362 */ 363 int 364 sbic_scsicmd(xs) 365 struct scsipi_xfer *xs; 366 { 367 struct scsipi_link *slp = xs->sc_link; 368 struct sbic_softc *dev = slp->adapter_softc; 369 struct sbic_acb *acb; 370 int flags = xs->xs_control, 371 s; 372 373 if ( flags & XS_CTL_DATA_UIO ) 374 panic("sbic: scsi data uio requested"); 375 376 if ( dev->sc_nexus && (flags & XS_CTL_POLL) ) 377 panic("sbic_scsicmd: busy"); 378 379 if ( slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target ) 380 return ESCAPE_NOT_SUPPORTED; 381 382 s = splbio(); 383 384 if ( (acb = dev->free_list.tqh_first) != NULL ) 385 TAILQ_REMOVE(&dev->free_list, acb, chain); 386 387 splx(s); 388 389 if ( acb == NULL ) { 390 #ifdef DEBUG 391 printf("sbic_scsicmd: unable to queue request for target %d\n", 392 slp->scsipi_scsi.target); 393 #ifdef DDB 394 Debugger(); 395 #endif 396 #endif 397 xs->error = XS_DRIVER_STUFFUP; 398 399 return(TRY_AGAIN_LATER); 400 } 401 402 if ( flags & XS_CTL_DATA_IN ) 403 acb->flags = ACB_ACTIVE | ACB_DATAIN; 404 else 405 acb->flags = ACB_ACTIVE; 406 407 acb->xs = xs; 408 acb->clen = xs->cmdlen; 409 acb->sc_kv.dc_addr = xs->data; 410 acb->sc_kv.dc_count = xs->datalen; 411 acb->pa_addr = xs->data ? (char *)kvtop((caddr_t)xs->data) : 0; 412 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 413 414 if ( flags & XS_CTL_POLL ) { 415 /* 416 * This has major side effects -- it locks up the machine 417 */ 418 int stat; 419 420 s = splbio(); 421 422 dev->sc_flags |= SBICF_ICMD; 423 424 do { 425 /* 426 * If we already had a nexus, while away the time until idle... 427 * This is likely only to happen if a reselection occurs between 428 * here and our earlier check for ICMD && sc_nexus (which would 429 * have resulted in a panic() had it been true). 430 */ 431 while ( dev->sc_nexus ) 432 sbicpoll(dev); 433 434 /* 435 * Fix up the new nexus 436 */ 437 dev->sc_nexus = acb; 438 dev->sc_xs = xs; 439 dev->target = slp->scsipi_scsi.target; 440 dev->lun = slp->scsipi_scsi.lun; 441 442 stat = sbicicmd(dev, &acb->cmd, acb->clen, 443 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 444 445 } while ( dev->sc_nexus != acb ); 446 447 sbic_scsidone(acb, stat); 448 449 splx(s); 450 451 return(COMPLETE); 452 } 453 454 s = splbio(); 455 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 456 457 /* 458 * If nothing is active, try to start it now. 459 */ 460 if ( dev->sc_nexus == NULL ) 461 sbic_sched(dev); 462 463 splx(s); 464 465 return(SUCCESSFULLY_QUEUED); 466 } 467 468 /* 469 * attempt to start the next available command 470 */ 471 void 472 sbic_sched(dev) 473 struct sbic_softc *dev; 474 { 475 struct scsipi_xfer *xs; 476 struct scsipi_link *slp = NULL; /* Gag the compiler */ 477 struct sbic_acb *acb; 478 int flags, 479 stat; 480 481 /* 482 * XXXSCW 483 * I'll keep this test here, even though I can't see any obvious way 484 * in which sbic_sched() could be called with sc_nexus non NULL 485 */ 486 if ( dev->sc_nexus ) 487 return; /* a command is current active */ 488 489 /* 490 * Loop through the ready list looking for work to do... 491 */ 492 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 493 int i, j; 494 495 slp = acb->xs->sc_link; 496 i = slp->scsipi_scsi.target; 497 j = 1 << slp->scsipi_scsi.lun; 498 499 /* 500 * We've found a potential command, but is the target/lun busy? 501 */ 502 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 503 /* 504 * Nope, it's not busy, so we can use it. 505 */ 506 dev->sc_tinfo[i].lubusy |= j; 507 TAILQ_REMOVE(&dev->ready_list, acb, chain); 508 dev->sc_nexus = acb; 509 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 510 break; 511 } 512 } 513 514 if ( acb == NULL ) { 515 QPRINTF(("sbicsched: no work\n")); 516 return; /* did not find an available command */ 517 } 518 519 #ifdef DEBUG 520 if ( data_pointer_debug > 1 ) 521 printf("sbic_sched(%d,%d)\n", slp->scsipi_scsi.target, 522 slp->scsipi_scsi.lun); 523 #endif 524 525 dev->sc_xs = xs = acb->xs; 526 flags = xs->xs_control; 527 528 if ( flags & XS_CTL_RESET ) 529 sbicreset(dev); 530 531 dev->sc_stat[0] = -1; 532 dev->target = slp->scsipi_scsi.target; 533 dev->lun = slp->scsipi_scsi.lun; 534 535 if ( flags & XS_CTL_POLL || (!sbic_parallel_operations && 536 (sbicdmaok(dev, xs) == 0)) ) 537 stat = sbicicmd(dev, &acb->cmd, acb->clen, 538 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 539 else 540 if ( sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT ) 541 return; 542 else 543 stat = dev->sc_stat[0]; 544 545 sbic_scsidone(acb, stat); 546 } 547 548 void 549 sbic_scsidone(acb, stat) 550 struct sbic_acb *acb; 551 int stat; 552 { 553 struct scsipi_xfer *xs = acb->xs; 554 struct scsipi_link *slp = xs->sc_link; 555 struct sbic_softc *dev = slp->adapter_softc; 556 int dosched = 0; 557 558 #ifdef DIAGNOSTIC 559 if ( acb == NULL || xs == NULL ) { 560 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); 561 #ifdef DDB 562 Debugger(); 563 #endif 564 return; 565 } 566 #endif 567 568 /* 569 * is this right? 570 */ 571 xs->status = stat; 572 573 #ifdef DEBUG 574 if ( data_pointer_debug > 1 ) 575 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", slp->scsipi_scsi.target, 576 slp->scsipi_scsi.lun, 577 dev->target, dev->lun, stat); 578 579 if ( xs->sc_link->scsipi_scsi.target == 580 dev->sc_link.scsipi_scsi.adapter_target ) 581 panic("target == hostid"); 582 #endif 583 584 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) == 0 ) { 585 586 if ( stat == SCSI_CHECK ) { 587 /* 588 * Schedule a REQUEST SENSE 589 */ 590 struct scsipi_sense *ss = (void *)&acb->cmd; 591 592 #ifdef DEBUG 593 if ( report_sense ) 594 printf("sbic_scsidone: autosense %02x targ %d lun %d", 595 acb->cmd.opcode, slp->scsipi_scsi.target, 596 slp->scsipi_scsi.lun); 597 #endif 598 599 bzero(ss, sizeof(*ss)); 600 601 ss->opcode = REQUEST_SENSE; 602 ss->byte2 = slp->scsipi_scsi.lun << 5; 603 ss->length = sizeof(struct scsipi_sense_data); 604 605 acb->clen = sizeof(*ss); 606 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 607 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 608 acb->pa_addr = (char *)kvtop((caddr_t)&xs->sense.scsi_sense); 609 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 610 611 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 612 613 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 614 ~(1 << slp->scsipi_scsi.lun); 615 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 616 617 if ( dev->sc_nexus == acb ) { 618 dev->sc_nexus = NULL; 619 dev->sc_xs = NULL; 620 sbic_sched(dev); 621 } 622 return; 623 } 624 } 625 626 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) != 0 ) { 627 628 xs->error = XS_SENSE; 629 630 #ifdef DEBUG 631 if (report_sense) 632 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 633 xs->sense.scsi_sense.extra_bytes[3]); 634 #endif 635 636 } else { 637 xs->resid = 0; /* XXXX */ 638 } 639 640 xs->xs_status |= XS_STS_DONE; 641 642 /* 643 * Remove the ACB from whatever queue it's on. We have to do a bit of 644 * a hack to figure out which queue it's on. Note that it is *not* 645 * necessary to cdr down the ready queue, but we must cdr down the 646 * nexus queue and see if it's there, so we can mark the unit as no 647 * longer busy. This code is sickening, but it works. 648 */ 649 if ( acb == dev->sc_nexus ) { 650 651 dev->sc_nexus = NULL; 652 dev->sc_xs = NULL; 653 654 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 655 ~(1 << slp->scsipi_scsi.lun); 656 657 if ( dev->ready_list.tqh_first ) 658 dosched = 1; /* start next command */ 659 660 } else 661 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 662 663 TAILQ_REMOVE(&dev->ready_list, acb, chain); 664 665 } else { 666 667 struct sbic_acb *a; 668 669 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 670 if ( a == acb ) { 671 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 672 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 673 ~(1 << slp->scsipi_scsi.lun); 674 break; 675 } 676 } 677 678 if ( a ) 679 ; 680 else if ( acb->chain.tqe_next ) { 681 TAILQ_REMOVE(&dev->ready_list, acb, chain); 682 } else { 683 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 684 #ifdef DDB 685 Debugger(); 686 #endif 687 } 688 } 689 690 /* 691 * Put it on the free list. 692 */ 693 acb->flags = ACB_FREE; 694 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 695 696 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 697 698 scsipi_done(xs); 699 700 if ( dosched ) 701 sbic_sched(dev); 702 } 703 704 int 705 sbicdmaok(dev, xs) 706 struct sbic_softc *dev; 707 struct scsipi_xfer *xs; 708 { 709 if ( sbic_no_dma || xs->datalen == 0 || 710 xs->datalen & 0x03 || (int)xs->data & 0x03) 711 return(0); 712 713 /* 714 * controller supports dma to any addresses? 715 */ 716 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 717 return(1); 718 719 /* 720 * this address is ok for dma? 721 */ 722 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 723 return(1); 724 725 return(0); 726 } 727 728 int 729 sbicwait(regs, until, timeo, line) 730 sbic_regmap_p regs; 731 u_char until; 732 int timeo; 733 int line; 734 { 735 u_char val; 736 737 if ( timeo == 0 ) 738 timeo = 1000000; /* some large value.. */ 739 740 GET_SBIC_asr(regs, val); 741 742 while ( (val & until) == 0 ) { 743 744 if ( timeo-- == 0 ) { 745 int csr; 746 GET_SBIC_csr(regs, csr); 747 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 748 #if defined(DDB) && defined(DEBUG) 749 Debugger(); 750 #endif 751 return(val); /* Maybe I should abort */ 752 break; 753 } 754 755 DELAY(1); 756 GET_SBIC_asr(regs, val); 757 } 758 759 return(val); 760 } 761 762 int 763 sbicabort(dev, where) 764 struct sbic_softc *dev; 765 char *where; 766 { 767 sbic_regmap_p regs = dev->sc_sbicp; 768 u_char csr, 769 asr; 770 771 GET_SBIC_asr(regs, asr); 772 GET_SBIC_csr(regs, csr); 773 774 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 775 dev->sc_dev.dv_xname, where, csr, asr); 776 777 /* 778 * Clean up chip itself 779 */ 780 if ( dev->sc_flags & SBICF_SELECTED ) { 781 782 while ( asr & SBIC_ASR_DBR ) { 783 /* 784 * sbic is jammed w/data. need to clear it 785 * But we don't know what direction it needs to go 786 */ 787 GET_SBIC_data(regs, asr); 788 printf("%s: abort %s: clearing data buffer 0x%02x\n", 789 dev->sc_dev.dv_xname, where, asr); 790 GET_SBIC_asr(regs, asr); 791 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 792 SET_SBIC_data(regs, asr); 793 GET_SBIC_asr(regs, asr); 794 } 795 796 WAIT_CIP(regs); 797 798 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 799 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 800 WAIT_CIP(regs); 801 802 GET_SBIC_asr(regs, asr); 803 804 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 805 /* 806 * ok, get more drastic.. 807 */ 808 printf("%s: sbicabort - asr %x, trying to reset\n", 809 dev->sc_dev.dv_xname, asr); 810 sbicreset(dev); 811 dev->sc_flags &= ~SBICF_SELECTED; 812 return SBIC_STATE_ERROR; 813 } 814 815 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 816 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 817 818 do { 819 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 820 GET_SBIC_asr(regs, asr); 821 GET_SBIC_csr (regs, csr); 822 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 823 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 824 (csr != SBIC_CSR_CMD_INVALID) ); 825 826 /* 827 * lets just hope it worked.. 828 */ 829 dev->sc_flags &= ~SBICF_SELECTED; 830 } 831 832 return SBIC_STATE_ERROR; 833 } 834 835 836 /* 837 * Initialize driver-private structures 838 */ 839 void 840 sbicinit(dev) 841 struct sbic_softc *dev; 842 { 843 u_int i; 844 845 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 846 847 struct sbic_acb *acb; 848 849 TAILQ_INIT(&dev->ready_list); 850 TAILQ_INIT(&dev->nexus_list); 851 TAILQ_INIT(&dev->free_list); 852 callout_init(&dev->sc_timo_ch); 853 854 dev->sc_nexus = NULL; 855 dev->sc_xs = NULL; 856 857 acb = dev->sc_acb; 858 bzero(acb, sizeof(dev->sc_acb)); 859 860 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 861 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 862 acb++; 863 } 864 865 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 866 867 #ifdef DEBUG 868 /* 869 * make sure timeout is really not needed 870 */ 871 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 872 #endif 873 874 } else 875 panic("sbic: reinitializing driver!"); 876 877 dev->sc_flags |= SBICF_ALIVE; 878 dev->sc_flags &= ~SBICF_SELECTED; 879 880 /* 881 * initialize inhibit array 882 * Never enable Sync, since it just doesn't work on mvme147 :( 883 */ 884 for (i = 0; i < 8; ++i) 885 sbic_inhibit_sync[i] = 1; 886 887 sbicreset(dev); 888 } 889 890 void 891 sbicreset(dev) 892 struct sbic_softc *dev; 893 { 894 sbic_regmap_p regs = dev->sc_sbicp; 895 u_int my_id, 896 s; 897 u_char csr; 898 899 s = splbio(); 900 901 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 902 903 if (dev->sc_clkfreq < 110) 904 my_id |= SBIC_ID_FS_8_10; 905 else if (dev->sc_clkfreq < 160) 906 my_id |= SBIC_ID_FS_12_15; 907 else if (dev->sc_clkfreq < 210) 908 my_id |= SBIC_ID_FS_16_20; 909 910 SET_SBIC_myid(regs, my_id); 911 912 /* 913 * Reset the chip 914 */ 915 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 916 DELAY(25); 917 918 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 919 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 920 921 /* 922 * Set up various chip parameters 923 */ 924 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 925 926 /* 927 * don't allow Selection (SBIC_RID_ES) 928 * until we can handle target mode!! 929 */ 930 SET_SBIC_rselid(regs, SBIC_RID_ER); 931 932 /* 933 * Asynchronous for now 934 */ 935 SET_SBIC_syn(regs, 0); 936 937 /* 938 * Anything else was zeroed by reset 939 */ 940 splx(s); 941 942 dev->sc_flags &= ~SBICF_SELECTED; 943 } 944 945 void 946 sbicerror(dev, csr) 947 struct sbic_softc *dev; 948 u_char csr; 949 { 950 struct scsipi_xfer *xs = dev->sc_xs; 951 952 #ifdef DIAGNOSTIC 953 if ( xs == NULL ) 954 panic("sbicerror: dev->sc_xs == NULL"); 955 #endif 956 957 if ( xs->xs_control & XS_CTL_SILENT ) 958 return; 959 960 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 961 } 962 963 /* 964 * select the bus, return when selected or error. 965 * 966 * Returns the current CSR following selection and optionally MSG out phase. 967 * i.e. the returned CSR *should* indicate CMD phase... 968 * If the return value is 0, some error happened. 969 */ 970 u_char 971 sbicselectbus(dev) 972 struct sbic_softc *dev; 973 { 974 sbic_regmap_p regs = dev->sc_sbicp; 975 u_char target = dev->target, 976 lun = dev->lun, 977 asr, 978 csr, 979 id; 980 981 /* 982 * if we're already selected, return (XXXX panic maybe?) 983 */ 984 if ( dev->sc_flags & SBICF_SELECTED ) 985 return(0); 986 987 QPRINTF(("sbicselectbus %d: ", target)); 988 989 /* 990 * issue select 991 */ 992 SET_SBIC_selid(regs, target); 993 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 994 995 GET_SBIC_asr(regs, asr); 996 997 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 998 /* 999 * This means we got ourselves reselected upon 1000 */ 1001 QPRINTF(("WD busy (reselect?)\n")); 1002 return 0; 1003 } 1004 1005 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1006 1007 /* 1008 * wait for select (merged from seperate function may need 1009 * cleanup) 1010 */ 1011 WAIT_CIP(regs); 1012 1013 do { 1014 1015 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1016 1017 if ( asr & SBIC_ASR_LCI ) { 1018 QPRINTF(("late LCI: asr %02x\n", asr)); 1019 return 0; 1020 } 1021 1022 /* 1023 * Clear interrupt 1024 */ 1025 GET_SBIC_csr (regs, csr); 1026 1027 QPRINTF(("%02x ", csr)); 1028 1029 /* 1030 * Reselected from under our feet? 1031 */ 1032 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 1033 QPRINTF(("got reselected, asr %02x\n", asr)); 1034 /* 1035 * We need to handle this now so we don't lock up later 1036 */ 1037 sbicnextstate(dev, csr, asr); 1038 1039 return 0; 1040 } 1041 1042 /* 1043 * Whoops! 1044 */ 1045 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1046 panic("sbicselectbus: target issued select!"); 1047 return 0; 1048 } 1049 1050 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1051 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1052 csr != SBIC_CSR_SEL_TIMEO); 1053 1054 /* 1055 * Anyone at home? 1056 */ 1057 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1058 dev->sc_xs->error = XS_SELTIMEOUT; 1059 QPRINTF(("Selection Timeout\n")); 1060 return 0; 1061 } 1062 1063 QPRINTF(("Selection Complete\n")); 1064 1065 /* 1066 * Assume we're now selected 1067 */ 1068 GET_SBIC_selid(regs, id); 1069 dev->target = id; 1070 dev->lun = lun; 1071 dev->sc_flags |= SBICF_SELECTED; 1072 1073 /* 1074 * Enable (or not) reselection 1075 * XXXSCW This is probably not necessary since we don't use use the 1076 * Select-and-Xfer-with-ATN command to initiate a selection... 1077 */ 1078 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1079 SET_SBIC_rselid (regs, 0); 1080 else 1081 SET_SBIC_rselid (regs, SBIC_RID_ER); 1082 1083 /* 1084 * We only really need to do anything when the target goes to MSG out 1085 * If the device ignored ATN, it's probably old and brain-dead, 1086 * but we'll try to support it anyhow. 1087 * If it doesn't support message out, it definately doesn't 1088 * support synchronous transfers, so no point in even asking... 1089 */ 1090 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1091 /* 1092 * Send identify message (SCSI-2 requires an identify msg) 1093 */ 1094 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1095 /* 1096 * Handle drives that don't want to be asked 1097 * whether to go sync at all. 1098 */ 1099 dev->sc_sync[id].offset = 0; 1100 dev->sc_sync[id].period = sbic_min_period; 1101 dev->sc_sync[id].state = SYNC_DONE; 1102 } 1103 1104 /* 1105 * Do we need to negotiate Synchronous Xfers for this target? 1106 */ 1107 if ( dev->sc_sync[id].state != SYNC_START ) { 1108 /* 1109 * Nope, we've already negotiated. 1110 * Now see if we should allow the target to disconnect/reselect... 1111 */ 1112 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 1113 !sbic_enable_reselect ) 1114 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1115 else 1116 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1117 1118 } else { 1119 /* 1120 * try to initiate a sync transfer. 1121 * So compose the sync message we're going 1122 * to send to the target 1123 */ 1124 #ifdef DEBUG 1125 if ( sync_debug ) 1126 printf("\nSending sync request to target %d ... ", id); 1127 #endif 1128 /* 1129 * setup scsi message sync message request 1130 */ 1131 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1132 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1133 dev->sc_msg[2] = 3; 1134 dev->sc_msg[3] = MSG_SYNC_REQ; 1135 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1136 dev->sc_msg[5] = sbic_max_offset; 1137 1138 sbicxfout(regs, 6, dev->sc_msg); 1139 1140 dev->sc_sync[id].state = SYNC_SENT; 1141 #ifdef DEBUG 1142 if ( sync_debug ) 1143 printf ("sent\n"); 1144 #endif 1145 } 1146 1147 /* 1148 * There's one interrupt still to come: the change to CMD phase... 1149 */ 1150 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1151 GET_SBIC_csr(regs, csr); 1152 } 1153 1154 /* 1155 * set sync or async 1156 */ 1157 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1158 #ifdef DEBUG 1159 if ( sync_debug ) 1160 printf("select(%d): sync reg = 0x%02x\n", target, 1161 SBIC_SYN(dev->sc_sync[target].offset, 1162 dev->sc_sync[target].period)); 1163 #endif 1164 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1165 dev->sc_sync[target].period)); 1166 } else { 1167 #ifdef DEBUG 1168 if ( sync_debug ) 1169 printf("select(%d): sync reg = 0x%02x\n", target, 1170 SBIC_SYN(0,sbic_min_period)); 1171 #endif 1172 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1173 } 1174 1175 return csr; 1176 } 1177 1178 /* 1179 * Information Transfer *to* a Scsi Target. 1180 * 1181 * Note: Don't expect there to be an interrupt immediately after all 1182 * the data is transferred out. The WD spec sheet says that the Transfer- 1183 * Info command for non-MSG_IN phases only completes when the target 1184 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1185 * 1186 * This can have a nasty effect on commands which take a relatively long 1187 * time to complete, for example a START/STOP unit command may remain in 1188 * CMD phase until the disk has spun up. Only then will the target change 1189 * to STATUS phase. This is really only a problem for immediate commands 1190 * since we don't allow disconnection for them (yet). 1191 */ 1192 int 1193 sbicxfout(regs, len, bp) 1194 sbic_regmap_p regs; 1195 int len; 1196 void *bp; 1197 { 1198 int wait = sbic_data_wait; 1199 u_char asr, 1200 *buf = bp; 1201 1202 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1203 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1204 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1205 1206 /* 1207 * sigh.. WD-PROTO strikes again.. sending the command in one go 1208 * causes the chip to lock up if talking to certain (misbehaving?) 1209 * targets. Anyway, this procedure should work for all targets, but 1210 * it's slightly slower due to the overhead 1211 */ 1212 WAIT_CIP (regs); 1213 1214 SBIC_TC_PUT (regs, 0); 1215 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1216 SBIC_TC_PUT (regs, (unsigned)len); 1217 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1218 1219 /* 1220 * Loop for each byte transferred 1221 */ 1222 do { 1223 1224 GET_SBIC_asr (regs, asr); 1225 1226 if ( asr & SBIC_ASR_DBR ) { 1227 if ( len ) { 1228 SET_SBIC_data (regs, *buf); 1229 buf++; 1230 len--; 1231 } else { 1232 SET_SBIC_data (regs, 0); 1233 } 1234 wait = sbic_data_wait; 1235 } 1236 1237 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1238 1239 #ifdef DEBUG 1240 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1241 #endif 1242 1243 /* 1244 * Normally, an interrupt will be pending when this routing returns. 1245 */ 1246 return(len); 1247 } 1248 1249 /* 1250 * Information Transfer *from* a Scsi Target 1251 * returns # bytes left to read 1252 */ 1253 int 1254 sbicxfin(regs, len, bp) 1255 sbic_regmap_p regs; 1256 int len; 1257 void *bp; 1258 { 1259 int wait = sbic_data_wait; 1260 u_char *buf = bp; 1261 u_char asr; 1262 #ifdef DEBUG 1263 u_char *obp = bp; 1264 #endif 1265 1266 WAIT_CIP (regs); 1267 1268 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1269 SBIC_TC_PUT (regs, (unsigned)len); 1270 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1271 1272 /* 1273 * Loop for each byte transferred 1274 */ 1275 do { 1276 1277 GET_SBIC_asr (regs, asr); 1278 1279 if ( asr & SBIC_ASR_DBR ) { 1280 if ( len ) { 1281 GET_SBIC_data (regs, *buf); 1282 buf++; 1283 len--; 1284 } else { 1285 u_char foo; 1286 GET_SBIC_data (regs, foo); 1287 } 1288 wait = sbic_data_wait; 1289 } 1290 1291 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1292 1293 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1294 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1295 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1296 1297 SBIC_TC_PUT (regs, 0); 1298 1299 /* 1300 * this leaves with one csr to be read 1301 */ 1302 return len; 1303 } 1304 1305 /* 1306 * SCSI 'immediate' command: issue a command to some SCSI device 1307 * and get back an 'immediate' response (i.e., do programmed xfer 1308 * to get the response data). 'cbuf' is a buffer containing a scsi 1309 * command of length clen bytes. 'buf' is a buffer of length 'len' 1310 * bytes for data. The transfer direction is determined by the device 1311 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1312 * command must supply no data. 1313 * 1314 * Note that although this routine looks like it can handle disconnect/ 1315 * reselect, the fact is that it can't. There is still some work to be 1316 * done to clean this lot up. 1317 */ 1318 int 1319 sbicicmd(dev, cbuf, clen, buf, len) 1320 struct sbic_softc *dev; 1321 void *cbuf, 1322 *buf; 1323 int clen, 1324 len; 1325 { 1326 sbic_regmap_p regs = dev->sc_sbicp; 1327 struct sbic_acb *acb = dev->sc_nexus; 1328 u_char csr, 1329 asr; 1330 int still_busy = SBIC_STATE_RUNNING; 1331 1332 /* 1333 * Make sure pointers are OK 1334 */ 1335 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1336 dev->sc_tcnt = acb->sc_tcnt = 0; 1337 1338 acb->sc_dmacmd = 0; 1339 acb->sc_pa.dc_count = 0; /* No DMA */ 1340 acb->sc_kv.dc_addr = buf; 1341 acb->sc_kv.dc_count = len; 1342 1343 #ifdef DEBUG 1344 if ( data_pointer_debug > 1 ) 1345 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1346 #endif 1347 1348 /* 1349 * set the sbic into non-DMA mode 1350 */ 1351 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1352 1353 dev->sc_stat[0] = 0xff; 1354 dev->sc_msg[0] = 0xff; 1355 1356 /* 1357 * We're stealing the SCSI bus 1358 */ 1359 dev->sc_flags |= SBICF_ICMD; 1360 1361 do { 1362 GET_SBIC_asr (regs, asr); 1363 1364 /* 1365 * select the SCSI bus (it's an error if bus isn't free) 1366 */ 1367 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1368 still_busy != SBIC_STATE_DISCONNECT ) { 1369 if ( (csr = sbicselectbus(dev)) == 0 ) { 1370 dev->sc_flags &= ~SBICF_ICMD; 1371 return(-1); 1372 } 1373 } else 1374 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1375 GET_SBIC_csr(regs, csr); 1376 else 1377 csr = 0; 1378 1379 if ( csr ) { 1380 1381 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1382 1383 switch ( csr ) { 1384 1385 case SBIC_CSR_S_XFERRED: 1386 case SBIC_CSR_DISC: 1387 case SBIC_CSR_DISC_1: 1388 { 1389 u_char phase; 1390 1391 dev->sc_flags &= ~SBICF_SELECTED; 1392 GET_SBIC_cmd_phase (regs, phase); 1393 1394 if ( phase == 0x60 ) { 1395 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1396 still_busy = SBIC_STATE_DONE; /* done */ 1397 } else { 1398 #ifdef DEBUG 1399 if ( reselect_debug > 1 ) 1400 printf("sbicicmd: handling disconnect\n"); 1401 #endif 1402 still_busy = SBIC_STATE_DISCONNECT; 1403 } 1404 } 1405 break; 1406 1407 case SBIC_CSR_XFERRED | CMD_PHASE: 1408 case SBIC_CSR_MIS | CMD_PHASE: 1409 case SBIC_CSR_MIS_1 | CMD_PHASE: 1410 case SBIC_CSR_MIS_2 | CMD_PHASE: 1411 { 1412 if ( sbicxfout(regs, clen, cbuf) ) 1413 still_busy = sbicabort(dev, "icmd sending cmd"); 1414 } 1415 break; 1416 1417 case SBIC_CSR_XFERRED | STATUS_PHASE: 1418 case SBIC_CSR_MIS | STATUS_PHASE: 1419 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1420 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1421 { 1422 /* 1423 * The sbic does the status/cmd-complete reading ok, 1424 * so do this with its hi-level commands. 1425 */ 1426 #ifdef DEBUG 1427 if ( sbic_debug ) 1428 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1429 #endif 1430 SET_SBIC_cmd_phase(regs, 0x46); 1431 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1432 } 1433 break; 1434 1435 default: 1436 { 1437 still_busy = sbicnextstate(dev, csr, asr); 1438 } 1439 break; 1440 } 1441 1442 /* 1443 * make sure the last command was taken, 1444 * ie. we're not hunting after an ignored command.. 1445 */ 1446 GET_SBIC_asr(regs, asr); 1447 1448 /* 1449 * tapes may take a loooong time.. 1450 */ 1451 while (asr & SBIC_ASR_BSY ) { 1452 1453 if ( asr & SBIC_ASR_DBR ) { 1454 int i; 1455 1456 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1457 #ifdef DDB 1458 Debugger(); 1459 #endif 1460 /* 1461 * SBIC is jammed 1462 * DUNNO which direction 1463 * Try old direction 1464 */ 1465 GET_SBIC_data(regs, i); 1466 GET_SBIC_asr(regs, asr); 1467 1468 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1469 SET_SBIC_data(regs, i); 1470 } 1471 1472 GET_SBIC_asr(regs, asr); 1473 } 1474 } 1475 1476 /* 1477 * wait for last command to complete 1478 */ 1479 if ( asr & SBIC_ASR_LCI ) { 1480 printf("sbicicmd: last command ignored\n"); 1481 } 1482 else 1483 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1484 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1485 1486 /* 1487 * do it again 1488 */ 1489 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1490 1491 /* 1492 * Sometimes we need to do an extra read of the CSR 1493 */ 1494 GET_SBIC_csr(regs, csr); 1495 1496 #ifdef DEBUG 1497 if ( data_pointer_debug > 1 ) 1498 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1499 acb->sc_kv.dc_count, 1500 dev->sc_stat[0]); 1501 #endif 1502 1503 dev->sc_flags &= ~SBICF_ICMD; 1504 1505 return(dev->sc_stat[0]); 1506 } 1507 1508 /* 1509 * Finish SCSI xfer command: After the completion interrupt from 1510 * a read/write operation, sequence through the final phases in 1511 * programmed i/o. This routine is a lot like sbicicmd except we 1512 * skip (and don't allow) the select, cmd out and data in/out phases. 1513 */ 1514 void 1515 sbicxfdone(dev) 1516 struct sbic_softc *dev; 1517 { 1518 sbic_regmap_p regs = dev->sc_sbicp; 1519 u_char phase, 1520 csr; 1521 int s; 1522 1523 QPRINTF(("{")); 1524 s = splbio(); 1525 1526 /* 1527 * have the sbic complete on its own 1528 */ 1529 SBIC_TC_PUT(regs, 0); 1530 SET_SBIC_cmd_phase(regs, 0x46); 1531 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1532 1533 do { 1534 1535 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1536 GET_SBIC_csr (regs, csr); 1537 QPRINTF(("%02x:", csr)); 1538 1539 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1540 (csr != SBIC_CSR_S_XFERRED)); 1541 1542 dev->sc_flags &= ~SBICF_SELECTED; 1543 1544 GET_SBIC_cmd_phase (regs, phase); 1545 QPRINTF(("}%02x", phase)); 1546 1547 if ( phase == 0x60 ) 1548 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1549 else 1550 sbicerror(dev, csr); 1551 1552 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1553 1554 splx(s); 1555 } 1556 1557 /* 1558 * No DMA chains 1559 */ 1560 int 1561 sbicgo(dev, xs) 1562 struct sbic_softc *dev; 1563 struct scsipi_xfer *xs; 1564 { 1565 struct sbic_acb *acb = dev->sc_nexus; 1566 sbic_regmap_p regs = dev->sc_sbicp; 1567 int i, 1568 dmaflags, 1569 count, 1570 usedma; 1571 u_char csr, 1572 asr, 1573 *addr; 1574 1575 dev->target = xs->sc_link->scsipi_scsi.target; 1576 dev->lun = xs->sc_link->scsipi_scsi.lun; 1577 1578 usedma = sbicdmaok(dev, xs); 1579 1580 #ifdef DEBUG 1581 if ( data_pointer_debug > 1 ) 1582 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1583 #endif 1584 1585 /* 1586 * select the SCSI bus (it's an error if bus isn't free) 1587 */ 1588 if ( (csr = sbicselectbus(dev)) == 0 ) 1589 return(0); /* Not done: needs to be rescheduled */ 1590 1591 dev->sc_stat[0] = 0xff; 1592 1593 /* 1594 * Calculate DMA chains now 1595 */ 1596 if ( acb->flags & ACB_DATAIN ) 1597 dmaflags = DMAGO_READ; 1598 else 1599 dmaflags = 0; 1600 1601 addr = acb->sc_kv.dc_addr; 1602 count = acb->sc_kv.dc_count; 1603 1604 if ( count && ((char *)kvtop((caddr_t)addr) != acb->sc_pa.dc_addr) ) { 1605 printf("sbic: DMA buffer mapping changed %p->%lx\n", 1606 acb->sc_pa.dc_addr, kvtop((caddr_t)addr)); 1607 #ifdef DDB 1608 Debugger(); 1609 #endif 1610 } 1611 1612 #ifdef DEBUG 1613 ++sbicdma_ops; /* count total DMA operations */ 1614 #endif 1615 1616 /* 1617 * Allocate the DMA chain 1618 * Mark end of segment... 1619 */ 1620 acb->sc_tcnt = dev->sc_tcnt = 0; 1621 acb->sc_pa.dc_count = 0; 1622 1623 sbic_load_ptrs(dev); 1624 1625 /* 1626 * Enable interrupts but don't do any DMA 1627 * enintr() also enables interrupts for the sbic 1628 */ 1629 dev->sc_enintr(dev); 1630 1631 if ( usedma ) { 1632 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1633 acb->sc_pa.dc_count, dmaflags); 1634 #ifdef DEBUG 1635 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1636 #endif 1637 } else 1638 dev->sc_dmacmd = 0; /* Don't use DMA */ 1639 1640 acb->sc_dmacmd = dev->sc_dmacmd; 1641 1642 #ifdef DEBUG 1643 if ( data_pointer_debug > 1 ) { 1644 printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, 1645 dev->sc_cur->dc_addr, 1646 dev->sc_tcnt, 1647 dev->sc_dmacmd); 1648 } 1649 #endif 1650 1651 /* 1652 * Lets cycle a while then let the interrupt handler take over. 1653 */ 1654 GET_SBIC_asr(regs, asr); 1655 1656 do { 1657 1658 QPRINTF(("go ")); 1659 1660 /* 1661 * Handle the new phase 1662 */ 1663 i = sbicnextstate(dev, csr, asr); 1664 #if 0 1665 WAIT_CIP(regs); 1666 #endif 1667 if ( i == SBIC_STATE_RUNNING ) { 1668 GET_SBIC_asr(regs, asr); 1669 1670 if ( asr & SBIC_ASR_LCI ) 1671 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1672 1673 if ( asr & SBIC_ASR_INT ) 1674 GET_SBIC_csr(regs, csr); 1675 } 1676 1677 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1678 1679 if ( i == SBIC_STATE_DONE ) { 1680 if ( dev->sc_stat[0] == 0xff ) 1681 #if 0 1682 printf("sbicgo: done & stat = 0xff\n"); 1683 #else 1684 ; 1685 #endif 1686 else 1687 return 1; /* Did we really finish that fast? */ 1688 } 1689 1690 return 0; 1691 } 1692 1693 1694 int 1695 sbicintr(dev) 1696 struct sbic_softc *dev; 1697 { 1698 sbic_regmap_p regs = dev->sc_sbicp; 1699 u_char asr, 1700 csr; 1701 int i; 1702 1703 /* 1704 * pending interrupt? 1705 */ 1706 GET_SBIC_asr (regs, asr); 1707 if ( (asr & SBIC_ASR_INT) == 0 ) 1708 return(0); 1709 1710 GET_SBIC_csr(regs, csr); 1711 1712 do { 1713 1714 QPRINTF(("intr[0x%x]", csr)); 1715 1716 i = sbicnextstate(dev, csr, asr); 1717 #if 0 1718 WAIT_CIP(regs); 1719 #endif 1720 if ( i == SBIC_STATE_RUNNING ) { 1721 GET_SBIC_asr(regs, asr); 1722 1723 if ( asr & SBIC_ASR_LCI ) 1724 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1725 1726 if ( asr & SBIC_ASR_INT ) 1727 GET_SBIC_csr(regs, csr); 1728 } 1729 1730 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1731 1732 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1733 1734 return(1); 1735 } 1736 1737 /* 1738 * Run commands and wait for disconnect. 1739 * This is only ever called when a command is in progress, when we 1740 * want to busy wait for it to finish. 1741 */ 1742 int 1743 sbicpoll(dev) 1744 struct sbic_softc *dev; 1745 { 1746 sbic_regmap_p regs = dev->sc_sbicp; 1747 u_char asr, 1748 csr; 1749 int i; 1750 1751 /* 1752 * Wait for the next interrupt 1753 */ 1754 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1755 1756 do { 1757 GET_SBIC_asr (regs, asr); 1758 1759 if ( asr & SBIC_ASR_INT ) 1760 GET_SBIC_csr(regs, csr); 1761 1762 QPRINTF(("poll[0x%x]", csr)); 1763 1764 /* 1765 * Handle it 1766 */ 1767 i = sbicnextstate(dev, csr, asr); 1768 1769 WAIT_CIP(regs); 1770 GET_SBIC_asr(regs, asr); 1771 1772 /* 1773 * tapes may take a loooong time.. 1774 */ 1775 while ( asr & SBIC_ASR_BSY ) { 1776 u_char z = 0; 1777 1778 if ( asr & SBIC_ASR_DBR ) { 1779 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1780 #ifdef DDB 1781 Debugger(); 1782 #endif 1783 /* 1784 * SBIC is jammed 1785 * DUNNO which direction 1786 * Try old direction 1787 */ 1788 GET_SBIC_data(regs, z); 1789 GET_SBIC_asr(regs, asr); 1790 1791 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1792 SET_SBIC_data(regs, z); 1793 } 1794 1795 GET_SBIC_asr(regs, asr); 1796 } 1797 1798 if ( asr & SBIC_ASR_LCI ) 1799 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1800 else 1801 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1802 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1803 1804 } while ( i == SBIC_STATE_RUNNING ); 1805 1806 return(1); 1807 } 1808 1809 /* 1810 * Handle a single msgin 1811 */ 1812 int 1813 sbicmsgin(dev) 1814 struct sbic_softc *dev; 1815 { 1816 sbic_regmap_p regs = dev->sc_sbicp; 1817 int recvlen = 1; 1818 u_char asr, 1819 csr, 1820 *tmpaddr, 1821 *msgaddr; 1822 1823 tmpaddr = msgaddr = dev->sc_msg; 1824 1825 tmpaddr[0] = 0xff; 1826 tmpaddr[1] = 0xff; 1827 1828 GET_SBIC_asr(regs, asr); 1829 1830 #ifdef DEBUG 1831 if ( reselect_debug > 1 ) 1832 printf("sbicmsgin asr=%02x\n", asr); 1833 #endif 1834 1835 GET_SBIC_selid (regs, csr); 1836 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1837 1838 SBIC_TC_PUT(regs, 0); 1839 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1840 1841 do { 1842 while( recvlen-- ) { 1843 1844 /* 1845 * Fetch the next byte of the message 1846 */ 1847 RECV_BYTE(regs, *tmpaddr); 1848 1849 /* 1850 * get the command completion interrupt, or we 1851 * can't send a new command (LCI) 1852 */ 1853 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1854 GET_SBIC_csr(regs, csr); 1855 1856 #ifdef DEBUG 1857 if ( reselect_debug > 1 ) 1858 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1859 #endif 1860 1861 tmpaddr++; 1862 1863 if ( recvlen ) { 1864 /* 1865 * Clear ACK, and wait for the interrupt for the next byte 1866 */ 1867 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1868 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1869 GET_SBIC_csr(regs, csr); 1870 } 1871 } 1872 1873 if ( msgaddr[0] == 0xff ) { 1874 printf("sbicmsgin: sbic swallowed our message\n"); 1875 break; 1876 } 1877 1878 #ifdef DEBUG 1879 if ( sync_debug ) { 1880 GET_SBIC_asr(regs, asr); 1881 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1882 } 1883 #endif 1884 /* 1885 * test whether this is a reply to our sync 1886 * request 1887 */ 1888 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1889 1890 /* 1891 * Got IFFY msg -- ack it 1892 */ 1893 QPRINTF(("IFFY")); 1894 1895 } else 1896 if ( msgaddr[0] == MSG_REJECT && 1897 dev->sc_sync[dev->target].state == SYNC_SENT) { 1898 1899 /* 1900 * Target probably rejected our Sync negotiation. 1901 */ 1902 QPRINTF(("REJECT of SYN")); 1903 1904 #ifdef DEBUG 1905 if ( sync_debug ) 1906 printf("target %d rejected sync, going async\n", dev->target); 1907 #endif 1908 1909 dev->sc_sync[dev->target].period = sbic_min_period; 1910 dev->sc_sync[dev->target].offset = 0; 1911 dev->sc_sync[dev->target].state = SYNC_DONE; 1912 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1913 dev->sc_sync[dev->target].period)); 1914 1915 } else 1916 if ( msgaddr[0] == MSG_REJECT ) { 1917 1918 /* 1919 * we'll never REJECt a REJECT message.. 1920 */ 1921 QPRINTF(("REJECT")); 1922 1923 } else 1924 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1925 1926 /* 1927 * don't reject this either. 1928 */ 1929 QPRINTF(("MSG_SAVE_DATA_PTR")); 1930 1931 } else 1932 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1933 1934 /* 1935 * don't reject this either. 1936 */ 1937 QPRINTF(("MSG_RESTORE_PTR")); 1938 1939 } else 1940 if ( msgaddr[0] == MSG_DISCONNECT ) { 1941 1942 /* 1943 * Target is disconnecting... 1944 */ 1945 QPRINTF(("DISCONNECT")); 1946 1947 #ifdef DEBUG 1948 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1949 printf("sbicmsgin: got disconnect msg %s\n", 1950 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1951 #endif 1952 1953 if ( dev->sc_flags & SBICF_ICMD ) { 1954 /* 1955 * We're in immediate mode. Prevent disconnects. 1956 * prepare to reject the message, NACK 1957 */ 1958 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1959 WAIT_CIP(regs); 1960 } 1961 1962 } else 1963 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1964 1965 /* 1966 * !! KLUDGE ALERT !! quite a few drives don't seem to 1967 * really like the current way of sending the 1968 * sync-handshake together with the ident-message, and 1969 * they react by sending command-complete and 1970 * disconnecting right after returning the valid sync 1971 * handshake. So, all I can do is reselect the drive, 1972 * and hope it won't disconnect again. I don't think 1973 * this is valid behavior, but I can't help fixing a 1974 * problem that apparently exists. 1975 * 1976 * Note: we should not get here on `normal' command 1977 * completion, as that condition is handled by the 1978 * high-level sel&xfer resume command used to walk 1979 * thru status/cc-phase. 1980 */ 1981 QPRINTF(("CMD_COMPLETE")); 1982 1983 #ifdef DEBUG 1984 if ( sync_debug ) 1985 printf ("GOT MSG %d! target %d acting weird.." 1986 " waiting for disconnect...\n", msgaddr[0], dev->target); 1987 #endif 1988 1989 /* 1990 * Check to see if sbic is handling this 1991 */ 1992 GET_SBIC_asr(regs, asr); 1993 1994 /* 1995 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 1996 */ 1997 if ( asr & SBIC_ASR_BSY ) 1998 return SBIC_STATE_RUNNING; 1999 2000 /* 2001 * Let's try this: Assume it works and set status to 00 2002 */ 2003 dev->sc_stat[0] = 0; 2004 2005 } else 2006 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 2007 2008 /* 2009 * Target is sending us an extended message. We'll assume it's 2010 * the response to our Sync. negotiation. 2011 */ 2012 QPRINTF(("ExtMSG\n")); 2013 2014 /* 2015 * Read in whole extended message. First, negate ACK to accept 2016 * the MSG_EXT_MESSAGE byte... 2017 */ 2018 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2019 2020 /* 2021 * Wait for the interrupt for the next byte (length) 2022 */ 2023 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2024 GET_SBIC_csr(regs, csr); 2025 2026 #ifdef DEBUG 2027 QPRINTF(("CLR ACK csr %02x\n", csr)); 2028 #endif 2029 2030 /* 2031 * Read the length byte 2032 */ 2033 RECV_BYTE(regs, *tmpaddr); 2034 2035 /* 2036 * Wait for command completion IRQ 2037 */ 2038 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2039 GET_SBIC_csr(regs, csr); 2040 2041 /* 2042 * Reload the loop counter 2043 */ 2044 recvlen = *tmpaddr++; 2045 2046 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2047 2048 } else 2049 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2050 msgaddr[2] == MSG_SYNC_REQ ) { 2051 2052 /* 2053 * We've received the complete Extended Message Sync. Request... 2054 */ 2055 QPRINTF(("SYN")); 2056 2057 /* 2058 * Compute the required Transfer Period for the WD chip... 2059 */ 2060 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2061 dev->sc_sync[dev->target].offset = msgaddr[4]; 2062 dev->sc_sync[dev->target].state = SYNC_DONE; 2063 2064 /* 2065 * Put the WD chip in synchronous mode 2066 */ 2067 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2068 dev->sc_sync[dev->target].period)); 2069 #ifdef DEBUG 2070 if ( sync_debug ) 2071 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2072 SBIC_SYN(dev->sc_sync[dev->target].offset, 2073 dev->sc_sync[dev->target].period)); 2074 #endif 2075 2076 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2077 dev->sc_dev.dv_xname, dev->target, 2078 msgaddr[3] * 4, msgaddr[4]); 2079 2080 } else { 2081 2082 /* 2083 * We don't support whatever this message is... 2084 */ 2085 #ifdef DEBUG 2086 if ( sbic_debug || sync_debug ) 2087 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2088 #endif 2089 2090 /* 2091 * prepare to reject the message, NACK 2092 */ 2093 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2094 WAIT_CIP(regs); 2095 } 2096 2097 /* 2098 * Negate ACK to complete the transfer 2099 */ 2100 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2101 2102 /* 2103 * Wait for the interrupt for the next byte, or phase change. 2104 * Only read the CSR if we have more data to transfer. 2105 * XXXSCW: We should really verify that we're still in MSG IN phase 2106 * before blindly going back around this loop, but that would mean 2107 * we read the CSR... <sigh> 2108 */ 2109 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2110 if ( recvlen > 0 ) 2111 GET_SBIC_csr(regs, csr); 2112 2113 } while ( recvlen > 0 ); 2114 2115 /* 2116 * Should still have one CSR to read 2117 */ 2118 return SBIC_STATE_RUNNING; 2119 } 2120 2121 2122 /* 2123 * sbicnextstate() 2124 * return: 2125 * SBIC_STATE_DONE == done 2126 * SBIC_STATE_RUNNING == working 2127 * SBIC_STATE_DISCONNECT == disconnected 2128 * SBIC_STATE_ERROR == error 2129 */ 2130 int 2131 sbicnextstate(dev, csr, asr) 2132 struct sbic_softc *dev; 2133 u_char csr, 2134 asr; 2135 { 2136 sbic_regmap_p regs = dev->sc_sbicp; 2137 struct sbic_acb *acb = dev->sc_nexus; 2138 2139 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2140 2141 switch (csr) { 2142 2143 case SBIC_CSR_XFERRED | CMD_PHASE: 2144 case SBIC_CSR_MIS | CMD_PHASE: 2145 case SBIC_CSR_MIS_1 | CMD_PHASE: 2146 case SBIC_CSR_MIS_2 | CMD_PHASE: 2147 { 2148 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2149 goto abort; 2150 } 2151 break; 2152 2153 case SBIC_CSR_XFERRED | STATUS_PHASE: 2154 case SBIC_CSR_MIS | STATUS_PHASE: 2155 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2156 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2157 { 2158 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2159 2160 /* 2161 * this should be the normal i/o completion case. 2162 * get the status & cmd complete msg then let the 2163 * device driver look at what happened. 2164 */ 2165 sbicxfdone(dev); 2166 2167 #ifdef DEBUG 2168 dev->sc_dmatimo = 0; 2169 if ( data_pointer_debug > 1 ) 2170 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2171 dev->sc_cur->dc_addr, 2172 dev->sc_tcnt); 2173 #endif 2174 /* 2175 * Stop the DMA chip 2176 */ 2177 dev->sc_dmastop(dev); 2178 2179 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2180 2181 /* 2182 * Indicate to the upper layers that the command is done 2183 */ 2184 sbic_scsidone(acb, dev->sc_stat[0]); 2185 2186 return SBIC_STATE_DONE; 2187 } 2188 2189 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2190 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2191 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2192 case SBIC_CSR_MIS | DATA_IN_PHASE: 2193 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2194 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2195 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2196 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2197 { 2198 /* 2199 * Verify that we expected to transfer data... 2200 */ 2201 if ( acb->sc_kv.dc_count <= 0 ) { 2202 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2203 acb->sc_kv.dc_count, asr, csr); 2204 goto abort; 2205 } 2206 2207 /* 2208 * Should we transfer using PIO or DMA ? 2209 */ 2210 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2211 acb->sc_dmacmd == 0 ) { 2212 2213 /* 2214 * Do PIO transfer 2215 */ 2216 int i; 2217 2218 #ifdef DEBUG 2219 if ( data_pointer_debug > 1 ) 2220 printf("next PIO: %d(%p:%x)\n", dev->target, 2221 acb->sc_kv.dc_addr, 2222 acb->sc_kv.dc_count); 2223 #endif 2224 2225 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2226 /* 2227 * data in 2228 */ 2229 i = sbicxfin(regs, acb->sc_kv.dc_count, 2230 acb->sc_kv.dc_addr); 2231 else 2232 /* 2233 * data out 2234 */ 2235 i = sbicxfout(regs, acb->sc_kv.dc_count, 2236 acb->sc_kv.dc_addr); 2237 2238 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2239 acb->sc_kv.dc_count = i; 2240 2241 /* 2242 * Update current count... 2243 */ 2244 acb->sc_tcnt = dev->sc_tcnt = i; 2245 2246 dev->sc_flags &= ~SBICF_INDMA; 2247 2248 } else { 2249 2250 /* 2251 * Do DMA transfer 2252 * set next dma addr and dec count 2253 */ 2254 sbic_save_ptrs(dev); 2255 sbic_load_ptrs(dev); 2256 2257 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2258 SBIC_MACHINE_DMA_MODE); 2259 2260 #ifdef DEBUG 2261 dev->sc_dmatimo = 1; 2262 if ( data_pointer_debug > 1 ) 2263 printf("next DMA: %d(%p:%lx)\n", dev->target, 2264 dev->sc_cur->dc_addr, 2265 dev->sc_tcnt); 2266 #endif 2267 /* 2268 * Start the DMA chip going 2269 */ 2270 dev->sc_tcnt = dev->sc_dmanext(dev); 2271 2272 /* 2273 * Tell the WD chip how much to transfer this time around 2274 */ 2275 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2276 2277 /* 2278 * Start the transfer 2279 */ 2280 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2281 2282 /* 2283 * Indicate that we're in DMA mode 2284 */ 2285 dev->sc_flags |= SBICF_INDMA; 2286 } 2287 } 2288 break; 2289 2290 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2291 case SBIC_CSR_MIS | MESG_IN_PHASE: 2292 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2293 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2294 { 2295 sbic_save_ptrs(dev); 2296 2297 /* 2298 * Handle a single message in... 2299 */ 2300 return sbicmsgin(dev); 2301 } 2302 2303 case SBIC_CSR_MSGIN_W_ACK: 2304 { 2305 /* 2306 * We should never see this since it's handled in 'sbicmsgin()' 2307 * but just for the sake of paranoia... 2308 */ 2309 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2310 printf("Acking unknown msgin CSR:%02x",csr); 2311 } 2312 break; 2313 2314 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2315 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2316 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2317 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2318 { 2319 /* 2320 * We only ever handle a message out phase here for sending a 2321 * REJECT message. 2322 */ 2323 sbic_save_ptrs(dev); 2324 2325 #ifdef DEBUG 2326 if (sync_debug) 2327 printf ("sending REJECT msg to last msg.\n"); 2328 #endif 2329 2330 SEND_BYTE(regs, MSG_REJECT); 2331 WAIT_CIP(regs); 2332 } 2333 break; 2334 2335 case SBIC_CSR_DISC: 2336 case SBIC_CSR_DISC_1: 2337 { 2338 /* 2339 * Try to schedule another target 2340 */ 2341 sbic_save_ptrs(dev); 2342 2343 dev->sc_flags &= ~SBICF_SELECTED; 2344 2345 #ifdef DEBUG 2346 if ( reselect_debug > 1 ) 2347 printf("sbicnext target %d disconnected\n", dev->target); 2348 #endif 2349 2350 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2351 2352 ++dev->sc_tinfo[dev->target].dconns; 2353 2354 dev->sc_nexus = NULL; 2355 dev->sc_xs = NULL; 2356 2357 if ( acb->xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2358 !sbic_parallel_operations ) 2359 return SBIC_STATE_DISCONNECT; 2360 2361 QPRINTF(("sbicnext: calling sbic_sched\n")); 2362 2363 sbic_sched(dev); 2364 2365 QPRINTF(("sbicnext: sbic_sched returned\n")); 2366 2367 return SBIC_STATE_DISCONNECT; 2368 } 2369 2370 case SBIC_CSR_RSLT_NI: 2371 case SBIC_CSR_RSLT_IFY: 2372 { 2373 /* 2374 * A reselection. 2375 * Note that since we don't enable Advanced Features (assuming 2376 * the WD chip is at least the 'A' revision), we're only ever 2377 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2378 * hell of it, we'll handle it anyway, for all the extra code 2379 * it needs... 2380 */ 2381 u_char newtarget, 2382 newlun; 2383 2384 GET_SBIC_rselid(regs, newtarget); 2385 2386 /* 2387 * check SBIC_RID_SIV? 2388 */ 2389 newtarget &= SBIC_RID_MASK; 2390 2391 if ( csr == SBIC_CSR_RSLT_IFY ) { 2392 2393 /* 2394 * Read Identify msg to avoid lockup 2395 */ 2396 GET_SBIC_data(regs, newlun); 2397 WAIT_CIP(regs); 2398 newlun &= SBIC_TLUN_MASK; 2399 2400 } else { 2401 2402 /* 2403 * Need to read Identify message the hard way, assuming 2404 * the target even sends us one... 2405 */ 2406 for (newlun = 255; newlun; --newlun) { 2407 GET_SBIC_asr(regs, asr); 2408 if (asr & SBIC_ASR_INT) 2409 break; 2410 delay(10); 2411 } 2412 2413 /* 2414 * If we didn't get an interrupt, somethink's up 2415 */ 2416 if ( (asr & SBIC_ASR_INT) == 0 ) { 2417 printf("%s: Reselect without identify? asr %x\n", 2418 dev->sc_dev.dv_xname, asr); 2419 newlun = 0; /* XXXX */ 2420 } else { 2421 /* 2422 * We got an interrupt, verify that it's a change to 2423 * message in phase, and if so read the message. 2424 */ 2425 GET_SBIC_csr(regs,csr); 2426 2427 if ( csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2428 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2429 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE) ) { 2430 /* 2431 * Yup, gone to message in. Fetch the target LUN 2432 */ 2433 sbicmsgin(dev); 2434 newlun = dev->sc_msg[0] & 0x07; 2435 2436 } else { 2437 /* 2438 * Whoops! Target didn't go to message in phase!! 2439 */ 2440 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2441 newlun = 0; /* XXXSCW */ 2442 } 2443 } 2444 } 2445 2446 /* 2447 * Ok, we have the identity of the reselecting target. 2448 */ 2449 #ifdef DEBUG 2450 if ( reselect_debug > 1 || 2451 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2452 printf("sbicnext: reselect %s from targ %d lun %d\n", 2453 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2454 } 2455 #endif 2456 2457 if ( dev->sc_nexus ) { 2458 /* 2459 * Whoops! We've been reselected with an command in progress! 2460 * The best we can do is to put the current command back on the 2461 * ready list and hope for the best. 2462 */ 2463 #ifdef DEBUG 2464 if ( reselect_debug > 1 ) { 2465 printf("%s: reselect %s with active command\n", 2466 dev->sc_dev.dv_xname, 2467 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2468 } 2469 #endif 2470 2471 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2472 2473 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2474 2475 dev->sc_nexus = NULL; 2476 dev->sc_xs = NULL; 2477 } 2478 2479 /* 2480 * Reload sync values for this target 2481 */ 2482 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2483 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2484 dev->sc_sync[newtarget].period)); 2485 else 2486 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2487 2488 /* 2489 * Loop through the nexus list until we find the saved entry 2490 * for the reselecting target... 2491 */ 2492 for (acb = dev->nexus_list.tqh_first; acb; 2493 acb = acb->chain.tqe_next) { 2494 2495 if ( acb->xs->sc_link->scsipi_scsi.target == newtarget && 2496 acb->xs->sc_link->scsipi_scsi.lun == newlun) { 2497 /* 2498 * We've found the saved entry. Dequeue it, and 2499 * make it current again. 2500 */ 2501 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2502 2503 dev->sc_nexus = acb; 2504 dev->sc_xs = acb->xs; 2505 dev->sc_flags |= SBICF_SELECTED; 2506 dev->target = newtarget; 2507 dev->lun = newlun; 2508 break; 2509 } 2510 } 2511 2512 if ( acb == NULL ) { 2513 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2514 dev->sc_dev.dv_xname, 2515 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2516 &dev->nexus_list.tqh_first); 2517 panic("bad reselect in sbic"); 2518 } 2519 2520 if ( csr == SBIC_CSR_RSLT_IFY ) 2521 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2522 } 2523 break; 2524 2525 default: 2526 abort: 2527 { 2528 /* 2529 * Something unexpected happened -- deal with it. 2530 */ 2531 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2532 2533 #ifdef DDB 2534 Debugger(); 2535 #endif 2536 2537 #ifdef DEBUG 2538 dev->sc_dmatimo = 0; 2539 if ( data_pointer_debug > 1 ) 2540 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2541 dev->sc_cur->dc_addr, 2542 dev->sc_tcnt); 2543 #endif 2544 2545 dev->sc_dmastop(dev); 2546 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2547 if ( dev->sc_xs ) sbicerror(dev, csr); 2548 sbicabort(dev, "next"); 2549 2550 if ( dev->sc_flags & SBICF_INDMA ) { 2551 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2552 2553 #ifdef DEBUG 2554 dev->sc_dmatimo = 0; 2555 if ( data_pointer_debug > 1 ) 2556 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2557 dev->sc_cur->dc_addr, 2558 dev->sc_tcnt); 2559 #endif 2560 sbic_scsidone(acb, -1); 2561 } 2562 2563 return SBIC_STATE_ERROR; 2564 } 2565 } 2566 2567 return(SBIC_STATE_RUNNING); 2568 } 2569 2570 2571 /* 2572 * Check if DMA can not be used with specified buffer 2573 */ 2574 int 2575 sbiccheckdmap(bp, len, mask) 2576 void *bp; 2577 u_long len, 2578 mask; 2579 { 2580 u_char *buffer; 2581 u_long phy_buf; 2582 u_long phy_len; 2583 2584 buffer = bp; 2585 2586 if ( len == 0 ) 2587 return(1); 2588 2589 while ( len ) { 2590 2591 phy_buf = kvtop((caddr_t)buffer); 2592 phy_len = NBPG - ((int) buffer & PGOFSET); 2593 2594 if ( len < phy_len ) 2595 phy_len = len; 2596 2597 if ( phy_buf & mask ) 2598 return(1); 2599 2600 buffer += phy_len; 2601 len -= phy_len; 2602 } 2603 2604 return(0); 2605 } 2606 2607 int 2608 sbictoscsiperiod(dev, a) 2609 struct sbic_softc *dev; 2610 int a; 2611 { 2612 unsigned int fs; 2613 2614 /* 2615 * cycle = DIV / (2 * CLK) 2616 * DIV = FS + 2 2617 * best we can do is 200ns at 20Mhz, 2 cycles 2618 */ 2619 2620 GET_SBIC_myid(dev->sc_sbicp, fs); 2621 2622 fs = (fs >> 6) + 2; /* DIV */ 2623 2624 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2625 2626 if ( a < 2 ) 2627 a = 8; /* map to Cycles */ 2628 2629 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2630 } 2631 2632 int 2633 sbicfromscsiperiod(dev, p) 2634 struct sbic_softc *dev; 2635 int p; 2636 { 2637 unsigned fs, 2638 ret; 2639 2640 /* 2641 * Just the inverse of the above 2642 */ 2643 GET_SBIC_myid(dev->sc_sbicp, fs); 2644 2645 fs = (fs >> 6) + 2; /* DIV */ 2646 2647 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2648 2649 ret = p << 2; /* in ns units */ 2650 ret = ret / fs; /* in Cycles */ 2651 2652 if ( ret < sbic_min_period ) 2653 return(sbic_min_period); 2654 2655 /* 2656 * verify rounding 2657 */ 2658 if ( sbictoscsiperiod(dev, ret) < p ) 2659 ret++; 2660 2661 return( (ret >= 8) ? 0 : ret ); 2662 } 2663 2664 #ifdef DEBUG 2665 void 2666 sbictimeout(dev) 2667 struct sbic_softc *dev; 2668 { 2669 int s, 2670 asr; 2671 2672 s = splbio(); 2673 2674 if ( dev->sc_dmatimo ) { 2675 2676 if ( dev->sc_dmatimo > 1 ) { 2677 2678 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2679 dev->sc_dmatimo - 1); 2680 2681 GET_SBIC_asr(dev->sc_sbicp, asr); 2682 2683 if ( asr & SBIC_ASR_INT ) { 2684 /* 2685 * We need to service a missed IRQ 2686 */ 2687 sbicintr(dev); 2688 } else { 2689 (void) sbicabort(dev, "timeout"); 2690 splx(s); 2691 return; 2692 } 2693 } 2694 2695 dev->sc_dmatimo++; 2696 } 2697 2698 splx(s); 2699 2700 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 2701 } 2702 #endif 2703
Indexes created Tue Sep 30 07:10:03 GMT 2025