sbic.c revision 1.18
1 /* $NetBSD: sbic.c,v 1.18 2001/07/22 13:34:06 wiz Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 #include "opt_ddb.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/kernel.h> /* For hz */ 61 #include <sys/disklabel.h> 62 #include <sys/dkstat.h> 63 #include <sys/buf.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <uvm/uvm_extern.h> 70 71 #include <mvme68k/mvme68k/isr.h> 72 #include <mvme68k/dev/dmavar.h> 73 #include <mvme68k/dev/sbicreg.h> 74 #include <mvme68k/dev/sbicvar.h> 75 76 77 /* 78 * Since I can't find this in any other header files 79 */ 80 #define SCSI_PHASE(reg) (reg&0x07) 81 82 /* 83 * SCSI delays 84 * In u-seconds, primarily for state changes on the SPC. 85 */ 86 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 87 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 88 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 89 90 /* 91 * Convenience macro for waiting for a particular sbic event 92 */ 93 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 94 95 extern paddr_t kvtop __P((caddr_t)); 96 97 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 98 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 99 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 100 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 101 int sbiccheckdmap __P((void *, u_long, u_long)); 102 u_char sbicselectbus __P((struct sbic_softc *)); 103 int sbicxfout __P((sbic_regmap_p, int, void *)); 104 int sbicxfin __P((sbic_regmap_p, int, void *)); 105 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 106 int sbictoscsiperiod __P((struct sbic_softc *, int)); 107 int sbicpoll __P((struct sbic_softc *)); 108 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 109 int sbicmsgin __P((struct sbic_softc *)); 110 int sbicabort __P((struct sbic_softc *, char *)); 111 void sbicxfdone __P((struct sbic_softc *)); 112 void sbicerror __P((struct sbic_softc *,u_char)); 113 void sbicreset __P((struct sbic_softc *)); 114 void sbic_scsidone __P((struct sbic_acb *, int)); 115 void sbic_sched __P((struct sbic_softc *)); 116 void sbic_save_ptrs __P((struct sbic_softc *)); 117 void sbic_load_ptrs __P((struct sbic_softc *)); 118 119 /* 120 * Synch xfer parameters, and timing conversions 121 */ 122 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 123 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 124 int sbic_cmd_wait = SBIC_CMD_WAIT; 125 int sbic_data_wait = SBIC_DATA_WAIT; 126 int sbic_init_wait = SBIC_INIT_WAIT; 127 128 /* 129 * was broken before.. now if you want this you get it for all drives 130 * on sbic controllers. 131 */ 132 u_char sbic_inhibit_sync[8]; 133 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 134 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 135 int sbic_parallel_operations = 1; /* Allow command queues */ 136 137 /* 138 * Some useful stuff for debugging purposes 139 */ 140 #ifdef DEBUG 141 int sbicdma_ops = 0; /* total DMA operations */ 142 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 143 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 144 int sbicdma_saves = 0; 145 146 #define QPRINTF(a) if (sbic_debug > 1) printf a 147 148 int sbic_debug = 0; /* Debug all chip related things */ 149 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 150 int reselect_debug = 0; /* Debug all reselection related things */ 151 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 152 153 void sbictimeout __P((struct sbic_softc *dev)); 154 155 #else 156 #define QPRINTF(a) /* */ 157 #endif 158 159 160 /* 161 * default minphys routine for sbic based controllers 162 */ 163 void 164 sbic_minphys(bp) 165 struct buf *bp; 166 { 167 /* 168 * No max transfer at this level. 169 */ 170 minphys(bp); 171 } 172 173 174 /* 175 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 176 */ 177 void 178 sbic_save_ptrs(dev) 179 struct sbic_softc *dev; 180 { 181 sbic_regmap_p regs; 182 struct sbic_acb* acb; 183 int count, 184 asr, 185 s; 186 187 /* 188 * Only need to save pointers if DMA was active... 189 */ 190 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 191 return; 192 193 regs = dev->sc_sbicp; 194 195 s = splbio(); 196 197 /* 198 * Wait until WD chip is idle 199 */ 200 do { 201 GET_SBIC_asr(regs, asr); 202 if( asr & SBIC_ASR_DBR ) { 203 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 204 splx(s); 205 return; 206 } 207 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 208 209 210 /* 211 * Save important state. 212 * must be done before dmastop 213 */ 214 acb = dev->sc_nexus; 215 acb->sc_dmacmd = dev->sc_dmacmd; 216 217 /* 218 * Fetch the residual count 219 */ 220 SBIC_TC_GET(regs, count); 221 222 /* 223 * Shut down DMA 224 */ 225 dev->sc_dmastop(dev); 226 227 /* 228 * No longer in DMA 229 */ 230 dev->sc_flags &= ~SBICF_INDMA; 231 232 /* 233 * Ensure the WD chip is back in polled I/O mode, with nothing to 234 * transfer. 235 */ 236 SBIC_TC_PUT(regs, 0); 237 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 238 239 /* 240 * Update current count... 241 */ 242 acb->sc_tcnt = count; 243 244 /* 245 * Work out how many bytes were actually transferred 246 */ 247 count = dev->sc_tcnt - count; 248 dev->sc_tcnt = acb->sc_tcnt; 249 250 /* 251 * Fixup partial xfers 252 */ 253 acb->sc_kv.dc_addr += count; 254 acb->sc_kv.dc_count -= count; 255 acb->sc_pa.dc_addr += count; 256 acb->sc_pa.dc_count -= count >> 1; 257 258 #ifdef DEBUG 259 if ( data_pointer_debug ) 260 printf("save at (%p,%x):%x\n", 261 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 262 sbicdma_saves++; 263 #endif 264 265 splx(s); 266 } 267 268 269 /* 270 * DOES NOT RESTART DMA!!! 271 */ 272 void 273 sbic_load_ptrs(dev) 274 struct sbic_softc *dev; 275 { 276 struct sbic_acb *acb = dev->sc_nexus; 277 int s; 278 279 if ( acb->sc_kv.dc_count == 0 ) { 280 /* 281 * No data to xfer 282 */ 283 return; 284 } 285 286 s = splbio(); 287 288 /* 289 * Reset the Scatter-Gather chain 290 */ 291 dev->sc_last = dev->sc_cur = &acb->sc_pa; 292 293 /* 294 * Restore the Transfer Count and DMA specific data 295 */ 296 dev->sc_tcnt = acb->sc_tcnt; 297 dev->sc_dmacmd = acb->sc_dmacmd; 298 299 #ifdef DEBUG 300 sbicdma_ops++; 301 #endif 302 303 /* 304 * Need to fixup new segment? 305 */ 306 if ( dev->sc_tcnt == 0 ) { 307 /* 308 * sc_tcnt == 0 implies end of segment 309 */ 310 char *vaddr, *paddr; 311 int count; 312 313 /* 314 * do kvm to pa mappings 315 */ 316 vaddr = acb->sc_kv.dc_addr; 317 paddr = acb->sc_pa.dc_addr = (char *) kvtop((caddr_t)vaddr); 318 319 for (count = (NBPG - ((int)vaddr & PGOFSET)); 320 count < acb->sc_kv.dc_count && 321 (char*)kvtop((caddr_t)(vaddr + count + 4)) == paddr + count + 4; 322 count += NBPG) 323 ; /* Do nothing */ 324 325 /* 326 * If it's all contiguous... 327 */ 328 if ( count > acb->sc_kv.dc_count ) { 329 count = acb->sc_kv.dc_count; 330 #ifdef DEBUG 331 sbicdma_hits++; 332 #endif 333 } 334 #ifdef DEBUG 335 else 336 sbicdma_misses++; 337 #endif 338 339 acb->sc_tcnt = count; 340 acb->sc_pa.dc_count = count >> 1; 341 342 #ifdef DEBUG 343 if ( data_pointer_debug ) 344 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", acb->sc_kv.dc_addr, 345 acb->sc_kv.dc_count, 346 acb->sc_pa.dc_addr, 347 acb->sc_tcnt); 348 #endif 349 350 } 351 352 splx(s); 353 } 354 355 /* 356 * used by specific sbic controller 357 * 358 * it appears that the higher level code does nothing with LUN's 359 * so I will too. I could plug it in, however so could they 360 * in scsi_scsipi_cmd(). 361 */ 362 void 363 sbic_scsi_request(chan, req, arg) 364 struct scsipi_channel *chan; 365 scsipi_adapter_req_t req; 366 void *arg; 367 { 368 struct scsipi_xfer *xs; 369 struct scsipi_periph *periph; 370 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 371 struct sbic_acb *acb; 372 int flags, s; 373 374 switch (req) { 375 case ADAPTER_REQ_RUN_XFER: 376 xs = arg; 377 periph = xs->xs_periph; 378 flags = xs->xs_control; 379 380 if ( flags & XS_CTL_DATA_UIO ) 381 panic("sbic: scsi data uio requested"); 382 383 if ( dev->sc_nexus && (flags & XS_CTL_POLL) ) 384 panic("sbic_scsicmd: busy"); 385 386 s = splbio(); 387 388 if ( (acb = dev->free_list.tqh_first) != NULL ) 389 TAILQ_REMOVE(&dev->free_list, acb, chain); 390 391 splx(s); 392 393 if ( acb == NULL ) { 394 #ifdef DEBUG 395 printf("sbic_scsicmd: unable to queue request for target %d\n", 396 periph->periph_target); 397 #ifdef DDB 398 Debugger(); 399 #endif 400 #endif 401 xs->error = XS_RESOURCE_SHORTAGE; 402 scsipi_done(xs); 403 return; 404 } 405 406 if ( flags & XS_CTL_DATA_IN ) 407 acb->flags = ACB_ACTIVE | ACB_DATAIN; 408 else 409 acb->flags = ACB_ACTIVE; 410 411 acb->xs = xs; 412 acb->clen = xs->cmdlen; 413 acb->sc_kv.dc_addr = xs->data; 414 acb->sc_kv.dc_count = xs->datalen; 415 acb->pa_addr = xs->data ? (char *)kvtop((caddr_t)xs->data) : 0; 416 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 417 418 if ( flags & XS_CTL_POLL ) { 419 /* 420 * This has major side effects -- it locks up the machine 421 */ 422 int stat; 423 424 s = splbio(); 425 426 dev->sc_flags |= SBICF_ICMD; 427 428 do { 429 /* 430 * If we already had a nexus, while away the time until idle... 431 * This is likely only to happen if a reselection occurs between 432 * here and our earlier check for ICMD && sc_nexus (which would 433 * have resulted in a panic() had it been true). 434 */ 435 while ( dev->sc_nexus ) 436 sbicpoll(dev); 437 438 /* 439 * Fix up the new nexus 440 */ 441 dev->sc_nexus = acb; 442 dev->sc_xs = xs; 443 dev->target = periph->periph_target; 444 dev->lun = periph->periph_lun; 445 446 stat = sbicicmd(dev, &acb->cmd, acb->clen, 447 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 448 449 } while ( dev->sc_nexus != acb ); 450 451 sbic_scsidone(acb, stat); 452 453 splx(s); 454 455 return; 456 } 457 458 s = splbio(); 459 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 460 461 /* 462 * If nothing is active, try to start it now. 463 */ 464 if ( dev->sc_nexus == NULL ) 465 sbic_sched(dev); 466 467 splx(s); 468 469 return; 470 471 case ADAPTER_REQ_GROW_RESOURCES: 472 /* XXX Not supported. */ 473 return; 474 475 case ADAPTER_REQ_SET_XFER_MODE: 476 /* XXX Not supported. */ 477 return; 478 } 479 480 } 481 482 /* 483 * attempt to start the next available command 484 */ 485 void 486 sbic_sched(dev) 487 struct sbic_softc *dev; 488 { 489 struct scsipi_xfer *xs; 490 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 491 struct sbic_acb *acb; 492 int flags, 493 stat; 494 495 /* 496 * XXXSCW 497 * I'll keep this test here, even though I can't see any obvious way 498 * in which sbic_sched() could be called with sc_nexus non NULL 499 */ 500 if ( dev->sc_nexus ) 501 return; /* a command is current active */ 502 503 /* 504 * Loop through the ready list looking for work to do... 505 */ 506 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 507 int i, j; 508 509 periph = acb->xs->xs_periph; 510 i = periph->periph_target; 511 j = 1 << periph->periph_lun; 512 513 /* 514 * We've found a potential command, but is the target/lun busy? 515 */ 516 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 517 /* 518 * Nope, it's not busy, so we can use it. 519 */ 520 dev->sc_tinfo[i].lubusy |= j; 521 TAILQ_REMOVE(&dev->ready_list, acb, chain); 522 dev->sc_nexus = acb; 523 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 524 break; 525 } 526 } 527 528 if ( acb == NULL ) { 529 QPRINTF(("sbicsched: no work\n")); 530 return; /* did not find an available command */ 531 } 532 533 #ifdef DEBUG 534 if ( data_pointer_debug > 1 ) 535 printf("sbic_sched(%d,%d)\n", periph->periph_target, 536 periph->periph_lun); 537 #endif 538 539 dev->sc_xs = xs = acb->xs; 540 flags = xs->xs_control; 541 542 if ( flags & XS_CTL_RESET ) 543 sbicreset(dev); 544 545 dev->sc_stat[0] = -1; 546 dev->target = periph->periph_target; 547 dev->lun = periph->periph_lun; 548 549 if ( flags & XS_CTL_POLL || (!sbic_parallel_operations && 550 (sbicdmaok(dev, xs) == 0)) ) 551 stat = sbicicmd(dev, &acb->cmd, acb->clen, 552 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 553 else 554 if ( sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT ) 555 return; 556 else 557 stat = dev->sc_stat[0]; 558 559 sbic_scsidone(acb, stat); 560 } 561 562 void 563 sbic_scsidone(acb, stat) 564 struct sbic_acb *acb; 565 int stat; 566 { 567 struct scsipi_xfer *xs = acb->xs; 568 struct scsipi_periph *periph = xs->xs_periph; 569 struct sbic_softc *dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 570 int dosched = 0; 571 572 #ifdef DIAGNOSTIC 573 if ( acb == NULL || xs == NULL ) { 574 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); 575 #ifdef DDB 576 Debugger(); 577 #endif 578 return; 579 } 580 #endif 581 582 583 #ifdef DEBUG 584 if ( data_pointer_debug > 1 ) 585 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", periph->periph_target, 586 periph->periph_lun, 587 dev->target, dev->lun, stat); 588 589 if ( xs->xs_periph->periph_target == dev->sc_channel.chan_id) 590 panic("target == hostid"); 591 #endif 592 593 xs->status = stat; 594 xs->resid = 0; /* XXXX */ 595 if ( xs->error == XS_NOERROR) { 596 if ( stat == SCSI_CHECK || stat == SCSI_BUSY) 597 xs->error = XS_BUSY; 598 } 599 600 601 /* 602 * Remove the ACB from whatever queue it's on. We have to do a bit of 603 * a hack to figure out which queue it's on. Note that it is *not* 604 * necessary to cdr down the ready queue, but we must cdr down the 605 * nexus queue and see if it's there, so we can mark the unit as no 606 * longer busy. This code is sickening, but it works. 607 */ 608 if ( acb == dev->sc_nexus ) { 609 610 dev->sc_nexus = NULL; 611 dev->sc_xs = NULL; 612 613 dev->sc_tinfo[periph->periph_target].lubusy &= 614 ~(1 << periph->periph_lun); 615 616 if ( dev->ready_list.tqh_first ) 617 dosched = 1; /* start next command */ 618 619 } else 620 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 621 622 TAILQ_REMOVE(&dev->ready_list, acb, chain); 623 624 } else { 625 626 struct sbic_acb *a; 627 628 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 629 if ( a == acb ) { 630 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 631 dev->sc_tinfo[periph->periph_target].lubusy &= 632 ~(1 << periph->periph_lun); 633 break; 634 } 635 } 636 637 if ( a ) 638 ; 639 else if ( acb->chain.tqe_next ) { 640 TAILQ_REMOVE(&dev->ready_list, acb, chain); 641 } else { 642 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 643 #ifdef DDB 644 Debugger(); 645 #endif 646 } 647 } 648 649 /* 650 * Put it on the free list. 651 */ 652 acb->flags = ACB_FREE; 653 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 654 655 dev->sc_tinfo[periph->periph_target].cmds++; 656 657 scsipi_done(xs); 658 659 if ( dosched ) 660 sbic_sched(dev); 661 } 662 663 int 664 sbicdmaok(dev, xs) 665 struct sbic_softc *dev; 666 struct scsipi_xfer *xs; 667 { 668 if ( sbic_no_dma || xs->datalen == 0 || 669 xs->datalen & 0x03 || (int)xs->data & 0x03) 670 return(0); 671 672 /* 673 * controller supports dma to any addresses? 674 */ 675 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 676 return(1); 677 678 /* 679 * this address is ok for dma? 680 */ 681 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 682 return(1); 683 684 return(0); 685 } 686 687 int 688 sbicwait(regs, until, timeo, line) 689 sbic_regmap_p regs; 690 u_char until; 691 int timeo; 692 int line; 693 { 694 u_char val; 695 696 if ( timeo == 0 ) 697 timeo = 1000000; /* some large value.. */ 698 699 GET_SBIC_asr(regs, val); 700 701 while ( (val & until) == 0 ) { 702 703 if ( timeo-- == 0 ) { 704 int csr; 705 GET_SBIC_csr(regs, csr); 706 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 707 #if defined(DDB) && defined(DEBUG) 708 Debugger(); 709 #endif 710 return(val); /* Maybe I should abort */ 711 break; 712 } 713 714 DELAY(1); 715 GET_SBIC_asr(regs, val); 716 } 717 718 return(val); 719 } 720 721 int 722 sbicabort(dev, where) 723 struct sbic_softc *dev; 724 char *where; 725 { 726 sbic_regmap_p regs = dev->sc_sbicp; 727 u_char csr, 728 asr; 729 730 GET_SBIC_asr(regs, asr); 731 GET_SBIC_csr(regs, csr); 732 733 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 734 dev->sc_dev.dv_xname, where, csr, asr); 735 736 /* 737 * Clean up chip itself 738 */ 739 if ( dev->sc_flags & SBICF_SELECTED ) { 740 741 while ( asr & SBIC_ASR_DBR ) { 742 /* 743 * sbic is jammed w/data. need to clear it 744 * But we don't know what direction it needs to go 745 */ 746 GET_SBIC_data(regs, asr); 747 printf("%s: abort %s: clearing data buffer 0x%02x\n", 748 dev->sc_dev.dv_xname, where, asr); 749 GET_SBIC_asr(regs, asr); 750 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 751 SET_SBIC_data(regs, asr); 752 GET_SBIC_asr(regs, asr); 753 } 754 755 WAIT_CIP(regs); 756 757 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 758 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 759 WAIT_CIP(regs); 760 761 GET_SBIC_asr(regs, asr); 762 763 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 764 /* 765 * ok, get more drastic.. 766 */ 767 printf("%s: sbicabort - asr %x, trying to reset\n", 768 dev->sc_dev.dv_xname, asr); 769 sbicreset(dev); 770 dev->sc_flags &= ~SBICF_SELECTED; 771 return SBIC_STATE_ERROR; 772 } 773 774 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 775 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 776 777 do { 778 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 779 GET_SBIC_asr(regs, asr); 780 GET_SBIC_csr (regs, csr); 781 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 782 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 783 (csr != SBIC_CSR_CMD_INVALID) ); 784 785 /* 786 * lets just hope it worked.. 787 */ 788 dev->sc_flags &= ~SBICF_SELECTED; 789 } 790 791 return SBIC_STATE_ERROR; 792 } 793 794 795 /* 796 * Initialize driver-private structures 797 */ 798 void 799 sbicinit(dev) 800 struct sbic_softc *dev; 801 { 802 u_int i; 803 804 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 805 806 struct sbic_acb *acb; 807 808 TAILQ_INIT(&dev->ready_list); 809 TAILQ_INIT(&dev->nexus_list); 810 TAILQ_INIT(&dev->free_list); 811 callout_init(&dev->sc_timo_ch); 812 813 dev->sc_nexus = NULL; 814 dev->sc_xs = NULL; 815 816 acb = dev->sc_acb; 817 memset(acb, 0, sizeof(dev->sc_acb)); 818 819 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 820 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 821 acb++; 822 } 823 824 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 825 826 #ifdef DEBUG 827 /* 828 * make sure timeout is really not needed 829 */ 830 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 831 #endif 832 833 } else 834 panic("sbic: reinitializing driver!"); 835 836 dev->sc_flags |= SBICF_ALIVE; 837 dev->sc_flags &= ~SBICF_SELECTED; 838 839 /* 840 * initialize inhibit array 841 * Never enable Sync, since it just doesn't work on mvme147 :( 842 */ 843 for (i = 0; i < 8; ++i) 844 sbic_inhibit_sync[i] = 1; 845 846 sbicreset(dev); 847 } 848 849 void 850 sbicreset(dev) 851 struct sbic_softc *dev; 852 { 853 sbic_regmap_p regs = dev->sc_sbicp; 854 u_int my_id, 855 s; 856 u_char csr; 857 858 s = splbio(); 859 860 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 861 862 if (dev->sc_clkfreq < 110) 863 my_id |= SBIC_ID_FS_8_10; 864 else if (dev->sc_clkfreq < 160) 865 my_id |= SBIC_ID_FS_12_15; 866 else if (dev->sc_clkfreq < 210) 867 my_id |= SBIC_ID_FS_16_20; 868 869 SET_SBIC_myid(regs, my_id); 870 871 /* 872 * Reset the chip 873 */ 874 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 875 DELAY(25); 876 877 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 878 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 879 880 /* 881 * Set up various chip parameters 882 */ 883 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 884 885 /* 886 * don't allow Selection (SBIC_RID_ES) 887 * until we can handle target mode!! 888 */ 889 SET_SBIC_rselid(regs, SBIC_RID_ER); 890 891 /* 892 * Asynchronous for now 893 */ 894 SET_SBIC_syn(regs, 0); 895 896 /* 897 * Anything else was zeroed by reset 898 */ 899 splx(s); 900 901 dev->sc_flags &= ~SBICF_SELECTED; 902 } 903 904 void 905 sbicerror(dev, csr) 906 struct sbic_softc *dev; 907 u_char csr; 908 { 909 struct scsipi_xfer *xs = dev->sc_xs; 910 911 #ifdef DIAGNOSTIC 912 if ( xs == NULL ) 913 panic("sbicerror: dev->sc_xs == NULL"); 914 #endif 915 916 if ( xs->xs_control & XS_CTL_SILENT ) 917 return; 918 919 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 920 } 921 922 /* 923 * select the bus, return when selected or error. 924 * 925 * Returns the current CSR following selection and optionally MSG out phase. 926 * i.e. the returned CSR *should* indicate CMD phase... 927 * If the return value is 0, some error happened. 928 */ 929 u_char 930 sbicselectbus(dev) 931 struct sbic_softc *dev; 932 { 933 sbic_regmap_p regs = dev->sc_sbicp; 934 u_char target = dev->target, 935 lun = dev->lun, 936 asr, 937 csr, 938 id; 939 940 /* 941 * if we're already selected, return (XXXX panic maybe?) 942 */ 943 if ( dev->sc_flags & SBICF_SELECTED ) 944 return(0); 945 946 QPRINTF(("sbicselectbus %d: ", target)); 947 948 /* 949 * issue select 950 */ 951 SET_SBIC_selid(regs, target); 952 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 953 954 GET_SBIC_asr(regs, asr); 955 956 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 957 /* 958 * This means we got ourselves reselected upon 959 */ 960 QPRINTF(("WD busy (reselect?)\n")); 961 return 0; 962 } 963 964 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 965 966 /* 967 * wait for select (merged from separate function may need 968 * cleanup) 969 */ 970 WAIT_CIP(regs); 971 972 do { 973 974 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 975 976 if ( asr & SBIC_ASR_LCI ) { 977 QPRINTF(("late LCI: asr %02x\n", asr)); 978 return 0; 979 } 980 981 /* 982 * Clear interrupt 983 */ 984 GET_SBIC_csr (regs, csr); 985 986 QPRINTF(("%02x ", csr)); 987 988 /* 989 * Reselected from under our feet? 990 */ 991 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 992 QPRINTF(("got reselected, asr %02x\n", asr)); 993 /* 994 * We need to handle this now so we don't lock up later 995 */ 996 sbicnextstate(dev, csr, asr); 997 998 return 0; 999 } 1000 1001 /* 1002 * Whoops! 1003 */ 1004 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1005 panic("sbicselectbus: target issued select!"); 1006 return 0; 1007 } 1008 1009 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1010 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1011 csr != SBIC_CSR_SEL_TIMEO); 1012 1013 /* 1014 * Anyone at home? 1015 */ 1016 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1017 dev->sc_xs->error = XS_SELTIMEOUT; 1018 QPRINTF(("Selection Timeout\n")); 1019 return 0; 1020 } 1021 1022 QPRINTF(("Selection Complete\n")); 1023 1024 /* 1025 * Assume we're now selected 1026 */ 1027 GET_SBIC_selid(regs, id); 1028 dev->target = id; 1029 dev->lun = lun; 1030 dev->sc_flags |= SBICF_SELECTED; 1031 1032 /* 1033 * Enable (or not) reselection 1034 * XXXSCW This is probably not necessary since we don't use use the 1035 * Select-and-Xfer-with-ATN command to initiate a selection... 1036 */ 1037 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1038 SET_SBIC_rselid (regs, 0); 1039 else 1040 SET_SBIC_rselid (regs, SBIC_RID_ER); 1041 1042 /* 1043 * We only really need to do anything when the target goes to MSG out 1044 * If the device ignored ATN, it's probably old and brain-dead, 1045 * but we'll try to support it anyhow. 1046 * If it doesn't support message out, it definately doesn't 1047 * support synchronous transfers, so no point in even asking... 1048 */ 1049 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1050 /* 1051 * Send identify message (SCSI-2 requires an identify msg) 1052 */ 1053 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1054 /* 1055 * Handle drives that don't want to be asked 1056 * whether to go sync at all. 1057 */ 1058 dev->sc_sync[id].offset = 0; 1059 dev->sc_sync[id].period = sbic_min_period; 1060 dev->sc_sync[id].state = SYNC_DONE; 1061 } 1062 1063 /* 1064 * Do we need to negotiate Synchronous Xfers for this target? 1065 */ 1066 if ( dev->sc_sync[id].state != SYNC_START ) { 1067 /* 1068 * Nope, we've already negotiated. 1069 * Now see if we should allow the target to disconnect/reselect... 1070 */ 1071 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 1072 !sbic_enable_reselect ) 1073 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1074 else 1075 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1076 1077 } else { 1078 /* 1079 * try to initiate a sync transfer. 1080 * So compose the sync message we're going 1081 * to send to the target 1082 */ 1083 #ifdef DEBUG 1084 if ( sync_debug ) 1085 printf("\nSending sync request to target %d ... ", id); 1086 #endif 1087 /* 1088 * setup scsi message sync message request 1089 */ 1090 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1091 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1092 dev->sc_msg[2] = 3; 1093 dev->sc_msg[3] = MSG_SYNC_REQ; 1094 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1095 dev->sc_msg[5] = sbic_max_offset; 1096 1097 sbicxfout(regs, 6, dev->sc_msg); 1098 1099 dev->sc_sync[id].state = SYNC_SENT; 1100 #ifdef DEBUG 1101 if ( sync_debug ) 1102 printf ("sent\n"); 1103 #endif 1104 } 1105 1106 /* 1107 * There's one interrupt still to come: the change to CMD phase... 1108 */ 1109 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1110 GET_SBIC_csr(regs, csr); 1111 } 1112 1113 /* 1114 * set sync or async 1115 */ 1116 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1117 #ifdef DEBUG 1118 if ( sync_debug ) 1119 printf("select(%d): sync reg = 0x%02x\n", target, 1120 SBIC_SYN(dev->sc_sync[target].offset, 1121 dev->sc_sync[target].period)); 1122 #endif 1123 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1124 dev->sc_sync[target].period)); 1125 } else { 1126 #ifdef DEBUG 1127 if ( sync_debug ) 1128 printf("select(%d): sync reg = 0x%02x\n", target, 1129 SBIC_SYN(0,sbic_min_period)); 1130 #endif 1131 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1132 } 1133 1134 return csr; 1135 } 1136 1137 /* 1138 * Information Transfer *to* a Scsi Target. 1139 * 1140 * Note: Don't expect there to be an interrupt immediately after all 1141 * the data is transferred out. The WD spec sheet says that the Transfer- 1142 * Info command for non-MSG_IN phases only completes when the target 1143 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1144 * 1145 * This can have a nasty effect on commands which take a relatively long 1146 * time to complete, for example a START/STOP unit command may remain in 1147 * CMD phase until the disk has spun up. Only then will the target change 1148 * to STATUS phase. This is really only a problem for immediate commands 1149 * since we don't allow disconnection for them (yet). 1150 */ 1151 int 1152 sbicxfout(regs, len, bp) 1153 sbic_regmap_p regs; 1154 int len; 1155 void *bp; 1156 { 1157 int wait = sbic_data_wait; 1158 u_char asr, 1159 *buf = bp; 1160 1161 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1162 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1163 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1164 1165 /* 1166 * sigh.. WD-PROTO strikes again.. sending the command in one go 1167 * causes the chip to lock up if talking to certain (misbehaving?) 1168 * targets. Anyway, this procedure should work for all targets, but 1169 * it's slightly slower due to the overhead 1170 */ 1171 WAIT_CIP (regs); 1172 1173 SBIC_TC_PUT (regs, 0); 1174 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1175 SBIC_TC_PUT (regs, (unsigned)len); 1176 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1177 1178 /* 1179 * Loop for each byte transferred 1180 */ 1181 do { 1182 1183 GET_SBIC_asr (regs, asr); 1184 1185 if ( asr & SBIC_ASR_DBR ) { 1186 if ( len ) { 1187 SET_SBIC_data (regs, *buf); 1188 buf++; 1189 len--; 1190 } else { 1191 SET_SBIC_data (regs, 0); 1192 } 1193 wait = sbic_data_wait; 1194 } 1195 1196 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1197 1198 #ifdef DEBUG 1199 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1200 #endif 1201 1202 /* 1203 * Normally, an interrupt will be pending when this routing returns. 1204 */ 1205 return(len); 1206 } 1207 1208 /* 1209 * Information Transfer *from* a Scsi Target 1210 * returns # bytes left to read 1211 */ 1212 int 1213 sbicxfin(regs, len, bp) 1214 sbic_regmap_p regs; 1215 int len; 1216 void *bp; 1217 { 1218 int wait = sbic_data_wait; 1219 u_char *buf = bp; 1220 u_char asr; 1221 #ifdef DEBUG 1222 u_char *obp = bp; 1223 #endif 1224 1225 WAIT_CIP (regs); 1226 1227 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1228 SBIC_TC_PUT (regs, (unsigned)len); 1229 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1230 1231 /* 1232 * Loop for each byte transferred 1233 */ 1234 do { 1235 1236 GET_SBIC_asr (regs, asr); 1237 1238 if ( asr & SBIC_ASR_DBR ) { 1239 if ( len ) { 1240 GET_SBIC_data (regs, *buf); 1241 buf++; 1242 len--; 1243 } else { 1244 u_char foo; 1245 GET_SBIC_data (regs, foo); 1246 } 1247 wait = sbic_data_wait; 1248 } 1249 1250 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1251 1252 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1253 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1254 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1255 1256 SBIC_TC_PUT (regs, 0); 1257 1258 /* 1259 * this leaves with one csr to be read 1260 */ 1261 return len; 1262 } 1263 1264 /* 1265 * SCSI 'immediate' command: issue a command to some SCSI device 1266 * and get back an 'immediate' response (i.e., do programmed xfer 1267 * to get the response data). 'cbuf' is a buffer containing a scsi 1268 * command of length clen bytes. 'buf' is a buffer of length 'len' 1269 * bytes for data. The transfer direction is determined by the device 1270 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1271 * command must supply no data. 1272 * 1273 * Note that although this routine looks like it can handle disconnect/ 1274 * reselect, the fact is that it can't. There is still some work to be 1275 * done to clean this lot up. 1276 */ 1277 int 1278 sbicicmd(dev, cbuf, clen, buf, len) 1279 struct sbic_softc *dev; 1280 void *cbuf, 1281 *buf; 1282 int clen, 1283 len; 1284 { 1285 sbic_regmap_p regs = dev->sc_sbicp; 1286 struct sbic_acb *acb = dev->sc_nexus; 1287 u_char csr, 1288 asr; 1289 int still_busy = SBIC_STATE_RUNNING; 1290 1291 /* 1292 * Make sure pointers are OK 1293 */ 1294 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1295 dev->sc_tcnt = acb->sc_tcnt = 0; 1296 1297 acb->sc_dmacmd = 0; 1298 acb->sc_pa.dc_count = 0; /* No DMA */ 1299 acb->sc_kv.dc_addr = buf; 1300 acb->sc_kv.dc_count = len; 1301 1302 #ifdef DEBUG 1303 if ( data_pointer_debug > 1 ) 1304 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1305 #endif 1306 1307 /* 1308 * set the sbic into non-DMA mode 1309 */ 1310 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1311 1312 dev->sc_stat[0] = 0xff; 1313 dev->sc_msg[0] = 0xff; 1314 1315 /* 1316 * We're stealing the SCSI bus 1317 */ 1318 dev->sc_flags |= SBICF_ICMD; 1319 1320 do { 1321 GET_SBIC_asr (regs, asr); 1322 1323 /* 1324 * select the SCSI bus (it's an error if bus isn't free) 1325 */ 1326 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1327 still_busy != SBIC_STATE_DISCONNECT ) { 1328 if ( (csr = sbicselectbus(dev)) == 0 ) { 1329 dev->sc_flags &= ~SBICF_ICMD; 1330 return(-1); 1331 } 1332 } else 1333 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1334 GET_SBIC_csr(regs, csr); 1335 else 1336 csr = 0; 1337 1338 if ( csr ) { 1339 1340 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1341 1342 switch ( csr ) { 1343 1344 case SBIC_CSR_S_XFERRED: 1345 case SBIC_CSR_DISC: 1346 case SBIC_CSR_DISC_1: 1347 { 1348 u_char phase; 1349 1350 dev->sc_flags &= ~SBICF_SELECTED; 1351 GET_SBIC_cmd_phase (regs, phase); 1352 1353 if ( phase == 0x60 ) { 1354 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1355 still_busy = SBIC_STATE_DONE; /* done */ 1356 } else { 1357 #ifdef DEBUG 1358 if ( reselect_debug > 1 ) 1359 printf("sbicicmd: handling disconnect\n"); 1360 #endif 1361 still_busy = SBIC_STATE_DISCONNECT; 1362 } 1363 } 1364 break; 1365 1366 case SBIC_CSR_XFERRED | CMD_PHASE: 1367 case SBIC_CSR_MIS | CMD_PHASE: 1368 case SBIC_CSR_MIS_1 | CMD_PHASE: 1369 case SBIC_CSR_MIS_2 | CMD_PHASE: 1370 { 1371 if ( sbicxfout(regs, clen, cbuf) ) 1372 still_busy = sbicabort(dev, "icmd sending cmd"); 1373 } 1374 break; 1375 1376 case SBIC_CSR_XFERRED | STATUS_PHASE: 1377 case SBIC_CSR_MIS | STATUS_PHASE: 1378 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1379 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1380 { 1381 /* 1382 * The sbic does the status/cmd-complete reading ok, 1383 * so do this with its hi-level commands. 1384 */ 1385 #ifdef DEBUG 1386 if ( sbic_debug ) 1387 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1388 #endif 1389 SET_SBIC_cmd_phase(regs, 0x46); 1390 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1391 } 1392 break; 1393 1394 default: 1395 { 1396 still_busy = sbicnextstate(dev, csr, asr); 1397 } 1398 break; 1399 } 1400 1401 /* 1402 * make sure the last command was taken, 1403 * ie. we're not hunting after an ignored command.. 1404 */ 1405 GET_SBIC_asr(regs, asr); 1406 1407 /* 1408 * tapes may take a loooong time.. 1409 */ 1410 while (asr & SBIC_ASR_BSY ) { 1411 1412 if ( asr & SBIC_ASR_DBR ) { 1413 int i; 1414 1415 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1416 #ifdef DDB 1417 Debugger(); 1418 #endif 1419 /* 1420 * SBIC is jammed 1421 * DUNNO which direction 1422 * Try old direction 1423 */ 1424 GET_SBIC_data(regs, i); 1425 GET_SBIC_asr(regs, asr); 1426 1427 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1428 SET_SBIC_data(regs, i); 1429 } 1430 1431 GET_SBIC_asr(regs, asr); 1432 } 1433 } 1434 1435 /* 1436 * wait for last command to complete 1437 */ 1438 if ( asr & SBIC_ASR_LCI ) { 1439 printf("sbicicmd: last command ignored\n"); 1440 } 1441 else 1442 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1443 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1444 1445 /* 1446 * do it again 1447 */ 1448 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1449 1450 /* 1451 * Sometimes we need to do an extra read of the CSR 1452 */ 1453 GET_SBIC_csr(regs, csr); 1454 1455 #ifdef DEBUG 1456 if ( data_pointer_debug > 1 ) 1457 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1458 acb->sc_kv.dc_count, 1459 dev->sc_stat[0]); 1460 #endif 1461 1462 dev->sc_flags &= ~SBICF_ICMD; 1463 1464 return(dev->sc_stat[0]); 1465 } 1466 1467 /* 1468 * Finish SCSI xfer command: After the completion interrupt from 1469 * a read/write operation, sequence through the final phases in 1470 * programmed i/o. This routine is a lot like sbicicmd except we 1471 * skip (and don't allow) the select, cmd out and data in/out phases. 1472 */ 1473 void 1474 sbicxfdone(dev) 1475 struct sbic_softc *dev; 1476 { 1477 sbic_regmap_p regs = dev->sc_sbicp; 1478 u_char phase, 1479 csr; 1480 int s; 1481 1482 QPRINTF(("{")); 1483 s = splbio(); 1484 1485 /* 1486 * have the sbic complete on its own 1487 */ 1488 SBIC_TC_PUT(regs, 0); 1489 SET_SBIC_cmd_phase(regs, 0x46); 1490 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1491 1492 do { 1493 1494 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1495 GET_SBIC_csr (regs, csr); 1496 QPRINTF(("%02x:", csr)); 1497 1498 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1499 (csr != SBIC_CSR_S_XFERRED)); 1500 1501 dev->sc_flags &= ~SBICF_SELECTED; 1502 1503 GET_SBIC_cmd_phase (regs, phase); 1504 QPRINTF(("}%02x", phase)); 1505 1506 if ( phase == 0x60 ) 1507 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1508 else 1509 sbicerror(dev, csr); 1510 1511 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1512 1513 splx(s); 1514 } 1515 1516 /* 1517 * No DMA chains 1518 */ 1519 int 1520 sbicgo(dev, xs) 1521 struct sbic_softc *dev; 1522 struct scsipi_xfer *xs; 1523 { 1524 struct sbic_acb *acb = dev->sc_nexus; 1525 sbic_regmap_p regs = dev->sc_sbicp; 1526 int i, 1527 dmaflags, 1528 count, 1529 usedma; 1530 u_char csr, 1531 asr, 1532 *addr; 1533 1534 dev->target = xs->xs_periph->periph_target; 1535 dev->lun = xs->xs_periph->periph_lun; 1536 1537 usedma = sbicdmaok(dev, xs); 1538 1539 #ifdef DEBUG 1540 if ( data_pointer_debug > 1 ) 1541 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1542 #endif 1543 1544 /* 1545 * select the SCSI bus (it's an error if bus isn't free) 1546 */ 1547 if ( (csr = sbicselectbus(dev)) == 0 ) 1548 return(0); /* Not done: needs to be rescheduled */ 1549 1550 dev->sc_stat[0] = 0xff; 1551 1552 /* 1553 * Calculate DMA chains now 1554 */ 1555 if ( acb->flags & ACB_DATAIN ) 1556 dmaflags = DMAGO_READ; 1557 else 1558 dmaflags = 0; 1559 1560 addr = acb->sc_kv.dc_addr; 1561 count = acb->sc_kv.dc_count; 1562 1563 if ( count && ((char *)kvtop((caddr_t)addr) != acb->sc_pa.dc_addr) ) { 1564 printf("sbic: DMA buffer mapping changed %p->%lx\n", 1565 acb->sc_pa.dc_addr, kvtop((caddr_t)addr)); 1566 #ifdef DDB 1567 Debugger(); 1568 #endif 1569 } 1570 1571 #ifdef DEBUG 1572 ++sbicdma_ops; /* count total DMA operations */ 1573 #endif 1574 1575 /* 1576 * Allocate the DMA chain 1577 * Mark end of segment... 1578 */ 1579 acb->sc_tcnt = dev->sc_tcnt = 0; 1580 acb->sc_pa.dc_count = 0; 1581 1582 sbic_load_ptrs(dev); 1583 1584 /* 1585 * Enable interrupts but don't do any DMA 1586 * enintr() also enables interrupts for the sbic 1587 */ 1588 dev->sc_enintr(dev); 1589 1590 if ( usedma ) { 1591 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1592 acb->sc_pa.dc_count, dmaflags); 1593 #ifdef DEBUG 1594 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1595 #endif 1596 } else 1597 dev->sc_dmacmd = 0; /* Don't use DMA */ 1598 1599 acb->sc_dmacmd = dev->sc_dmacmd; 1600 1601 #ifdef DEBUG 1602 if ( data_pointer_debug > 1 ) { 1603 printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, 1604 dev->sc_cur->dc_addr, 1605 dev->sc_tcnt, 1606 dev->sc_dmacmd); 1607 } 1608 #endif 1609 1610 /* 1611 * Lets cycle a while then let the interrupt handler take over. 1612 */ 1613 GET_SBIC_asr(regs, asr); 1614 1615 do { 1616 1617 QPRINTF(("go ")); 1618 1619 /* 1620 * Handle the new phase 1621 */ 1622 i = sbicnextstate(dev, csr, asr); 1623 #if 0 1624 WAIT_CIP(regs); 1625 #endif 1626 if ( i == SBIC_STATE_RUNNING ) { 1627 GET_SBIC_asr(regs, asr); 1628 1629 if ( asr & SBIC_ASR_LCI ) 1630 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1631 1632 if ( asr & SBIC_ASR_INT ) 1633 GET_SBIC_csr(regs, csr); 1634 } 1635 1636 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1637 1638 if ( i == SBIC_STATE_DONE ) { 1639 if ( dev->sc_stat[0] == 0xff ) 1640 #if 0 1641 printf("sbicgo: done & stat = 0xff\n"); 1642 #else 1643 ; 1644 #endif 1645 else 1646 return 1; /* Did we really finish that fast? */ 1647 } 1648 1649 return 0; 1650 } 1651 1652 1653 int 1654 sbicintr(dev) 1655 struct sbic_softc *dev; 1656 { 1657 sbic_regmap_p regs = dev->sc_sbicp; 1658 u_char asr, 1659 csr; 1660 int i; 1661 1662 /* 1663 * pending interrupt? 1664 */ 1665 GET_SBIC_asr (regs, asr); 1666 if ( (asr & SBIC_ASR_INT) == 0 ) 1667 return(0); 1668 1669 GET_SBIC_csr(regs, csr); 1670 1671 do { 1672 1673 QPRINTF(("intr[0x%x]", csr)); 1674 1675 i = sbicnextstate(dev, csr, asr); 1676 #if 0 1677 WAIT_CIP(regs); 1678 #endif 1679 if ( i == SBIC_STATE_RUNNING ) { 1680 GET_SBIC_asr(regs, asr); 1681 1682 if ( asr & SBIC_ASR_LCI ) 1683 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1684 1685 if ( asr & SBIC_ASR_INT ) 1686 GET_SBIC_csr(regs, csr); 1687 } 1688 1689 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1690 1691 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1692 1693 return(1); 1694 } 1695 1696 /* 1697 * Run commands and wait for disconnect. 1698 * This is only ever called when a command is in progress, when we 1699 * want to busy wait for it to finish. 1700 */ 1701 int 1702 sbicpoll(dev) 1703 struct sbic_softc *dev; 1704 { 1705 sbic_regmap_p regs = dev->sc_sbicp; 1706 u_char asr, 1707 csr; 1708 int i; 1709 1710 /* 1711 * Wait for the next interrupt 1712 */ 1713 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1714 1715 do { 1716 GET_SBIC_asr (regs, asr); 1717 1718 if ( asr & SBIC_ASR_INT ) 1719 GET_SBIC_csr(regs, csr); 1720 1721 QPRINTF(("poll[0x%x]", csr)); 1722 1723 /* 1724 * Handle it 1725 */ 1726 i = sbicnextstate(dev, csr, asr); 1727 1728 WAIT_CIP(regs); 1729 GET_SBIC_asr(regs, asr); 1730 1731 /* 1732 * tapes may take a loooong time.. 1733 */ 1734 while ( asr & SBIC_ASR_BSY ) { 1735 u_char z = 0; 1736 1737 if ( asr & SBIC_ASR_DBR ) { 1738 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1739 #ifdef DDB 1740 Debugger(); 1741 #endif 1742 /* 1743 * SBIC is jammed 1744 * DUNNO which direction 1745 * Try old direction 1746 */ 1747 GET_SBIC_data(regs, z); 1748 GET_SBIC_asr(regs, asr); 1749 1750 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1751 SET_SBIC_data(regs, z); 1752 } 1753 1754 GET_SBIC_asr(regs, asr); 1755 } 1756 1757 if ( asr & SBIC_ASR_LCI ) 1758 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1759 else 1760 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1761 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1762 1763 } while ( i == SBIC_STATE_RUNNING ); 1764 1765 return(1); 1766 } 1767 1768 /* 1769 * Handle a single msgin 1770 */ 1771 int 1772 sbicmsgin(dev) 1773 struct sbic_softc *dev; 1774 { 1775 sbic_regmap_p regs = dev->sc_sbicp; 1776 int recvlen = 1; 1777 u_char asr, 1778 csr, 1779 *tmpaddr, 1780 *msgaddr; 1781 1782 tmpaddr = msgaddr = dev->sc_msg; 1783 1784 tmpaddr[0] = 0xff; 1785 tmpaddr[1] = 0xff; 1786 1787 GET_SBIC_asr(regs, asr); 1788 1789 #ifdef DEBUG 1790 if ( reselect_debug > 1 ) 1791 printf("sbicmsgin asr=%02x\n", asr); 1792 #endif 1793 1794 GET_SBIC_selid (regs, csr); 1795 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1796 1797 SBIC_TC_PUT(regs, 0); 1798 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1799 1800 do { 1801 while( recvlen-- ) { 1802 1803 /* 1804 * Fetch the next byte of the message 1805 */ 1806 RECV_BYTE(regs, *tmpaddr); 1807 1808 /* 1809 * get the command completion interrupt, or we 1810 * can't send a new command (LCI) 1811 */ 1812 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1813 GET_SBIC_csr(regs, csr); 1814 1815 #ifdef DEBUG 1816 if ( reselect_debug > 1 ) 1817 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1818 #endif 1819 1820 tmpaddr++; 1821 1822 if ( recvlen ) { 1823 /* 1824 * Clear ACK, and wait for the interrupt for the next byte 1825 */ 1826 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1827 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1828 GET_SBIC_csr(regs, csr); 1829 } 1830 } 1831 1832 if ( msgaddr[0] == 0xff ) { 1833 printf("sbicmsgin: sbic swallowed our message\n"); 1834 break; 1835 } 1836 1837 #ifdef DEBUG 1838 if ( sync_debug ) { 1839 GET_SBIC_asr(regs, asr); 1840 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1841 } 1842 #endif 1843 /* 1844 * test whether this is a reply to our sync 1845 * request 1846 */ 1847 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1848 1849 /* 1850 * Got IFFY msg -- ack it 1851 */ 1852 QPRINTF(("IFFY")); 1853 1854 } else 1855 if ( msgaddr[0] == MSG_REJECT && 1856 dev->sc_sync[dev->target].state == SYNC_SENT) { 1857 1858 /* 1859 * Target probably rejected our Sync negotiation. 1860 */ 1861 QPRINTF(("REJECT of SYN")); 1862 1863 #ifdef DEBUG 1864 if ( sync_debug ) 1865 printf("target %d rejected sync, going async\n", dev->target); 1866 #endif 1867 1868 dev->sc_sync[dev->target].period = sbic_min_period; 1869 dev->sc_sync[dev->target].offset = 0; 1870 dev->sc_sync[dev->target].state = SYNC_DONE; 1871 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1872 dev->sc_sync[dev->target].period)); 1873 1874 } else 1875 if ( msgaddr[0] == MSG_REJECT ) { 1876 1877 /* 1878 * we'll never REJECt a REJECT message.. 1879 */ 1880 QPRINTF(("REJECT")); 1881 1882 } else 1883 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1884 1885 /* 1886 * don't reject this either. 1887 */ 1888 QPRINTF(("MSG_SAVE_DATA_PTR")); 1889 1890 } else 1891 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1892 1893 /* 1894 * don't reject this either. 1895 */ 1896 QPRINTF(("MSG_RESTORE_PTR")); 1897 1898 } else 1899 if ( msgaddr[0] == MSG_DISCONNECT ) { 1900 1901 /* 1902 * Target is disconnecting... 1903 */ 1904 QPRINTF(("DISCONNECT")); 1905 1906 #ifdef DEBUG 1907 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1908 printf("sbicmsgin: got disconnect msg %s\n", 1909 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1910 #endif 1911 1912 if ( dev->sc_flags & SBICF_ICMD ) { 1913 /* 1914 * We're in immediate mode. Prevent disconnects. 1915 * prepare to reject the message, NACK 1916 */ 1917 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1918 WAIT_CIP(regs); 1919 } 1920 1921 } else 1922 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1923 1924 /* 1925 * !! KLUDGE ALERT !! quite a few drives don't seem to 1926 * really like the current way of sending the 1927 * sync-handshake together with the ident-message, and 1928 * they react by sending command-complete and 1929 * disconnecting right after returning the valid sync 1930 * handshake. So, all I can do is reselect the drive, 1931 * and hope it won't disconnect again. I don't think 1932 * this is valid behavior, but I can't help fixing a 1933 * problem that apparently exists. 1934 * 1935 * Note: we should not get here on `normal' command 1936 * completion, as that condition is handled by the 1937 * high-level sel&xfer resume command used to walk 1938 * thru status/cc-phase. 1939 */ 1940 QPRINTF(("CMD_COMPLETE")); 1941 1942 #ifdef DEBUG 1943 if ( sync_debug ) 1944 printf ("GOT MSG %d! target %d acting weird.." 1945 " waiting for disconnect...\n", msgaddr[0], dev->target); 1946 #endif 1947 1948 /* 1949 * Check to see if sbic is handling this 1950 */ 1951 GET_SBIC_asr(regs, asr); 1952 1953 /* 1954 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 1955 */ 1956 if ( asr & SBIC_ASR_BSY ) 1957 return SBIC_STATE_RUNNING; 1958 1959 /* 1960 * Let's try this: Assume it works and set status to 00 1961 */ 1962 dev->sc_stat[0] = 0; 1963 1964 } else 1965 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 1966 1967 /* 1968 * Target is sending us an extended message. We'll assume it's 1969 * the response to our Sync. negotiation. 1970 */ 1971 QPRINTF(("ExtMSG\n")); 1972 1973 /* 1974 * Read in whole extended message. First, negate ACK to accept 1975 * the MSG_EXT_MESSAGE byte... 1976 */ 1977 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1978 1979 /* 1980 * Wait for the interrupt for the next byte (length) 1981 */ 1982 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1983 GET_SBIC_csr(regs, csr); 1984 1985 #ifdef DEBUG 1986 QPRINTF(("CLR ACK csr %02x\n", csr)); 1987 #endif 1988 1989 /* 1990 * Read the length byte 1991 */ 1992 RECV_BYTE(regs, *tmpaddr); 1993 1994 /* 1995 * Wait for command completion IRQ 1996 */ 1997 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1998 GET_SBIC_csr(regs, csr); 1999 2000 /* 2001 * Reload the loop counter 2002 */ 2003 recvlen = *tmpaddr++; 2004 2005 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2006 2007 } else 2008 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2009 msgaddr[2] == MSG_SYNC_REQ ) { 2010 2011 /* 2012 * We've received the complete Extended Message Sync. Request... 2013 */ 2014 QPRINTF(("SYN")); 2015 2016 /* 2017 * Compute the required Transfer Period for the WD chip... 2018 */ 2019 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2020 dev->sc_sync[dev->target].offset = msgaddr[4]; 2021 dev->sc_sync[dev->target].state = SYNC_DONE; 2022 2023 /* 2024 * Put the WD chip in synchronous mode 2025 */ 2026 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2027 dev->sc_sync[dev->target].period)); 2028 #ifdef DEBUG 2029 if ( sync_debug ) 2030 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2031 SBIC_SYN(dev->sc_sync[dev->target].offset, 2032 dev->sc_sync[dev->target].period)); 2033 #endif 2034 2035 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2036 dev->sc_dev.dv_xname, dev->target, 2037 msgaddr[3] * 4, msgaddr[4]); 2038 2039 } else { 2040 2041 /* 2042 * We don't support whatever this message is... 2043 */ 2044 #ifdef DEBUG 2045 if ( sbic_debug || sync_debug ) 2046 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2047 #endif 2048 2049 /* 2050 * prepare to reject the message, NACK 2051 */ 2052 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2053 WAIT_CIP(regs); 2054 } 2055 2056 /* 2057 * Negate ACK to complete the transfer 2058 */ 2059 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2060 2061 /* 2062 * Wait for the interrupt for the next byte, or phase change. 2063 * Only read the CSR if we have more data to transfer. 2064 * XXXSCW: We should really verify that we're still in MSG IN phase 2065 * before blindly going back around this loop, but that would mean 2066 * we read the CSR... <sigh> 2067 */ 2068 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2069 if ( recvlen > 0 ) 2070 GET_SBIC_csr(regs, csr); 2071 2072 } while ( recvlen > 0 ); 2073 2074 /* 2075 * Should still have one CSR to read 2076 */ 2077 return SBIC_STATE_RUNNING; 2078 } 2079 2080 2081 /* 2082 * sbicnextstate() 2083 * return: 2084 * SBIC_STATE_DONE == done 2085 * SBIC_STATE_RUNNING == working 2086 * SBIC_STATE_DISCONNECT == disconnected 2087 * SBIC_STATE_ERROR == error 2088 */ 2089 int 2090 sbicnextstate(dev, csr, asr) 2091 struct sbic_softc *dev; 2092 u_char csr, 2093 asr; 2094 { 2095 sbic_regmap_p regs = dev->sc_sbicp; 2096 struct sbic_acb *acb = dev->sc_nexus; 2097 2098 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2099 2100 switch (csr) { 2101 2102 case SBIC_CSR_XFERRED | CMD_PHASE: 2103 case SBIC_CSR_MIS | CMD_PHASE: 2104 case SBIC_CSR_MIS_1 | CMD_PHASE: 2105 case SBIC_CSR_MIS_2 | CMD_PHASE: 2106 { 2107 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2108 goto abort; 2109 } 2110 break; 2111 2112 case SBIC_CSR_XFERRED | STATUS_PHASE: 2113 case SBIC_CSR_MIS | STATUS_PHASE: 2114 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2115 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2116 { 2117 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2118 2119 /* 2120 * this should be the normal i/o completion case. 2121 * get the status & cmd complete msg then let the 2122 * device driver look at what happened. 2123 */ 2124 sbicxfdone(dev); 2125 2126 #ifdef DEBUG 2127 dev->sc_dmatimo = 0; 2128 if ( data_pointer_debug > 1 ) 2129 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2130 dev->sc_cur->dc_addr, 2131 dev->sc_tcnt); 2132 #endif 2133 /* 2134 * Stop the DMA chip 2135 */ 2136 dev->sc_dmastop(dev); 2137 2138 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2139 2140 /* 2141 * Indicate to the upper layers that the command is done 2142 */ 2143 sbic_scsidone(acb, dev->sc_stat[0]); 2144 2145 return SBIC_STATE_DONE; 2146 } 2147 2148 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2149 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2150 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2151 case SBIC_CSR_MIS | DATA_IN_PHASE: 2152 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2153 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2154 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2155 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2156 { 2157 /* 2158 * Verify that we expected to transfer data... 2159 */ 2160 if ( acb->sc_kv.dc_count <= 0 ) { 2161 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2162 acb->sc_kv.dc_count, asr, csr); 2163 goto abort; 2164 } 2165 2166 /* 2167 * Should we transfer using PIO or DMA ? 2168 */ 2169 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2170 acb->sc_dmacmd == 0 ) { 2171 2172 /* 2173 * Do PIO transfer 2174 */ 2175 int i; 2176 2177 #ifdef DEBUG 2178 if ( data_pointer_debug > 1 ) 2179 printf("next PIO: %d(%p:%x)\n", dev->target, 2180 acb->sc_kv.dc_addr, 2181 acb->sc_kv.dc_count); 2182 #endif 2183 2184 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2185 /* 2186 * data in 2187 */ 2188 i = sbicxfin(regs, acb->sc_kv.dc_count, 2189 acb->sc_kv.dc_addr); 2190 else 2191 /* 2192 * data out 2193 */ 2194 i = sbicxfout(regs, acb->sc_kv.dc_count, 2195 acb->sc_kv.dc_addr); 2196 2197 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2198 acb->sc_kv.dc_count = i; 2199 2200 /* 2201 * Update current count... 2202 */ 2203 acb->sc_tcnt = dev->sc_tcnt = i; 2204 2205 dev->sc_flags &= ~SBICF_INDMA; 2206 2207 } else { 2208 2209 /* 2210 * Do DMA transfer 2211 * set next dma addr and dec count 2212 */ 2213 sbic_save_ptrs(dev); 2214 sbic_load_ptrs(dev); 2215 2216 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2217 SBIC_MACHINE_DMA_MODE); 2218 2219 #ifdef DEBUG 2220 dev->sc_dmatimo = 1; 2221 if ( data_pointer_debug > 1 ) 2222 printf("next DMA: %d(%p:%lx)\n", dev->target, 2223 dev->sc_cur->dc_addr, 2224 dev->sc_tcnt); 2225 #endif 2226 /* 2227 * Start the DMA chip going 2228 */ 2229 dev->sc_tcnt = dev->sc_dmanext(dev); 2230 2231 /* 2232 * Tell the WD chip how much to transfer this time around 2233 */ 2234 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2235 2236 /* 2237 * Start the transfer 2238 */ 2239 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2240 2241 /* 2242 * Indicate that we're in DMA mode 2243 */ 2244 dev->sc_flags |= SBICF_INDMA; 2245 } 2246 } 2247 break; 2248 2249 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2250 case SBIC_CSR_MIS | MESG_IN_PHASE: 2251 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2252 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2253 { 2254 sbic_save_ptrs(dev); 2255 2256 /* 2257 * Handle a single message in... 2258 */ 2259 return sbicmsgin(dev); 2260 } 2261 2262 case SBIC_CSR_MSGIN_W_ACK: 2263 { 2264 /* 2265 * We should never see this since it's handled in 'sbicmsgin()' 2266 * but just for the sake of paranoia... 2267 */ 2268 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2269 printf("Acking unknown msgin CSR:%02x",csr); 2270 } 2271 break; 2272 2273 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2274 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2275 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2276 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2277 { 2278 /* 2279 * We only ever handle a message out phase here for sending a 2280 * REJECT message. 2281 */ 2282 sbic_save_ptrs(dev); 2283 2284 #ifdef DEBUG 2285 if (sync_debug) 2286 printf ("sending REJECT msg to last msg.\n"); 2287 #endif 2288 2289 SEND_BYTE(regs, MSG_REJECT); 2290 WAIT_CIP(regs); 2291 } 2292 break; 2293 2294 case SBIC_CSR_DISC: 2295 case SBIC_CSR_DISC_1: 2296 { 2297 /* 2298 * Try to schedule another target 2299 */ 2300 sbic_save_ptrs(dev); 2301 2302 dev->sc_flags &= ~SBICF_SELECTED; 2303 2304 #ifdef DEBUG 2305 if ( reselect_debug > 1 ) 2306 printf("sbicnext target %d disconnected\n", dev->target); 2307 #endif 2308 2309 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2310 2311 ++dev->sc_tinfo[dev->target].dconns; 2312 2313 dev->sc_nexus = NULL; 2314 dev->sc_xs = NULL; 2315 2316 if ( acb->xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2317 !sbic_parallel_operations ) 2318 return SBIC_STATE_DISCONNECT; 2319 2320 QPRINTF(("sbicnext: calling sbic_sched\n")); 2321 2322 sbic_sched(dev); 2323 2324 QPRINTF(("sbicnext: sbic_sched returned\n")); 2325 2326 return SBIC_STATE_DISCONNECT; 2327 } 2328 2329 case SBIC_CSR_RSLT_NI: 2330 case SBIC_CSR_RSLT_IFY: 2331 { 2332 /* 2333 * A reselection. 2334 * Note that since we don't enable Advanced Features (assuming 2335 * the WD chip is at least the 'A' revision), we're only ever 2336 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2337 * hell of it, we'll handle it anyway, for all the extra code 2338 * it needs... 2339 */ 2340 u_char newtarget, 2341 newlun; 2342 2343 GET_SBIC_rselid(regs, newtarget); 2344 2345 /* 2346 * check SBIC_RID_SIV? 2347 */ 2348 newtarget &= SBIC_RID_MASK; 2349 2350 if ( csr == SBIC_CSR_RSLT_IFY ) { 2351 2352 /* 2353 * Read Identify msg to avoid lockup 2354 */ 2355 GET_SBIC_data(regs, newlun); 2356 WAIT_CIP(regs); 2357 newlun &= SBIC_TLUN_MASK; 2358 2359 } else { 2360 2361 /* 2362 * Need to read Identify message the hard way, assuming 2363 * the target even sends us one... 2364 */ 2365 for (newlun = 255; newlun; --newlun) { 2366 GET_SBIC_asr(regs, asr); 2367 if (asr & SBIC_ASR_INT) 2368 break; 2369 delay(10); 2370 } 2371 2372 /* 2373 * If we didn't get an interrupt, somethink's up 2374 */ 2375 if ( (asr & SBIC_ASR_INT) == 0 ) { 2376 printf("%s: Reselect without identify? asr %x\n", 2377 dev->sc_dev.dv_xname, asr); 2378 newlun = 0; /* XXXX */ 2379 } else { 2380 /* 2381 * We got an interrupt, verify that it's a change to 2382 * message in phase, and if so read the message. 2383 */ 2384 GET_SBIC_csr(regs,csr); 2385 2386 if ( csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2387 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2388 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE) ) { 2389 /* 2390 * Yup, gone to message in. Fetch the target LUN 2391 */ 2392 sbicmsgin(dev); 2393 newlun = dev->sc_msg[0] & 0x07; 2394 2395 } else { 2396 /* 2397 * Whoops! Target didn't go to message in phase!! 2398 */ 2399 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2400 newlun = 0; /* XXXSCW */ 2401 } 2402 } 2403 } 2404 2405 /* 2406 * Ok, we have the identity of the reselecting target. 2407 */ 2408 #ifdef DEBUG 2409 if ( reselect_debug > 1 || 2410 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2411 printf("sbicnext: reselect %s from targ %d lun %d\n", 2412 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2413 } 2414 #endif 2415 2416 if ( dev->sc_nexus ) { 2417 /* 2418 * Whoops! We've been reselected with an command in progress! 2419 * The best we can do is to put the current command back on the 2420 * ready list and hope for the best. 2421 */ 2422 #ifdef DEBUG 2423 if ( reselect_debug > 1 ) { 2424 printf("%s: reselect %s with active command\n", 2425 dev->sc_dev.dv_xname, 2426 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2427 } 2428 #endif 2429 2430 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2431 2432 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2433 2434 dev->sc_nexus = NULL; 2435 dev->sc_xs = NULL; 2436 } 2437 2438 /* 2439 * Reload sync values for this target 2440 */ 2441 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2442 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2443 dev->sc_sync[newtarget].period)); 2444 else 2445 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2446 2447 /* 2448 * Loop through the nexus list until we find the saved entry 2449 * for the reselecting target... 2450 */ 2451 for (acb = dev->nexus_list.tqh_first; acb; 2452 acb = acb->chain.tqe_next) { 2453 2454 if ( acb->xs->xs_periph->periph_target == newtarget && 2455 acb->xs->xs_periph->periph_lun == newlun) { 2456 /* 2457 * We've found the saved entry. Dequeue it, and 2458 * make it current again. 2459 */ 2460 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2461 2462 dev->sc_nexus = acb; 2463 dev->sc_xs = acb->xs; 2464 dev->sc_flags |= SBICF_SELECTED; 2465 dev->target = newtarget; 2466 dev->lun = newlun; 2467 break; 2468 } 2469 } 2470 2471 if ( acb == NULL ) { 2472 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2473 dev->sc_dev.dv_xname, 2474 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2475 &dev->nexus_list.tqh_first); 2476 panic("bad reselect in sbic"); 2477 } 2478 2479 if ( csr == SBIC_CSR_RSLT_IFY ) 2480 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2481 } 2482 break; 2483 2484 default: 2485 abort: 2486 { 2487 /* 2488 * Something unexpected happened -- deal with it. 2489 */ 2490 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2491 2492 #ifdef DDB 2493 Debugger(); 2494 #endif 2495 2496 #ifdef DEBUG 2497 dev->sc_dmatimo = 0; 2498 if ( data_pointer_debug > 1 ) 2499 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2500 dev->sc_cur->dc_addr, 2501 dev->sc_tcnt); 2502 #endif 2503 2504 dev->sc_dmastop(dev); 2505 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2506 if ( dev->sc_xs ) sbicerror(dev, csr); 2507 sbicabort(dev, "next"); 2508 2509 if ( dev->sc_flags & SBICF_INDMA ) { 2510 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2511 2512 #ifdef DEBUG 2513 dev->sc_dmatimo = 0; 2514 if ( data_pointer_debug > 1 ) 2515 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2516 dev->sc_cur->dc_addr, 2517 dev->sc_tcnt); 2518 #endif 2519 sbic_scsidone(acb, -1); 2520 } 2521 2522 return SBIC_STATE_ERROR; 2523 } 2524 } 2525 2526 return(SBIC_STATE_RUNNING); 2527 } 2528 2529 2530 /* 2531 * Check if DMA can not be used with specified buffer 2532 */ 2533 int 2534 sbiccheckdmap(bp, len, mask) 2535 void *bp; 2536 u_long len, 2537 mask; 2538 { 2539 u_char *buffer; 2540 u_long phy_buf; 2541 u_long phy_len; 2542 2543 buffer = bp; 2544 2545 if ( len == 0 ) 2546 return(1); 2547 2548 while ( len ) { 2549 2550 phy_buf = kvtop((caddr_t)buffer); 2551 phy_len = NBPG - ((int) buffer & PGOFSET); 2552 2553 if ( len < phy_len ) 2554 phy_len = len; 2555 2556 if ( phy_buf & mask ) 2557 return(1); 2558 2559 buffer += phy_len; 2560 len -= phy_len; 2561 } 2562 2563 return(0); 2564 } 2565 2566 int 2567 sbictoscsiperiod(dev, a) 2568 struct sbic_softc *dev; 2569 int a; 2570 { 2571 unsigned int fs; 2572 2573 /* 2574 * cycle = DIV / (2 * CLK) 2575 * DIV = FS + 2 2576 * best we can do is 200ns at 20Mhz, 2 cycles 2577 */ 2578 2579 GET_SBIC_myid(dev->sc_sbicp, fs); 2580 2581 fs = (fs >> 6) + 2; /* DIV */ 2582 2583 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2584 2585 if ( a < 2 ) 2586 a = 8; /* map to Cycles */ 2587 2588 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2589 } 2590 2591 int 2592 sbicfromscsiperiod(dev, p) 2593 struct sbic_softc *dev; 2594 int p; 2595 { 2596 unsigned fs, 2597 ret; 2598 2599 /* 2600 * Just the inverse of the above 2601 */ 2602 GET_SBIC_myid(dev->sc_sbicp, fs); 2603 2604 fs = (fs >> 6) + 2; /* DIV */ 2605 2606 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2607 2608 ret = p << 2; /* in ns units */ 2609 ret = ret / fs; /* in Cycles */ 2610 2611 if ( ret < sbic_min_period ) 2612 return(sbic_min_period); 2613 2614 /* 2615 * verify rounding 2616 */ 2617 if ( sbictoscsiperiod(dev, ret) < p ) 2618 ret++; 2619 2620 return( (ret >= 8) ? 0 : ret ); 2621 } 2622 2623 #ifdef DEBUG 2624 void 2625 sbictimeout(dev) 2626 struct sbic_softc *dev; 2627 { 2628 int s, 2629 asr; 2630 2631 s = splbio(); 2632 2633 if ( dev->sc_dmatimo ) { 2634 2635 if ( dev->sc_dmatimo > 1 ) { 2636 2637 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2638 dev->sc_dmatimo - 1); 2639 2640 GET_SBIC_asr(dev->sc_sbicp, asr); 2641 2642 if ( asr & SBIC_ASR_INT ) { 2643 /* 2644 * We need to service a missed IRQ 2645 */ 2646 sbicintr(dev); 2647 } else { 2648 (void) sbicabort(dev, "timeout"); 2649 splx(s); 2650 return; 2651 } 2652 } 2653 2654 dev->sc_dmatimo++; 2655 } 2656 2657 splx(s); 2658 2659 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 2660 } 2661 #endif 2662
Indexes created Sat Sep 27 22:09:54 GMT 2025