sbic.c revision 1.19
1 /* $NetBSD: sbic.c,v 1.19 2002/10/20 02:37:29 chs Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 #include "opt_ddb.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/kernel.h> /* For hz */ 61 #include <sys/disklabel.h> 62 #include <sys/dkstat.h> 63 #include <sys/buf.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <uvm/uvm_extern.h> 70 71 #include <mvme68k/mvme68k/isr.h> 72 #include <mvme68k/dev/dmavar.h> 73 #include <mvme68k/dev/sbicreg.h> 74 #include <mvme68k/dev/sbicvar.h> 75 76 77 /* 78 * Since I can't find this in any other header files 79 */ 80 #define SCSI_PHASE(reg) (reg&0x07) 81 82 /* 83 * SCSI delays 84 * In u-seconds, primarily for state changes on the SPC. 85 */ 86 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 87 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 88 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 89 90 /* 91 * Convenience macro for waiting for a particular sbic event 92 */ 93 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 94 95 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 96 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 97 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 98 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 99 int sbiccheckdmap __P((void *, u_long, u_long)); 100 u_char sbicselectbus __P((struct sbic_softc *)); 101 int sbicxfout __P((sbic_regmap_p, int, void *)); 102 int sbicxfin __P((sbic_regmap_p, int, void *)); 103 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 104 int sbictoscsiperiod __P((struct sbic_softc *, int)); 105 int sbicpoll __P((struct sbic_softc *)); 106 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 107 int sbicmsgin __P((struct sbic_softc *)); 108 int sbicabort __P((struct sbic_softc *, char *)); 109 void sbicxfdone __P((struct sbic_softc *)); 110 void sbicerror __P((struct sbic_softc *,u_char)); 111 void sbicreset __P((struct sbic_softc *)); 112 void sbic_scsidone __P((struct sbic_acb *, int)); 113 void sbic_sched __P((struct sbic_softc *)); 114 void sbic_save_ptrs __P((struct sbic_softc *)); 115 void sbic_load_ptrs __P((struct sbic_softc *)); 116 117 /* 118 * Synch xfer parameters, and timing conversions 119 */ 120 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 121 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 122 int sbic_cmd_wait = SBIC_CMD_WAIT; 123 int sbic_data_wait = SBIC_DATA_WAIT; 124 int sbic_init_wait = SBIC_INIT_WAIT; 125 126 /* 127 * was broken before.. now if you want this you get it for all drives 128 * on sbic controllers. 129 */ 130 u_char sbic_inhibit_sync[8]; 131 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 132 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 133 int sbic_parallel_operations = 1; /* Allow command queues */ 134 135 /* 136 * Some useful stuff for debugging purposes 137 */ 138 #ifdef DEBUG 139 int sbicdma_ops = 0; /* total DMA operations */ 140 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 141 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 142 int sbicdma_saves = 0; 143 144 #define QPRINTF(a) if (sbic_debug > 1) printf a 145 146 int sbic_debug = 0; /* Debug all chip related things */ 147 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 148 int reselect_debug = 0; /* Debug all reselection related things */ 149 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 150 151 void sbictimeout __P((struct sbic_softc *dev)); 152 153 #else 154 #define QPRINTF(a) /* */ 155 #endif 156 157 158 /* 159 * default minphys routine for sbic based controllers 160 */ 161 void 162 sbic_minphys(bp) 163 struct buf *bp; 164 { 165 /* 166 * No max transfer at this level. 167 */ 168 minphys(bp); 169 } 170 171 172 /* 173 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 174 */ 175 void 176 sbic_save_ptrs(dev) 177 struct sbic_softc *dev; 178 { 179 sbic_regmap_p regs; 180 struct sbic_acb* acb; 181 int count, 182 asr, 183 s; 184 185 /* 186 * Only need to save pointers if DMA was active... 187 */ 188 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 189 return; 190 191 regs = dev->sc_sbicp; 192 193 s = splbio(); 194 195 /* 196 * Wait until WD chip is idle 197 */ 198 do { 199 GET_SBIC_asr(regs, asr); 200 if( asr & SBIC_ASR_DBR ) { 201 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 202 splx(s); 203 return; 204 } 205 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 206 207 208 /* 209 * Save important state. 210 * must be done before dmastop 211 */ 212 acb = dev->sc_nexus; 213 acb->sc_dmacmd = dev->sc_dmacmd; 214 215 /* 216 * Fetch the residual count 217 */ 218 SBIC_TC_GET(regs, count); 219 220 /* 221 * Shut down DMA 222 */ 223 dev->sc_dmastop(dev); 224 225 /* 226 * No longer in DMA 227 */ 228 dev->sc_flags &= ~SBICF_INDMA; 229 230 /* 231 * Ensure the WD chip is back in polled I/O mode, with nothing to 232 * transfer. 233 */ 234 SBIC_TC_PUT(regs, 0); 235 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 236 237 /* 238 * Update current count... 239 */ 240 acb->sc_tcnt = count; 241 242 /* 243 * Work out how many bytes were actually transferred 244 */ 245 count = dev->sc_tcnt - count; 246 dev->sc_tcnt = acb->sc_tcnt; 247 248 /* 249 * Fixup partial xfers 250 */ 251 acb->sc_kv.dc_addr += count; 252 acb->sc_kv.dc_count -= count; 253 acb->sc_pa.dc_addr += count; 254 acb->sc_pa.dc_count -= count >> 1; 255 256 #ifdef DEBUG 257 if ( data_pointer_debug ) 258 printf("save at (%p,%x):%x\n", 259 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 260 sbicdma_saves++; 261 #endif 262 263 splx(s); 264 } 265 266 267 /* 268 * DOES NOT RESTART DMA!!! 269 */ 270 void 271 sbic_load_ptrs(dev) 272 struct sbic_softc *dev; 273 { 274 struct sbic_acb *acb = dev->sc_nexus; 275 int s; 276 277 if ( acb->sc_kv.dc_count == 0 ) { 278 /* 279 * No data to xfer 280 */ 281 return; 282 } 283 284 s = splbio(); 285 286 /* 287 * Reset the Scatter-Gather chain 288 */ 289 dev->sc_last = dev->sc_cur = &acb->sc_pa; 290 291 /* 292 * Restore the Transfer Count and DMA specific data 293 */ 294 dev->sc_tcnt = acb->sc_tcnt; 295 dev->sc_dmacmd = acb->sc_dmacmd; 296 297 #ifdef DEBUG 298 sbicdma_ops++; 299 #endif 300 301 /* 302 * Need to fixup new segment? 303 */ 304 if ( dev->sc_tcnt == 0 ) { 305 /* 306 * sc_tcnt == 0 implies end of segment 307 */ 308 char *vaddr, *paddr; 309 int count; 310 311 /* 312 * do kvm to pa mappings 313 */ 314 vaddr = acb->sc_kv.dc_addr; 315 paddr = acb->sc_pa.dc_addr = (char *) kvtop((caddr_t)vaddr); 316 317 for (count = (NBPG - ((int)vaddr & PGOFSET)); 318 count < acb->sc_kv.dc_count && 319 (char*)kvtop((caddr_t)(vaddr + count + 4)) == paddr + count + 4; 320 count += NBPG) 321 ; /* Do nothing */ 322 323 /* 324 * If it's all contiguous... 325 */ 326 if ( count > acb->sc_kv.dc_count ) { 327 count = acb->sc_kv.dc_count; 328 #ifdef DEBUG 329 sbicdma_hits++; 330 #endif 331 } 332 #ifdef DEBUG 333 else 334 sbicdma_misses++; 335 #endif 336 337 acb->sc_tcnt = count; 338 acb->sc_pa.dc_count = count >> 1; 339 340 #ifdef DEBUG 341 if ( data_pointer_debug ) 342 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", acb->sc_kv.dc_addr, 343 acb->sc_kv.dc_count, 344 acb->sc_pa.dc_addr, 345 acb->sc_tcnt); 346 #endif 347 348 } 349 350 splx(s); 351 } 352 353 /* 354 * used by specific sbic controller 355 * 356 * it appears that the higher level code does nothing with LUN's 357 * so I will too. I could plug it in, however so could they 358 * in scsi_scsipi_cmd(). 359 */ 360 void 361 sbic_scsi_request(chan, req, arg) 362 struct scsipi_channel *chan; 363 scsipi_adapter_req_t req; 364 void *arg; 365 { 366 struct scsipi_xfer *xs; 367 struct scsipi_periph *periph; 368 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 369 struct sbic_acb *acb; 370 int flags, s; 371 372 switch (req) { 373 case ADAPTER_REQ_RUN_XFER: 374 xs = arg; 375 periph = xs->xs_periph; 376 flags = xs->xs_control; 377 378 if ( flags & XS_CTL_DATA_UIO ) 379 panic("sbic: scsi data uio requested"); 380 381 if ( dev->sc_nexus && (flags & XS_CTL_POLL) ) 382 panic("sbic_scsicmd: busy"); 383 384 s = splbio(); 385 386 if ( (acb = dev->free_list.tqh_first) != NULL ) 387 TAILQ_REMOVE(&dev->free_list, acb, chain); 388 389 splx(s); 390 391 if ( acb == NULL ) { 392 #ifdef DEBUG 393 printf("sbic_scsicmd: unable to queue request for target %d\n", 394 periph->periph_target); 395 #ifdef DDB 396 Debugger(); 397 #endif 398 #endif 399 xs->error = XS_RESOURCE_SHORTAGE; 400 scsipi_done(xs); 401 return; 402 } 403 404 if ( flags & XS_CTL_DATA_IN ) 405 acb->flags = ACB_ACTIVE | ACB_DATAIN; 406 else 407 acb->flags = ACB_ACTIVE; 408 409 acb->xs = xs; 410 acb->clen = xs->cmdlen; 411 acb->sc_kv.dc_addr = xs->data; 412 acb->sc_kv.dc_count = xs->datalen; 413 acb->pa_addr = xs->data ? (char *)kvtop((caddr_t)xs->data) : 0; 414 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 415 416 if ( flags & XS_CTL_POLL ) { 417 /* 418 * This has major side effects -- it locks up the machine 419 */ 420 int stat; 421 422 s = splbio(); 423 424 dev->sc_flags |= SBICF_ICMD; 425 426 do { 427 /* 428 * If we already had a nexus, while away the time until idle... 429 * This is likely only to happen if a reselection occurs between 430 * here and our earlier check for ICMD && sc_nexus (which would 431 * have resulted in a panic() had it been true). 432 */ 433 while ( dev->sc_nexus ) 434 sbicpoll(dev); 435 436 /* 437 * Fix up the new nexus 438 */ 439 dev->sc_nexus = acb; 440 dev->sc_xs = xs; 441 dev->target = periph->periph_target; 442 dev->lun = periph->periph_lun; 443 444 stat = sbicicmd(dev, &acb->cmd, acb->clen, 445 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 446 447 } while ( dev->sc_nexus != acb ); 448 449 sbic_scsidone(acb, stat); 450 451 splx(s); 452 453 return; 454 } 455 456 s = splbio(); 457 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 458 459 /* 460 * If nothing is active, try to start it now. 461 */ 462 if ( dev->sc_nexus == NULL ) 463 sbic_sched(dev); 464 465 splx(s); 466 467 return; 468 469 case ADAPTER_REQ_GROW_RESOURCES: 470 /* XXX Not supported. */ 471 return; 472 473 case ADAPTER_REQ_SET_XFER_MODE: 474 /* XXX Not supported. */ 475 return; 476 } 477 478 } 479 480 /* 481 * attempt to start the next available command 482 */ 483 void 484 sbic_sched(dev) 485 struct sbic_softc *dev; 486 { 487 struct scsipi_xfer *xs; 488 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 489 struct sbic_acb *acb; 490 int flags, 491 stat; 492 493 /* 494 * XXXSCW 495 * I'll keep this test here, even though I can't see any obvious way 496 * in which sbic_sched() could be called with sc_nexus non NULL 497 */ 498 if ( dev->sc_nexus ) 499 return; /* a command is current active */ 500 501 /* 502 * Loop through the ready list looking for work to do... 503 */ 504 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 505 int i, j; 506 507 periph = acb->xs->xs_periph; 508 i = periph->periph_target; 509 j = 1 << periph->periph_lun; 510 511 /* 512 * We've found a potential command, but is the target/lun busy? 513 */ 514 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 515 /* 516 * Nope, it's not busy, so we can use it. 517 */ 518 dev->sc_tinfo[i].lubusy |= j; 519 TAILQ_REMOVE(&dev->ready_list, acb, chain); 520 dev->sc_nexus = acb; 521 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 522 break; 523 } 524 } 525 526 if ( acb == NULL ) { 527 QPRINTF(("sbicsched: no work\n")); 528 return; /* did not find an available command */ 529 } 530 531 #ifdef DEBUG 532 if ( data_pointer_debug > 1 ) 533 printf("sbic_sched(%d,%d)\n", periph->periph_target, 534 periph->periph_lun); 535 #endif 536 537 dev->sc_xs = xs = acb->xs; 538 flags = xs->xs_control; 539 540 if ( flags & XS_CTL_RESET ) 541 sbicreset(dev); 542 543 dev->sc_stat[0] = -1; 544 dev->target = periph->periph_target; 545 dev->lun = periph->periph_lun; 546 547 if ( flags & XS_CTL_POLL || (!sbic_parallel_operations && 548 (sbicdmaok(dev, xs) == 0)) ) 549 stat = sbicicmd(dev, &acb->cmd, acb->clen, 550 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 551 else 552 if ( sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT ) 553 return; 554 else 555 stat = dev->sc_stat[0]; 556 557 sbic_scsidone(acb, stat); 558 } 559 560 void 561 sbic_scsidone(acb, stat) 562 struct sbic_acb *acb; 563 int stat; 564 { 565 struct scsipi_xfer *xs = acb->xs; 566 struct scsipi_periph *periph = xs->xs_periph; 567 struct sbic_softc *dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 568 int dosched = 0; 569 570 #ifdef DIAGNOSTIC 571 if ( acb == NULL || xs == NULL ) { 572 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); 573 #ifdef DDB 574 Debugger(); 575 #endif 576 return; 577 } 578 #endif 579 580 581 #ifdef DEBUG 582 if ( data_pointer_debug > 1 ) 583 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", periph->periph_target, 584 periph->periph_lun, 585 dev->target, dev->lun, stat); 586 587 if ( xs->xs_periph->periph_target == dev->sc_channel.chan_id) 588 panic("target == hostid"); 589 #endif 590 591 xs->status = stat; 592 xs->resid = 0; /* XXXX */ 593 if ( xs->error == XS_NOERROR) { 594 if ( stat == SCSI_CHECK || stat == SCSI_BUSY) 595 xs->error = XS_BUSY; 596 } 597 598 599 /* 600 * Remove the ACB from whatever queue it's on. We have to do a bit of 601 * a hack to figure out which queue it's on. Note that it is *not* 602 * necessary to cdr down the ready queue, but we must cdr down the 603 * nexus queue and see if it's there, so we can mark the unit as no 604 * longer busy. This code is sickening, but it works. 605 */ 606 if ( acb == dev->sc_nexus ) { 607 608 dev->sc_nexus = NULL; 609 dev->sc_xs = NULL; 610 611 dev->sc_tinfo[periph->periph_target].lubusy &= 612 ~(1 << periph->periph_lun); 613 614 if ( dev->ready_list.tqh_first ) 615 dosched = 1; /* start next command */ 616 617 } else 618 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 619 620 TAILQ_REMOVE(&dev->ready_list, acb, chain); 621 622 } else { 623 624 struct sbic_acb *a; 625 626 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 627 if ( a == acb ) { 628 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 629 dev->sc_tinfo[periph->periph_target].lubusy &= 630 ~(1 << periph->periph_lun); 631 break; 632 } 633 } 634 635 if ( a ) 636 ; 637 else if ( acb->chain.tqe_next ) { 638 TAILQ_REMOVE(&dev->ready_list, acb, chain); 639 } else { 640 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 641 #ifdef DDB 642 Debugger(); 643 #endif 644 } 645 } 646 647 /* 648 * Put it on the free list. 649 */ 650 acb->flags = ACB_FREE; 651 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 652 653 dev->sc_tinfo[periph->periph_target].cmds++; 654 655 scsipi_done(xs); 656 657 if ( dosched ) 658 sbic_sched(dev); 659 } 660 661 int 662 sbicdmaok(dev, xs) 663 struct sbic_softc *dev; 664 struct scsipi_xfer *xs; 665 { 666 if ( sbic_no_dma || xs->datalen == 0 || 667 xs->datalen & 0x03 || (int)xs->data & 0x03) 668 return(0); 669 670 /* 671 * controller supports dma to any addresses? 672 */ 673 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 674 return(1); 675 676 /* 677 * this address is ok for dma? 678 */ 679 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 680 return(1); 681 682 return(0); 683 } 684 685 int 686 sbicwait(regs, until, timeo, line) 687 sbic_regmap_p regs; 688 u_char until; 689 int timeo; 690 int line; 691 { 692 u_char val; 693 694 if ( timeo == 0 ) 695 timeo = 1000000; /* some large value.. */ 696 697 GET_SBIC_asr(regs, val); 698 699 while ( (val & until) == 0 ) { 700 701 if ( timeo-- == 0 ) { 702 int csr; 703 GET_SBIC_csr(regs, csr); 704 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 705 #if defined(DDB) && defined(DEBUG) 706 Debugger(); 707 #endif 708 return(val); /* Maybe I should abort */ 709 break; 710 } 711 712 DELAY(1); 713 GET_SBIC_asr(regs, val); 714 } 715 716 return(val); 717 } 718 719 int 720 sbicabort(dev, where) 721 struct sbic_softc *dev; 722 char *where; 723 { 724 sbic_regmap_p regs = dev->sc_sbicp; 725 u_char csr, 726 asr; 727 728 GET_SBIC_asr(regs, asr); 729 GET_SBIC_csr(regs, csr); 730 731 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 732 dev->sc_dev.dv_xname, where, csr, asr); 733 734 /* 735 * Clean up chip itself 736 */ 737 if ( dev->sc_flags & SBICF_SELECTED ) { 738 739 while ( asr & SBIC_ASR_DBR ) { 740 /* 741 * sbic is jammed w/data. need to clear it 742 * But we don't know what direction it needs to go 743 */ 744 GET_SBIC_data(regs, asr); 745 printf("%s: abort %s: clearing data buffer 0x%02x\n", 746 dev->sc_dev.dv_xname, where, asr); 747 GET_SBIC_asr(regs, asr); 748 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 749 SET_SBIC_data(regs, asr); 750 GET_SBIC_asr(regs, asr); 751 } 752 753 WAIT_CIP(regs); 754 755 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 756 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 757 WAIT_CIP(regs); 758 759 GET_SBIC_asr(regs, asr); 760 761 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 762 /* 763 * ok, get more drastic.. 764 */ 765 printf("%s: sbicabort - asr %x, trying to reset\n", 766 dev->sc_dev.dv_xname, asr); 767 sbicreset(dev); 768 dev->sc_flags &= ~SBICF_SELECTED; 769 return SBIC_STATE_ERROR; 770 } 771 772 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 773 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 774 775 do { 776 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 777 GET_SBIC_asr(regs, asr); 778 GET_SBIC_csr (regs, csr); 779 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 780 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 781 (csr != SBIC_CSR_CMD_INVALID) ); 782 783 /* 784 * lets just hope it worked.. 785 */ 786 dev->sc_flags &= ~SBICF_SELECTED; 787 } 788 789 return SBIC_STATE_ERROR; 790 } 791 792 793 /* 794 * Initialize driver-private structures 795 */ 796 void 797 sbicinit(dev) 798 struct sbic_softc *dev; 799 { 800 u_int i; 801 802 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 803 804 struct sbic_acb *acb; 805 806 TAILQ_INIT(&dev->ready_list); 807 TAILQ_INIT(&dev->nexus_list); 808 TAILQ_INIT(&dev->free_list); 809 callout_init(&dev->sc_timo_ch); 810 811 dev->sc_nexus = NULL; 812 dev->sc_xs = NULL; 813 814 acb = dev->sc_acb; 815 memset(acb, 0, sizeof(dev->sc_acb)); 816 817 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 818 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 819 acb++; 820 } 821 822 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 823 824 #ifdef DEBUG 825 /* 826 * make sure timeout is really not needed 827 */ 828 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 829 #endif 830 831 } else 832 panic("sbic: reinitializing driver!"); 833 834 dev->sc_flags |= SBICF_ALIVE; 835 dev->sc_flags &= ~SBICF_SELECTED; 836 837 /* 838 * initialize inhibit array 839 * Never enable Sync, since it just doesn't work on mvme147 :( 840 */ 841 for (i = 0; i < 8; ++i) 842 sbic_inhibit_sync[i] = 1; 843 844 sbicreset(dev); 845 } 846 847 void 848 sbicreset(dev) 849 struct sbic_softc *dev; 850 { 851 sbic_regmap_p regs = dev->sc_sbicp; 852 u_int my_id, 853 s; 854 u_char csr; 855 856 s = splbio(); 857 858 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 859 860 if (dev->sc_clkfreq < 110) 861 my_id |= SBIC_ID_FS_8_10; 862 else if (dev->sc_clkfreq < 160) 863 my_id |= SBIC_ID_FS_12_15; 864 else if (dev->sc_clkfreq < 210) 865 my_id |= SBIC_ID_FS_16_20; 866 867 SET_SBIC_myid(regs, my_id); 868 869 /* 870 * Reset the chip 871 */ 872 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 873 DELAY(25); 874 875 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 876 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 877 878 /* 879 * Set up various chip parameters 880 */ 881 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 882 883 /* 884 * don't allow Selection (SBIC_RID_ES) 885 * until we can handle target mode!! 886 */ 887 SET_SBIC_rselid(regs, SBIC_RID_ER); 888 889 /* 890 * Asynchronous for now 891 */ 892 SET_SBIC_syn(regs, 0); 893 894 /* 895 * Anything else was zeroed by reset 896 */ 897 splx(s); 898 899 dev->sc_flags &= ~SBICF_SELECTED; 900 } 901 902 void 903 sbicerror(dev, csr) 904 struct sbic_softc *dev; 905 u_char csr; 906 { 907 struct scsipi_xfer *xs = dev->sc_xs; 908 909 #ifdef DIAGNOSTIC 910 if ( xs == NULL ) 911 panic("sbicerror: dev->sc_xs == NULL"); 912 #endif 913 914 if ( xs->xs_control & XS_CTL_SILENT ) 915 return; 916 917 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 918 } 919 920 /* 921 * select the bus, return when selected or error. 922 * 923 * Returns the current CSR following selection and optionally MSG out phase. 924 * i.e. the returned CSR *should* indicate CMD phase... 925 * If the return value is 0, some error happened. 926 */ 927 u_char 928 sbicselectbus(dev) 929 struct sbic_softc *dev; 930 { 931 sbic_regmap_p regs = dev->sc_sbicp; 932 u_char target = dev->target, 933 lun = dev->lun, 934 asr, 935 csr, 936 id; 937 938 /* 939 * if we're already selected, return (XXXX panic maybe?) 940 */ 941 if ( dev->sc_flags & SBICF_SELECTED ) 942 return(0); 943 944 QPRINTF(("sbicselectbus %d: ", target)); 945 946 /* 947 * issue select 948 */ 949 SET_SBIC_selid(regs, target); 950 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 951 952 GET_SBIC_asr(regs, asr); 953 954 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 955 /* 956 * This means we got ourselves reselected upon 957 */ 958 QPRINTF(("WD busy (reselect?)\n")); 959 return 0; 960 } 961 962 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 963 964 /* 965 * wait for select (merged from separate function may need 966 * cleanup) 967 */ 968 WAIT_CIP(regs); 969 970 do { 971 972 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 973 974 if ( asr & SBIC_ASR_LCI ) { 975 QPRINTF(("late LCI: asr %02x\n", asr)); 976 return 0; 977 } 978 979 /* 980 * Clear interrupt 981 */ 982 GET_SBIC_csr (regs, csr); 983 984 QPRINTF(("%02x ", csr)); 985 986 /* 987 * Reselected from under our feet? 988 */ 989 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 990 QPRINTF(("got reselected, asr %02x\n", asr)); 991 /* 992 * We need to handle this now so we don't lock up later 993 */ 994 sbicnextstate(dev, csr, asr); 995 996 return 0; 997 } 998 999 /* 1000 * Whoops! 1001 */ 1002 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1003 panic("sbicselectbus: target issued select!"); 1004 return 0; 1005 } 1006 1007 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1008 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1009 csr != SBIC_CSR_SEL_TIMEO); 1010 1011 /* 1012 * Anyone at home? 1013 */ 1014 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1015 dev->sc_xs->error = XS_SELTIMEOUT; 1016 QPRINTF(("Selection Timeout\n")); 1017 return 0; 1018 } 1019 1020 QPRINTF(("Selection Complete\n")); 1021 1022 /* 1023 * Assume we're now selected 1024 */ 1025 GET_SBIC_selid(regs, id); 1026 dev->target = id; 1027 dev->lun = lun; 1028 dev->sc_flags |= SBICF_SELECTED; 1029 1030 /* 1031 * Enable (or not) reselection 1032 * XXXSCW This is probably not necessary since we don't use use the 1033 * Select-and-Xfer-with-ATN command to initiate a selection... 1034 */ 1035 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1036 SET_SBIC_rselid (regs, 0); 1037 else 1038 SET_SBIC_rselid (regs, SBIC_RID_ER); 1039 1040 /* 1041 * We only really need to do anything when the target goes to MSG out 1042 * If the device ignored ATN, it's probably old and brain-dead, 1043 * but we'll try to support it anyhow. 1044 * If it doesn't support message out, it definately doesn't 1045 * support synchronous transfers, so no point in even asking... 1046 */ 1047 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1048 /* 1049 * Send identify message (SCSI-2 requires an identify msg) 1050 */ 1051 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1052 /* 1053 * Handle drives that don't want to be asked 1054 * whether to go sync at all. 1055 */ 1056 dev->sc_sync[id].offset = 0; 1057 dev->sc_sync[id].period = sbic_min_period; 1058 dev->sc_sync[id].state = SYNC_DONE; 1059 } 1060 1061 /* 1062 * Do we need to negotiate Synchronous Xfers for this target? 1063 */ 1064 if ( dev->sc_sync[id].state != SYNC_START ) { 1065 /* 1066 * Nope, we've already negotiated. 1067 * Now see if we should allow the target to disconnect/reselect... 1068 */ 1069 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 1070 !sbic_enable_reselect ) 1071 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1072 else 1073 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1074 1075 } else { 1076 /* 1077 * try to initiate a sync transfer. 1078 * So compose the sync message we're going 1079 * to send to the target 1080 */ 1081 #ifdef DEBUG 1082 if ( sync_debug ) 1083 printf("\nSending sync request to target %d ... ", id); 1084 #endif 1085 /* 1086 * setup scsi message sync message request 1087 */ 1088 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1089 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1090 dev->sc_msg[2] = 3; 1091 dev->sc_msg[3] = MSG_SYNC_REQ; 1092 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1093 dev->sc_msg[5] = sbic_max_offset; 1094 1095 sbicxfout(regs, 6, dev->sc_msg); 1096 1097 dev->sc_sync[id].state = SYNC_SENT; 1098 #ifdef DEBUG 1099 if ( sync_debug ) 1100 printf ("sent\n"); 1101 #endif 1102 } 1103 1104 /* 1105 * There's one interrupt still to come: the change to CMD phase... 1106 */ 1107 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1108 GET_SBIC_csr(regs, csr); 1109 } 1110 1111 /* 1112 * set sync or async 1113 */ 1114 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1115 #ifdef DEBUG 1116 if ( sync_debug ) 1117 printf("select(%d): sync reg = 0x%02x\n", target, 1118 SBIC_SYN(dev->sc_sync[target].offset, 1119 dev->sc_sync[target].period)); 1120 #endif 1121 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1122 dev->sc_sync[target].period)); 1123 } else { 1124 #ifdef DEBUG 1125 if ( sync_debug ) 1126 printf("select(%d): sync reg = 0x%02x\n", target, 1127 SBIC_SYN(0,sbic_min_period)); 1128 #endif 1129 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1130 } 1131 1132 return csr; 1133 } 1134 1135 /* 1136 * Information Transfer *to* a Scsi Target. 1137 * 1138 * Note: Don't expect there to be an interrupt immediately after all 1139 * the data is transferred out. The WD spec sheet says that the Transfer- 1140 * Info command for non-MSG_IN phases only completes when the target 1141 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1142 * 1143 * This can have a nasty effect on commands which take a relatively long 1144 * time to complete, for example a START/STOP unit command may remain in 1145 * CMD phase until the disk has spun up. Only then will the target change 1146 * to STATUS phase. This is really only a problem for immediate commands 1147 * since we don't allow disconnection for them (yet). 1148 */ 1149 int 1150 sbicxfout(regs, len, bp) 1151 sbic_regmap_p regs; 1152 int len; 1153 void *bp; 1154 { 1155 int wait = sbic_data_wait; 1156 u_char asr, 1157 *buf = bp; 1158 1159 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1160 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1161 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1162 1163 /* 1164 * sigh.. WD-PROTO strikes again.. sending the command in one go 1165 * causes the chip to lock up if talking to certain (misbehaving?) 1166 * targets. Anyway, this procedure should work for all targets, but 1167 * it's slightly slower due to the overhead 1168 */ 1169 WAIT_CIP (regs); 1170 1171 SBIC_TC_PUT (regs, 0); 1172 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1173 SBIC_TC_PUT (regs, (unsigned)len); 1174 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1175 1176 /* 1177 * Loop for each byte transferred 1178 */ 1179 do { 1180 1181 GET_SBIC_asr (regs, asr); 1182 1183 if ( asr & SBIC_ASR_DBR ) { 1184 if ( len ) { 1185 SET_SBIC_data (regs, *buf); 1186 buf++; 1187 len--; 1188 } else { 1189 SET_SBIC_data (regs, 0); 1190 } 1191 wait = sbic_data_wait; 1192 } 1193 1194 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1195 1196 #ifdef DEBUG 1197 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1198 #endif 1199 1200 /* 1201 * Normally, an interrupt will be pending when this routing returns. 1202 */ 1203 return(len); 1204 } 1205 1206 /* 1207 * Information Transfer *from* a Scsi Target 1208 * returns # bytes left to read 1209 */ 1210 int 1211 sbicxfin(regs, len, bp) 1212 sbic_regmap_p regs; 1213 int len; 1214 void *bp; 1215 { 1216 int wait = sbic_data_wait; 1217 u_char *buf = bp; 1218 u_char asr; 1219 #ifdef DEBUG 1220 u_char *obp = bp; 1221 #endif 1222 1223 WAIT_CIP (regs); 1224 1225 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1226 SBIC_TC_PUT (regs, (unsigned)len); 1227 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1228 1229 /* 1230 * Loop for each byte transferred 1231 */ 1232 do { 1233 1234 GET_SBIC_asr (regs, asr); 1235 1236 if ( asr & SBIC_ASR_DBR ) { 1237 if ( len ) { 1238 GET_SBIC_data (regs, *buf); 1239 buf++; 1240 len--; 1241 } else { 1242 u_char foo; 1243 GET_SBIC_data (regs, foo); 1244 } 1245 wait = sbic_data_wait; 1246 } 1247 1248 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1249 1250 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1251 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1252 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1253 1254 SBIC_TC_PUT (regs, 0); 1255 1256 /* 1257 * this leaves with one csr to be read 1258 */ 1259 return len; 1260 } 1261 1262 /* 1263 * SCSI 'immediate' command: issue a command to some SCSI device 1264 * and get back an 'immediate' response (i.e., do programmed xfer 1265 * to get the response data). 'cbuf' is a buffer containing a scsi 1266 * command of length clen bytes. 'buf' is a buffer of length 'len' 1267 * bytes for data. The transfer direction is determined by the device 1268 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1269 * command must supply no data. 1270 * 1271 * Note that although this routine looks like it can handle disconnect/ 1272 * reselect, the fact is that it can't. There is still some work to be 1273 * done to clean this lot up. 1274 */ 1275 int 1276 sbicicmd(dev, cbuf, clen, buf, len) 1277 struct sbic_softc *dev; 1278 void *cbuf, 1279 *buf; 1280 int clen, 1281 len; 1282 { 1283 sbic_regmap_p regs = dev->sc_sbicp; 1284 struct sbic_acb *acb = dev->sc_nexus; 1285 u_char csr, 1286 asr; 1287 int still_busy = SBIC_STATE_RUNNING; 1288 1289 /* 1290 * Make sure pointers are OK 1291 */ 1292 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1293 dev->sc_tcnt = acb->sc_tcnt = 0; 1294 1295 acb->sc_dmacmd = 0; 1296 acb->sc_pa.dc_count = 0; /* No DMA */ 1297 acb->sc_kv.dc_addr = buf; 1298 acb->sc_kv.dc_count = len; 1299 1300 #ifdef DEBUG 1301 if ( data_pointer_debug > 1 ) 1302 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1303 #endif 1304 1305 /* 1306 * set the sbic into non-DMA mode 1307 */ 1308 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1309 1310 dev->sc_stat[0] = 0xff; 1311 dev->sc_msg[0] = 0xff; 1312 1313 /* 1314 * We're stealing the SCSI bus 1315 */ 1316 dev->sc_flags |= SBICF_ICMD; 1317 1318 do { 1319 GET_SBIC_asr (regs, asr); 1320 1321 /* 1322 * select the SCSI bus (it's an error if bus isn't free) 1323 */ 1324 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1325 still_busy != SBIC_STATE_DISCONNECT ) { 1326 if ( (csr = sbicselectbus(dev)) == 0 ) { 1327 dev->sc_flags &= ~SBICF_ICMD; 1328 return(-1); 1329 } 1330 } else 1331 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1332 GET_SBIC_csr(regs, csr); 1333 else 1334 csr = 0; 1335 1336 if ( csr ) { 1337 1338 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1339 1340 switch ( csr ) { 1341 1342 case SBIC_CSR_S_XFERRED: 1343 case SBIC_CSR_DISC: 1344 case SBIC_CSR_DISC_1: 1345 { 1346 u_char phase; 1347 1348 dev->sc_flags &= ~SBICF_SELECTED; 1349 GET_SBIC_cmd_phase (regs, phase); 1350 1351 if ( phase == 0x60 ) { 1352 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1353 still_busy = SBIC_STATE_DONE; /* done */ 1354 } else { 1355 #ifdef DEBUG 1356 if ( reselect_debug > 1 ) 1357 printf("sbicicmd: handling disconnect\n"); 1358 #endif 1359 still_busy = SBIC_STATE_DISCONNECT; 1360 } 1361 } 1362 break; 1363 1364 case SBIC_CSR_XFERRED | CMD_PHASE: 1365 case SBIC_CSR_MIS | CMD_PHASE: 1366 case SBIC_CSR_MIS_1 | CMD_PHASE: 1367 case SBIC_CSR_MIS_2 | CMD_PHASE: 1368 { 1369 if ( sbicxfout(regs, clen, cbuf) ) 1370 still_busy = sbicabort(dev, "icmd sending cmd"); 1371 } 1372 break; 1373 1374 case SBIC_CSR_XFERRED | STATUS_PHASE: 1375 case SBIC_CSR_MIS | STATUS_PHASE: 1376 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1377 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1378 { 1379 /* 1380 * The sbic does the status/cmd-complete reading ok, 1381 * so do this with its hi-level commands. 1382 */ 1383 #ifdef DEBUG 1384 if ( sbic_debug ) 1385 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1386 #endif 1387 SET_SBIC_cmd_phase(regs, 0x46); 1388 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1389 } 1390 break; 1391 1392 default: 1393 { 1394 still_busy = sbicnextstate(dev, csr, asr); 1395 } 1396 break; 1397 } 1398 1399 /* 1400 * make sure the last command was taken, 1401 * ie. we're not hunting after an ignored command.. 1402 */ 1403 GET_SBIC_asr(regs, asr); 1404 1405 /* 1406 * tapes may take a loooong time.. 1407 */ 1408 while (asr & SBIC_ASR_BSY ) { 1409 1410 if ( asr & SBIC_ASR_DBR ) { 1411 int i; 1412 1413 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1414 #ifdef DDB 1415 Debugger(); 1416 #endif 1417 /* 1418 * SBIC is jammed 1419 * DUNNO which direction 1420 * Try old direction 1421 */ 1422 GET_SBIC_data(regs, i); 1423 GET_SBIC_asr(regs, asr); 1424 1425 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1426 SET_SBIC_data(regs, i); 1427 } 1428 1429 GET_SBIC_asr(regs, asr); 1430 } 1431 } 1432 1433 /* 1434 * wait for last command to complete 1435 */ 1436 if ( asr & SBIC_ASR_LCI ) { 1437 printf("sbicicmd: last command ignored\n"); 1438 } 1439 else 1440 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1441 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1442 1443 /* 1444 * do it again 1445 */ 1446 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1447 1448 /* 1449 * Sometimes we need to do an extra read of the CSR 1450 */ 1451 GET_SBIC_csr(regs, csr); 1452 1453 #ifdef DEBUG 1454 if ( data_pointer_debug > 1 ) 1455 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1456 acb->sc_kv.dc_count, 1457 dev->sc_stat[0]); 1458 #endif 1459 1460 dev->sc_flags &= ~SBICF_ICMD; 1461 1462 return(dev->sc_stat[0]); 1463 } 1464 1465 /* 1466 * Finish SCSI xfer command: After the completion interrupt from 1467 * a read/write operation, sequence through the final phases in 1468 * programmed i/o. This routine is a lot like sbicicmd except we 1469 * skip (and don't allow) the select, cmd out and data in/out phases. 1470 */ 1471 void 1472 sbicxfdone(dev) 1473 struct sbic_softc *dev; 1474 { 1475 sbic_regmap_p regs = dev->sc_sbicp; 1476 u_char phase, 1477 csr; 1478 int s; 1479 1480 QPRINTF(("{")); 1481 s = splbio(); 1482 1483 /* 1484 * have the sbic complete on its own 1485 */ 1486 SBIC_TC_PUT(regs, 0); 1487 SET_SBIC_cmd_phase(regs, 0x46); 1488 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1489 1490 do { 1491 1492 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1493 GET_SBIC_csr (regs, csr); 1494 QPRINTF(("%02x:", csr)); 1495 1496 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1497 (csr != SBIC_CSR_S_XFERRED)); 1498 1499 dev->sc_flags &= ~SBICF_SELECTED; 1500 1501 GET_SBIC_cmd_phase (regs, phase); 1502 QPRINTF(("}%02x", phase)); 1503 1504 if ( phase == 0x60 ) 1505 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1506 else 1507 sbicerror(dev, csr); 1508 1509 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1510 1511 splx(s); 1512 } 1513 1514 /* 1515 * No DMA chains 1516 */ 1517 int 1518 sbicgo(dev, xs) 1519 struct sbic_softc *dev; 1520 struct scsipi_xfer *xs; 1521 { 1522 struct sbic_acb *acb = dev->sc_nexus; 1523 sbic_regmap_p regs = dev->sc_sbicp; 1524 int i, 1525 dmaflags, 1526 count, 1527 usedma; 1528 u_char csr, 1529 asr, 1530 *addr; 1531 1532 dev->target = xs->xs_periph->periph_target; 1533 dev->lun = xs->xs_periph->periph_lun; 1534 1535 usedma = sbicdmaok(dev, xs); 1536 1537 #ifdef DEBUG 1538 if ( data_pointer_debug > 1 ) 1539 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1540 #endif 1541 1542 /* 1543 * select the SCSI bus (it's an error if bus isn't free) 1544 */ 1545 if ( (csr = sbicselectbus(dev)) == 0 ) 1546 return(0); /* Not done: needs to be rescheduled */ 1547 1548 dev->sc_stat[0] = 0xff; 1549 1550 /* 1551 * Calculate DMA chains now 1552 */ 1553 if ( acb->flags & ACB_DATAIN ) 1554 dmaflags = DMAGO_READ; 1555 else 1556 dmaflags = 0; 1557 1558 addr = acb->sc_kv.dc_addr; 1559 count = acb->sc_kv.dc_count; 1560 1561 if ( count && ((char *)kvtop((caddr_t)addr) != acb->sc_pa.dc_addr) ) { 1562 printf("sbic: DMA buffer mapping changed %p->%x\n", 1563 acb->sc_pa.dc_addr, kvtop((caddr_t)addr)); 1564 #ifdef DDB 1565 Debugger(); 1566 #endif 1567 } 1568 1569 #ifdef DEBUG 1570 ++sbicdma_ops; /* count total DMA operations */ 1571 #endif 1572 1573 /* 1574 * Allocate the DMA chain 1575 * Mark end of segment... 1576 */ 1577 acb->sc_tcnt = dev->sc_tcnt = 0; 1578 acb->sc_pa.dc_count = 0; 1579 1580 sbic_load_ptrs(dev); 1581 1582 /* 1583 * Enable interrupts but don't do any DMA 1584 * enintr() also enables interrupts for the sbic 1585 */ 1586 dev->sc_enintr(dev); 1587 1588 if ( usedma ) { 1589 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1590 acb->sc_pa.dc_count, dmaflags); 1591 #ifdef DEBUG 1592 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1593 #endif 1594 } else 1595 dev->sc_dmacmd = 0; /* Don't use DMA */ 1596 1597 acb->sc_dmacmd = dev->sc_dmacmd; 1598 1599 #ifdef DEBUG 1600 if ( data_pointer_debug > 1 ) { 1601 printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, 1602 dev->sc_cur->dc_addr, 1603 dev->sc_tcnt, 1604 dev->sc_dmacmd); 1605 } 1606 #endif 1607 1608 /* 1609 * Lets cycle a while then let the interrupt handler take over. 1610 */ 1611 GET_SBIC_asr(regs, asr); 1612 1613 do { 1614 1615 QPRINTF(("go ")); 1616 1617 /* 1618 * Handle the new phase 1619 */ 1620 i = sbicnextstate(dev, csr, asr); 1621 #if 0 1622 WAIT_CIP(regs); 1623 #endif 1624 if ( i == SBIC_STATE_RUNNING ) { 1625 GET_SBIC_asr(regs, asr); 1626 1627 if ( asr & SBIC_ASR_LCI ) 1628 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1629 1630 if ( asr & SBIC_ASR_INT ) 1631 GET_SBIC_csr(regs, csr); 1632 } 1633 1634 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1635 1636 if ( i == SBIC_STATE_DONE ) { 1637 if ( dev->sc_stat[0] == 0xff ) 1638 #if 0 1639 printf("sbicgo: done & stat = 0xff\n"); 1640 #else 1641 ; 1642 #endif 1643 else 1644 return 1; /* Did we really finish that fast? */ 1645 } 1646 1647 return 0; 1648 } 1649 1650 1651 int 1652 sbicintr(dev) 1653 struct sbic_softc *dev; 1654 { 1655 sbic_regmap_p regs = dev->sc_sbicp; 1656 u_char asr, 1657 csr; 1658 int i; 1659 1660 /* 1661 * pending interrupt? 1662 */ 1663 GET_SBIC_asr (regs, asr); 1664 if ( (asr & SBIC_ASR_INT) == 0 ) 1665 return(0); 1666 1667 GET_SBIC_csr(regs, csr); 1668 1669 do { 1670 1671 QPRINTF(("intr[0x%x]", csr)); 1672 1673 i = sbicnextstate(dev, csr, asr); 1674 #if 0 1675 WAIT_CIP(regs); 1676 #endif 1677 if ( i == SBIC_STATE_RUNNING ) { 1678 GET_SBIC_asr(regs, asr); 1679 1680 if ( asr & SBIC_ASR_LCI ) 1681 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1682 1683 if ( asr & SBIC_ASR_INT ) 1684 GET_SBIC_csr(regs, csr); 1685 } 1686 1687 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1688 1689 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1690 1691 return(1); 1692 } 1693 1694 /* 1695 * Run commands and wait for disconnect. 1696 * This is only ever called when a command is in progress, when we 1697 * want to busy wait for it to finish. 1698 */ 1699 int 1700 sbicpoll(dev) 1701 struct sbic_softc *dev; 1702 { 1703 sbic_regmap_p regs = dev->sc_sbicp; 1704 u_char asr, 1705 csr; 1706 int i; 1707 1708 /* 1709 * Wait for the next interrupt 1710 */ 1711 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1712 1713 do { 1714 GET_SBIC_asr (regs, asr); 1715 1716 if ( asr & SBIC_ASR_INT ) 1717 GET_SBIC_csr(regs, csr); 1718 1719 QPRINTF(("poll[0x%x]", csr)); 1720 1721 /* 1722 * Handle it 1723 */ 1724 i = sbicnextstate(dev, csr, asr); 1725 1726 WAIT_CIP(regs); 1727 GET_SBIC_asr(regs, asr); 1728 1729 /* 1730 * tapes may take a loooong time.. 1731 */ 1732 while ( asr & SBIC_ASR_BSY ) { 1733 u_char z = 0; 1734 1735 if ( asr & SBIC_ASR_DBR ) { 1736 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1737 #ifdef DDB 1738 Debugger(); 1739 #endif 1740 /* 1741 * SBIC is jammed 1742 * DUNNO which direction 1743 * Try old direction 1744 */ 1745 GET_SBIC_data(regs, z); 1746 GET_SBIC_asr(regs, asr); 1747 1748 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1749 SET_SBIC_data(regs, z); 1750 } 1751 1752 GET_SBIC_asr(regs, asr); 1753 } 1754 1755 if ( asr & SBIC_ASR_LCI ) 1756 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1757 else 1758 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1759 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1760 1761 } while ( i == SBIC_STATE_RUNNING ); 1762 1763 return(1); 1764 } 1765 1766 /* 1767 * Handle a single msgin 1768 */ 1769 int 1770 sbicmsgin(dev) 1771 struct sbic_softc *dev; 1772 { 1773 sbic_regmap_p regs = dev->sc_sbicp; 1774 int recvlen = 1; 1775 u_char asr, 1776 csr, 1777 *tmpaddr, 1778 *msgaddr; 1779 1780 tmpaddr = msgaddr = dev->sc_msg; 1781 1782 tmpaddr[0] = 0xff; 1783 tmpaddr[1] = 0xff; 1784 1785 GET_SBIC_asr(regs, asr); 1786 1787 #ifdef DEBUG 1788 if ( reselect_debug > 1 ) 1789 printf("sbicmsgin asr=%02x\n", asr); 1790 #endif 1791 1792 GET_SBIC_selid (regs, csr); 1793 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1794 1795 SBIC_TC_PUT(regs, 0); 1796 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1797 1798 do { 1799 while( recvlen-- ) { 1800 1801 /* 1802 * Fetch the next byte of the message 1803 */ 1804 RECV_BYTE(regs, *tmpaddr); 1805 1806 /* 1807 * get the command completion interrupt, or we 1808 * can't send a new command (LCI) 1809 */ 1810 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1811 GET_SBIC_csr(regs, csr); 1812 1813 #ifdef DEBUG 1814 if ( reselect_debug > 1 ) 1815 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1816 #endif 1817 1818 tmpaddr++; 1819 1820 if ( recvlen ) { 1821 /* 1822 * Clear ACK, and wait for the interrupt for the next byte 1823 */ 1824 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1825 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1826 GET_SBIC_csr(regs, csr); 1827 } 1828 } 1829 1830 if ( msgaddr[0] == 0xff ) { 1831 printf("sbicmsgin: sbic swallowed our message\n"); 1832 break; 1833 } 1834 1835 #ifdef DEBUG 1836 if ( sync_debug ) { 1837 GET_SBIC_asr(regs, asr); 1838 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1839 } 1840 #endif 1841 /* 1842 * test whether this is a reply to our sync 1843 * request 1844 */ 1845 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1846 1847 /* 1848 * Got IFFY msg -- ack it 1849 */ 1850 QPRINTF(("IFFY")); 1851 1852 } else 1853 if ( msgaddr[0] == MSG_REJECT && 1854 dev->sc_sync[dev->target].state == SYNC_SENT) { 1855 1856 /* 1857 * Target probably rejected our Sync negotiation. 1858 */ 1859 QPRINTF(("REJECT of SYN")); 1860 1861 #ifdef DEBUG 1862 if ( sync_debug ) 1863 printf("target %d rejected sync, going async\n", dev->target); 1864 #endif 1865 1866 dev->sc_sync[dev->target].period = sbic_min_period; 1867 dev->sc_sync[dev->target].offset = 0; 1868 dev->sc_sync[dev->target].state = SYNC_DONE; 1869 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1870 dev->sc_sync[dev->target].period)); 1871 1872 } else 1873 if ( msgaddr[0] == MSG_REJECT ) { 1874 1875 /* 1876 * we'll never REJECt a REJECT message.. 1877 */ 1878 QPRINTF(("REJECT")); 1879 1880 } else 1881 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1882 1883 /* 1884 * don't reject this either. 1885 */ 1886 QPRINTF(("MSG_SAVE_DATA_PTR")); 1887 1888 } else 1889 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1890 1891 /* 1892 * don't reject this either. 1893 */ 1894 QPRINTF(("MSG_RESTORE_PTR")); 1895 1896 } else 1897 if ( msgaddr[0] == MSG_DISCONNECT ) { 1898 1899 /* 1900 * Target is disconnecting... 1901 */ 1902 QPRINTF(("DISCONNECT")); 1903 1904 #ifdef DEBUG 1905 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1906 printf("sbicmsgin: got disconnect msg %s\n", 1907 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1908 #endif 1909 1910 if ( dev->sc_flags & SBICF_ICMD ) { 1911 /* 1912 * We're in immediate mode. Prevent disconnects. 1913 * prepare to reject the message, NACK 1914 */ 1915 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1916 WAIT_CIP(regs); 1917 } 1918 1919 } else 1920 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1921 1922 /* 1923 * !! KLUDGE ALERT !! quite a few drives don't seem to 1924 * really like the current way of sending the 1925 * sync-handshake together with the ident-message, and 1926 * they react by sending command-complete and 1927 * disconnecting right after returning the valid sync 1928 * handshake. So, all I can do is reselect the drive, 1929 * and hope it won't disconnect again. I don't think 1930 * this is valid behavior, but I can't help fixing a 1931 * problem that apparently exists. 1932 * 1933 * Note: we should not get here on `normal' command 1934 * completion, as that condition is handled by the 1935 * high-level sel&xfer resume command used to walk 1936 * thru status/cc-phase. 1937 */ 1938 QPRINTF(("CMD_COMPLETE")); 1939 1940 #ifdef DEBUG 1941 if ( sync_debug ) 1942 printf ("GOT MSG %d! target %d acting weird.." 1943 " waiting for disconnect...\n", msgaddr[0], dev->target); 1944 #endif 1945 1946 /* 1947 * Check to see if sbic is handling this 1948 */ 1949 GET_SBIC_asr(regs, asr); 1950 1951 /* 1952 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 1953 */ 1954 if ( asr & SBIC_ASR_BSY ) 1955 return SBIC_STATE_RUNNING; 1956 1957 /* 1958 * Let's try this: Assume it works and set status to 00 1959 */ 1960 dev->sc_stat[0] = 0; 1961 1962 } else 1963 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 1964 1965 /* 1966 * Target is sending us an extended message. We'll assume it's 1967 * the response to our Sync. negotiation. 1968 */ 1969 QPRINTF(("ExtMSG\n")); 1970 1971 /* 1972 * Read in whole extended message. First, negate ACK to accept 1973 * the MSG_EXT_MESSAGE byte... 1974 */ 1975 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1976 1977 /* 1978 * Wait for the interrupt for the next byte (length) 1979 */ 1980 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1981 GET_SBIC_csr(regs, csr); 1982 1983 #ifdef DEBUG 1984 QPRINTF(("CLR ACK csr %02x\n", csr)); 1985 #endif 1986 1987 /* 1988 * Read the length byte 1989 */ 1990 RECV_BYTE(regs, *tmpaddr); 1991 1992 /* 1993 * Wait for command completion IRQ 1994 */ 1995 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1996 GET_SBIC_csr(regs, csr); 1997 1998 /* 1999 * Reload the loop counter 2000 */ 2001 recvlen = *tmpaddr++; 2002 2003 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2004 2005 } else 2006 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2007 msgaddr[2] == MSG_SYNC_REQ ) { 2008 2009 /* 2010 * We've received the complete Extended Message Sync. Request... 2011 */ 2012 QPRINTF(("SYN")); 2013 2014 /* 2015 * Compute the required Transfer Period for the WD chip... 2016 */ 2017 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2018 dev->sc_sync[dev->target].offset = msgaddr[4]; 2019 dev->sc_sync[dev->target].state = SYNC_DONE; 2020 2021 /* 2022 * Put the WD chip in synchronous mode 2023 */ 2024 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2025 dev->sc_sync[dev->target].period)); 2026 #ifdef DEBUG 2027 if ( sync_debug ) 2028 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2029 SBIC_SYN(dev->sc_sync[dev->target].offset, 2030 dev->sc_sync[dev->target].period)); 2031 #endif 2032 2033 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2034 dev->sc_dev.dv_xname, dev->target, 2035 msgaddr[3] * 4, msgaddr[4]); 2036 2037 } else { 2038 2039 /* 2040 * We don't support whatever this message is... 2041 */ 2042 #ifdef DEBUG 2043 if ( sbic_debug || sync_debug ) 2044 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2045 #endif 2046 2047 /* 2048 * prepare to reject the message, NACK 2049 */ 2050 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2051 WAIT_CIP(regs); 2052 } 2053 2054 /* 2055 * Negate ACK to complete the transfer 2056 */ 2057 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2058 2059 /* 2060 * Wait for the interrupt for the next byte, or phase change. 2061 * Only read the CSR if we have more data to transfer. 2062 * XXXSCW: We should really verify that we're still in MSG IN phase 2063 * before blindly going back around this loop, but that would mean 2064 * we read the CSR... <sigh> 2065 */ 2066 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2067 if ( recvlen > 0 ) 2068 GET_SBIC_csr(regs, csr); 2069 2070 } while ( recvlen > 0 ); 2071 2072 /* 2073 * Should still have one CSR to read 2074 */ 2075 return SBIC_STATE_RUNNING; 2076 } 2077 2078 2079 /* 2080 * sbicnextstate() 2081 * return: 2082 * SBIC_STATE_DONE == done 2083 * SBIC_STATE_RUNNING == working 2084 * SBIC_STATE_DISCONNECT == disconnected 2085 * SBIC_STATE_ERROR == error 2086 */ 2087 int 2088 sbicnextstate(dev, csr, asr) 2089 struct sbic_softc *dev; 2090 u_char csr, 2091 asr; 2092 { 2093 sbic_regmap_p regs = dev->sc_sbicp; 2094 struct sbic_acb *acb = dev->sc_nexus; 2095 2096 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2097 2098 switch (csr) { 2099 2100 case SBIC_CSR_XFERRED | CMD_PHASE: 2101 case SBIC_CSR_MIS | CMD_PHASE: 2102 case SBIC_CSR_MIS_1 | CMD_PHASE: 2103 case SBIC_CSR_MIS_2 | CMD_PHASE: 2104 { 2105 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2106 goto abort; 2107 } 2108 break; 2109 2110 case SBIC_CSR_XFERRED | STATUS_PHASE: 2111 case SBIC_CSR_MIS | STATUS_PHASE: 2112 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2113 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2114 { 2115 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2116 2117 /* 2118 * this should be the normal i/o completion case. 2119 * get the status & cmd complete msg then let the 2120 * device driver look at what happened. 2121 */ 2122 sbicxfdone(dev); 2123 2124 #ifdef DEBUG 2125 dev->sc_dmatimo = 0; 2126 if ( data_pointer_debug > 1 ) 2127 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2128 dev->sc_cur->dc_addr, 2129 dev->sc_tcnt); 2130 #endif 2131 /* 2132 * Stop the DMA chip 2133 */ 2134 dev->sc_dmastop(dev); 2135 2136 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2137 2138 /* 2139 * Indicate to the upper layers that the command is done 2140 */ 2141 sbic_scsidone(acb, dev->sc_stat[0]); 2142 2143 return SBIC_STATE_DONE; 2144 } 2145 2146 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2147 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2148 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2149 case SBIC_CSR_MIS | DATA_IN_PHASE: 2150 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2151 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2152 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2153 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2154 { 2155 /* 2156 * Verify that we expected to transfer data... 2157 */ 2158 if ( acb->sc_kv.dc_count <= 0 ) { 2159 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2160 acb->sc_kv.dc_count, asr, csr); 2161 goto abort; 2162 } 2163 2164 /* 2165 * Should we transfer using PIO or DMA ? 2166 */ 2167 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2168 acb->sc_dmacmd == 0 ) { 2169 2170 /* 2171 * Do PIO transfer 2172 */ 2173 int i; 2174 2175 #ifdef DEBUG 2176 if ( data_pointer_debug > 1 ) 2177 printf("next PIO: %d(%p:%x)\n", dev->target, 2178 acb->sc_kv.dc_addr, 2179 acb->sc_kv.dc_count); 2180 #endif 2181 2182 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2183 /* 2184 * data in 2185 */ 2186 i = sbicxfin(regs, acb->sc_kv.dc_count, 2187 acb->sc_kv.dc_addr); 2188 else 2189 /* 2190 * data out 2191 */ 2192 i = sbicxfout(regs, acb->sc_kv.dc_count, 2193 acb->sc_kv.dc_addr); 2194 2195 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2196 acb->sc_kv.dc_count = i; 2197 2198 /* 2199 * Update current count... 2200 */ 2201 acb->sc_tcnt = dev->sc_tcnt = i; 2202 2203 dev->sc_flags &= ~SBICF_INDMA; 2204 2205 } else { 2206 2207 /* 2208 * Do DMA transfer 2209 * set next dma addr and dec count 2210 */ 2211 sbic_save_ptrs(dev); 2212 sbic_load_ptrs(dev); 2213 2214 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2215 SBIC_MACHINE_DMA_MODE); 2216 2217 #ifdef DEBUG 2218 dev->sc_dmatimo = 1; 2219 if ( data_pointer_debug > 1 ) 2220 printf("next DMA: %d(%p:%lx)\n", dev->target, 2221 dev->sc_cur->dc_addr, 2222 dev->sc_tcnt); 2223 #endif 2224 /* 2225 * Start the DMA chip going 2226 */ 2227 dev->sc_tcnt = dev->sc_dmanext(dev); 2228 2229 /* 2230 * Tell the WD chip how much to transfer this time around 2231 */ 2232 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2233 2234 /* 2235 * Start the transfer 2236 */ 2237 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2238 2239 /* 2240 * Indicate that we're in DMA mode 2241 */ 2242 dev->sc_flags |= SBICF_INDMA; 2243 } 2244 } 2245 break; 2246 2247 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2248 case SBIC_CSR_MIS | MESG_IN_PHASE: 2249 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2250 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2251 { 2252 sbic_save_ptrs(dev); 2253 2254 /* 2255 * Handle a single message in... 2256 */ 2257 return sbicmsgin(dev); 2258 } 2259 2260 case SBIC_CSR_MSGIN_W_ACK: 2261 { 2262 /* 2263 * We should never see this since it's handled in 'sbicmsgin()' 2264 * but just for the sake of paranoia... 2265 */ 2266 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2267 printf("Acking unknown msgin CSR:%02x",csr); 2268 } 2269 break; 2270 2271 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2272 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2273 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2274 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2275 { 2276 /* 2277 * We only ever handle a message out phase here for sending a 2278 * REJECT message. 2279 */ 2280 sbic_save_ptrs(dev); 2281 2282 #ifdef DEBUG 2283 if (sync_debug) 2284 printf ("sending REJECT msg to last msg.\n"); 2285 #endif 2286 2287 SEND_BYTE(regs, MSG_REJECT); 2288 WAIT_CIP(regs); 2289 } 2290 break; 2291 2292 case SBIC_CSR_DISC: 2293 case SBIC_CSR_DISC_1: 2294 { 2295 /* 2296 * Try to schedule another target 2297 */ 2298 sbic_save_ptrs(dev); 2299 2300 dev->sc_flags &= ~SBICF_SELECTED; 2301 2302 #ifdef DEBUG 2303 if ( reselect_debug > 1 ) 2304 printf("sbicnext target %d disconnected\n", dev->target); 2305 #endif 2306 2307 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2308 2309 ++dev->sc_tinfo[dev->target].dconns; 2310 2311 dev->sc_nexus = NULL; 2312 dev->sc_xs = NULL; 2313 2314 if ( acb->xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2315 !sbic_parallel_operations ) 2316 return SBIC_STATE_DISCONNECT; 2317 2318 QPRINTF(("sbicnext: calling sbic_sched\n")); 2319 2320 sbic_sched(dev); 2321 2322 QPRINTF(("sbicnext: sbic_sched returned\n")); 2323 2324 return SBIC_STATE_DISCONNECT; 2325 } 2326 2327 case SBIC_CSR_RSLT_NI: 2328 case SBIC_CSR_RSLT_IFY: 2329 { 2330 /* 2331 * A reselection. 2332 * Note that since we don't enable Advanced Features (assuming 2333 * the WD chip is at least the 'A' revision), we're only ever 2334 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2335 * hell of it, we'll handle it anyway, for all the extra code 2336 * it needs... 2337 */ 2338 u_char newtarget, 2339 newlun; 2340 2341 GET_SBIC_rselid(regs, newtarget); 2342 2343 /* 2344 * check SBIC_RID_SIV? 2345 */ 2346 newtarget &= SBIC_RID_MASK; 2347 2348 if ( csr == SBIC_CSR_RSLT_IFY ) { 2349 2350 /* 2351 * Read Identify msg to avoid lockup 2352 */ 2353 GET_SBIC_data(regs, newlun); 2354 WAIT_CIP(regs); 2355 newlun &= SBIC_TLUN_MASK; 2356 2357 } else { 2358 2359 /* 2360 * Need to read Identify message the hard way, assuming 2361 * the target even sends us one... 2362 */ 2363 for (newlun = 255; newlun; --newlun) { 2364 GET_SBIC_asr(regs, asr); 2365 if (asr & SBIC_ASR_INT) 2366 break; 2367 delay(10); 2368 } 2369 2370 /* 2371 * If we didn't get an interrupt, somethink's up 2372 */ 2373 if ( (asr & SBIC_ASR_INT) == 0 ) { 2374 printf("%s: Reselect without identify? asr %x\n", 2375 dev->sc_dev.dv_xname, asr); 2376 newlun = 0; /* XXXX */ 2377 } else { 2378 /* 2379 * We got an interrupt, verify that it's a change to 2380 * message in phase, and if so read the message. 2381 */ 2382 GET_SBIC_csr(regs,csr); 2383 2384 if ( csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2385 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2386 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE) ) { 2387 /* 2388 * Yup, gone to message in. Fetch the target LUN 2389 */ 2390 sbicmsgin(dev); 2391 newlun = dev->sc_msg[0] & 0x07; 2392 2393 } else { 2394 /* 2395 * Whoops! Target didn't go to message in phase!! 2396 */ 2397 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2398 newlun = 0; /* XXXSCW */ 2399 } 2400 } 2401 } 2402 2403 /* 2404 * Ok, we have the identity of the reselecting target. 2405 */ 2406 #ifdef DEBUG 2407 if ( reselect_debug > 1 || 2408 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2409 printf("sbicnext: reselect %s from targ %d lun %d\n", 2410 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2411 } 2412 #endif 2413 2414 if ( dev->sc_nexus ) { 2415 /* 2416 * Whoops! We've been reselected with an command in progress! 2417 * The best we can do is to put the current command back on the 2418 * ready list and hope for the best. 2419 */ 2420 #ifdef DEBUG 2421 if ( reselect_debug > 1 ) { 2422 printf("%s: reselect %s with active command\n", 2423 dev->sc_dev.dv_xname, 2424 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2425 } 2426 #endif 2427 2428 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2429 2430 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2431 2432 dev->sc_nexus = NULL; 2433 dev->sc_xs = NULL; 2434 } 2435 2436 /* 2437 * Reload sync values for this target 2438 */ 2439 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2440 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2441 dev->sc_sync[newtarget].period)); 2442 else 2443 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2444 2445 /* 2446 * Loop through the nexus list until we find the saved entry 2447 * for the reselecting target... 2448 */ 2449 for (acb = dev->nexus_list.tqh_first; acb; 2450 acb = acb->chain.tqe_next) { 2451 2452 if ( acb->xs->xs_periph->periph_target == newtarget && 2453 acb->xs->xs_periph->periph_lun == newlun) { 2454 /* 2455 * We've found the saved entry. Dequeue it, and 2456 * make it current again. 2457 */ 2458 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2459 2460 dev->sc_nexus = acb; 2461 dev->sc_xs = acb->xs; 2462 dev->sc_flags |= SBICF_SELECTED; 2463 dev->target = newtarget; 2464 dev->lun = newlun; 2465 break; 2466 } 2467 } 2468 2469 if ( acb == NULL ) { 2470 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2471 dev->sc_dev.dv_xname, 2472 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2473 &dev->nexus_list.tqh_first); 2474 panic("bad reselect in sbic"); 2475 } 2476 2477 if ( csr == SBIC_CSR_RSLT_IFY ) 2478 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2479 } 2480 break; 2481 2482 default: 2483 abort: 2484 { 2485 /* 2486 * Something unexpected happened -- deal with it. 2487 */ 2488 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2489 2490 #ifdef DDB 2491 Debugger(); 2492 #endif 2493 2494 #ifdef DEBUG 2495 dev->sc_dmatimo = 0; 2496 if ( data_pointer_debug > 1 ) 2497 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2498 dev->sc_cur->dc_addr, 2499 dev->sc_tcnt); 2500 #endif 2501 2502 dev->sc_dmastop(dev); 2503 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2504 if ( dev->sc_xs ) sbicerror(dev, csr); 2505 sbicabort(dev, "next"); 2506 2507 if ( dev->sc_flags & SBICF_INDMA ) { 2508 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2509 2510 #ifdef DEBUG 2511 dev->sc_dmatimo = 0; 2512 if ( data_pointer_debug > 1 ) 2513 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2514 dev->sc_cur->dc_addr, 2515 dev->sc_tcnt); 2516 #endif 2517 sbic_scsidone(acb, -1); 2518 } 2519 2520 return SBIC_STATE_ERROR; 2521 } 2522 } 2523 2524 return(SBIC_STATE_RUNNING); 2525 } 2526 2527 2528 /* 2529 * Check if DMA can not be used with specified buffer 2530 */ 2531 int 2532 sbiccheckdmap(bp, len, mask) 2533 void *bp; 2534 u_long len, 2535 mask; 2536 { 2537 u_char *buffer; 2538 u_long phy_buf; 2539 u_long phy_len; 2540 2541 buffer = bp; 2542 2543 if ( len == 0 ) 2544 return(1); 2545 2546 while ( len ) { 2547 2548 phy_buf = kvtop((caddr_t)buffer); 2549 phy_len = NBPG - ((int) buffer & PGOFSET); 2550 2551 if ( len < phy_len ) 2552 phy_len = len; 2553 2554 if ( phy_buf & mask ) 2555 return(1); 2556 2557 buffer += phy_len; 2558 len -= phy_len; 2559 } 2560 2561 return(0); 2562 } 2563 2564 int 2565 sbictoscsiperiod(dev, a) 2566 struct sbic_softc *dev; 2567 int a; 2568 { 2569 unsigned int fs; 2570 2571 /* 2572 * cycle = DIV / (2 * CLK) 2573 * DIV = FS + 2 2574 * best we can do is 200ns at 20Mhz, 2 cycles 2575 */ 2576 2577 GET_SBIC_myid(dev->sc_sbicp, fs); 2578 2579 fs = (fs >> 6) + 2; /* DIV */ 2580 2581 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2582 2583 if ( a < 2 ) 2584 a = 8; /* map to Cycles */ 2585 2586 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2587 } 2588 2589 int 2590 sbicfromscsiperiod(dev, p) 2591 struct sbic_softc *dev; 2592 int p; 2593 { 2594 unsigned fs, 2595 ret; 2596 2597 /* 2598 * Just the inverse of the above 2599 */ 2600 GET_SBIC_myid(dev->sc_sbicp, fs); 2601 2602 fs = (fs >> 6) + 2; /* DIV */ 2603 2604 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2605 2606 ret = p << 2; /* in ns units */ 2607 ret = ret / fs; /* in Cycles */ 2608 2609 if ( ret < sbic_min_period ) 2610 return(sbic_min_period); 2611 2612 /* 2613 * verify rounding 2614 */ 2615 if ( sbictoscsiperiod(dev, ret) < p ) 2616 ret++; 2617 2618 return( (ret >= 8) ? 0 : ret ); 2619 } 2620 2621 #ifdef DEBUG 2622 void 2623 sbictimeout(dev) 2624 struct sbic_softc *dev; 2625 { 2626 int s, 2627 asr; 2628 2629 s = splbio(); 2630 2631 if ( dev->sc_dmatimo ) { 2632 2633 if ( dev->sc_dmatimo > 1 ) { 2634 2635 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2636 dev->sc_dmatimo - 1); 2637 2638 GET_SBIC_asr(dev->sc_sbicp, asr); 2639 2640 if ( asr & SBIC_ASR_INT ) { 2641 /* 2642 * We need to service a missed IRQ 2643 */ 2644 sbicintr(dev); 2645 } else { 2646 (void) sbicabort(dev, "timeout"); 2647 splx(s); 2648 return; 2649 } 2650 } 2651 2652 dev->sc_dmatimo++; 2653 } 2654 2655 splx(s); 2656 2657 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 2658 } 2659 #endif 2660
Indexes created Sat Sep 27 22:09:54 GMT 2025