sbic.c revision 1.2
1 /* $NetBSD: sbic.c,v 1.2 1996/04/23 16:32:54 chuck Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/kernel.h> /* For hz */ 60 #include <sys/disklabel.h> 61 #include <sys/dkstat.h> 62 #include <sys/buf.h> 63 #include <scsi/scsi_all.h> 64 #include <scsi/scsiconf.h> 65 #include <vm/vm.h> 66 #include <vm/vm_kern.h> 67 #include <vm/vm_page.h> 68 #include <vm/pmap.h> 69 #include <machine/pmap.h> 70 #include <mvme68k/mvme68k/isr.h> 71 #include <mvme68k/dev/dmavar.h> 72 #include <mvme68k/dev/sbicreg.h> 73 #include <mvme68k/dev/sbicvar.h> 74 75 76 /* 77 * Since I can't find this in any other header files 78 */ 79 #define SCSI_PHASE(reg) (reg&0x07) 80 81 /* 82 * SCSI delays 83 * In u-seconds, primarily for state changes on the SPC. 84 */ 85 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 86 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 87 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 88 89 /* 90 * Convenience macro for waiting for a particular sbic event 91 */ 92 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 93 94 extern u_int kvtop(); 95 96 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 97 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 98 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 99 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 100 int sbiccheckdmap __P((void *, u_long, u_long)); 101 u_char sbicselectbus __P((struct sbic_softc *)); 102 int sbicxfout __P((sbic_regmap_p, int, void *)); 103 int sbicxfin __P((sbic_regmap_p, int, void *)); 104 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 105 int sbictoscsiperiod __P((struct sbic_softc *, int)); 106 int sbicintr __P((struct sbic_softc *)); 107 int sbicpoll __P((struct sbic_softc *)); 108 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 109 int sbicmsgin __P((struct sbic_softc *)); 110 int sbicabort __P((struct sbic_softc *, char *)); 111 void sbicxfdone __P((struct sbic_softc *)); 112 void sbicerror __P((struct sbic_softc *,u_char)); 113 void sbicreset __P((struct sbic_softc *)); 114 void sbic_scsidone __P((struct sbic_acb *, int)); 115 void sbic_sched __P((struct sbic_softc *)); 116 void sbic_save_ptrs __P((struct sbic_softc *)); 117 void sbic_load_ptrs __P((struct sbic_softc *)); 118 119 /* 120 * Synch xfer parameters, and timing conversions 121 */ 122 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 123 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 124 int sbic_cmd_wait = SBIC_CMD_WAIT; 125 int sbic_data_wait = SBIC_DATA_WAIT; 126 int sbic_init_wait = SBIC_INIT_WAIT; 127 128 /* 129 * was broken before.. now if you want this you get it for all drives 130 * on sbic controllers. 131 */ 132 u_char sbic_inhibit_sync[8]; 133 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 134 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 135 int sbic_parallel_operations = 1; /* Allow command queues */ 136 137 /* 138 * Some useful stuff for debugging purposes 139 */ 140 #ifdef DEBUG 141 int sbicdma_ops = 0; /* total DMA operations */ 142 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 143 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 144 int sbicdma_saves = 0; 145 146 #define QPRINTF(a) if (sbic_debug > 1) printf a 147 148 int sbic_debug = 0; /* Debug all chip related things */ 149 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 150 int reselect_debug = 0; /* Debug all reselection related things */ 151 int report_sense = 0; /* Always print Sense information */ 152 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 153 154 void sbictimeout __P((struct sbic_softc *dev)); 155 156 #else 157 #define QPRINTF(a) /* */ 158 #endif 159 160 161 /* 162 * default minphys routine for sbic based controllers 163 */ 164 void 165 sbic_minphys(bp) 166 struct buf *bp; 167 { 168 /* 169 * No max transfer at this level. 170 */ 171 minphys(bp); 172 } 173 174 175 /* 176 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 177 */ 178 void 179 sbic_save_ptrs(dev) 180 struct sbic_softc *dev; 181 { 182 sbic_regmap_p regs; 183 struct sbic_acb* acb; 184 int count, 185 asr, 186 s; 187 188 /* 189 * Only need to save pointers if DMA was active... 190 */ 191 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 192 return; 193 194 regs = dev->sc_sbicp; 195 196 s = splbio(); 197 198 /* 199 * Wait until WD chip is idle 200 */ 201 do { 202 GET_SBIC_asr(regs, asr); 203 if( asr & SBIC_ASR_DBR ) { 204 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 205 splx(s); 206 return; 207 } 208 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 209 210 211 /* 212 * Save important state. 213 * must be done before dmastop 214 */ 215 acb = dev->sc_nexus; 216 acb->sc_dmacmd = dev->sc_dmacmd; 217 218 /* 219 * Fetch the residual count 220 */ 221 SBIC_TC_GET(regs, count); 222 223 /* 224 * Shut down DMA 225 */ 226 dev->sc_dmastop(dev); 227 228 /* 229 * No longer in DMA 230 */ 231 dev->sc_flags &= ~SBICF_INDMA; 232 233 /* 234 * Ensure the WD chip is back in polled I/O mode, with nothing to 235 * transfer. 236 */ 237 SBIC_TC_PUT(regs, 0); 238 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 239 240 /* 241 * Update current count... 242 */ 243 acb->sc_tcnt = count; 244 245 /* 246 * Work out how many bytes were actually transferred 247 */ 248 count = dev->sc_tcnt - count; 249 dev->sc_tcnt = acb->sc_tcnt; 250 251 /* 252 * Fixup partial xfers 253 */ 254 acb->sc_kv.dc_addr += count; 255 acb->sc_kv.dc_count -= count; 256 acb->sc_pa.dc_addr += count; 257 acb->sc_pa.dc_count -= count >> 1; 258 259 #ifdef DEBUG 260 if ( data_pointer_debug ) 261 printf("save at (%x,%x):%x\n", 262 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 263 sbicdma_saves++; 264 #endif 265 266 splx(s); 267 } 268 269 270 /* 271 * DOES NOT RESTART DMA!!! 272 */ 273 void 274 sbic_load_ptrs(dev) 275 struct sbic_softc *dev; 276 { 277 struct sbic_acb *acb = dev->sc_nexus; 278 int s; 279 280 if ( acb->sc_kv.dc_count == 0 ) { 281 /* 282 * No data to xfer 283 */ 284 return; 285 } 286 287 s = splbio(); 288 289 /* 290 * Reset the Scatter-Gather chain 291 */ 292 dev->sc_last = dev->sc_cur = &acb->sc_pa; 293 294 /* 295 * Restore the Transfer Count and DMA specific data 296 */ 297 dev->sc_tcnt = acb->sc_tcnt; 298 dev->sc_dmacmd = acb->sc_dmacmd; 299 300 #ifdef DEBUG 301 sbicdma_ops++; 302 #endif 303 304 /* 305 * Need to fixup new segment? 306 */ 307 if ( dev->sc_tcnt == 0 ) { 308 /* 309 * sc_tcnt == 0 implies end of segment 310 */ 311 char *vaddr, *paddr; 312 int count; 313 314 /* 315 * do kvm to pa mappings 316 */ 317 vaddr = acb->sc_kv.dc_addr; 318 paddr = acb->sc_pa.dc_addr = (char *) kvtop(vaddr); 319 320 for (count = (NBPG - ((int)vaddr & PGOFSET)); 321 count < acb->sc_kv.dc_count && 322 (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 323 count += NBPG) 324 ; /* Do nothing */ 325 326 /* 327 * If it's all contiguous... 328 */ 329 if ( count > acb->sc_kv.dc_count ) { 330 count = acb->sc_kv.dc_count; 331 #ifdef DEBUG 332 sbicdma_hits++; 333 #endif 334 } 335 #ifdef DEBUG 336 else 337 sbicdma_misses++; 338 #endif 339 340 acb->sc_tcnt = count; 341 acb->sc_pa.dc_count = count >> 1; 342 343 #ifdef DEBUG 344 if ( data_pointer_debug ) 345 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", acb->sc_kv.dc_addr, 346 acb->sc_kv.dc_count, 347 acb->sc_pa.dc_addr, 348 acb->sc_tcnt); 349 #endif 350 351 } 352 353 splx(s); 354 } 355 356 /* 357 * used by specific sbic controller 358 * 359 * it appears that the higher level code does nothing with LUN's 360 * so I will too. I could plug it in, however so could they 361 * in scsi_scsi_cmd(). 362 */ 363 int 364 sbic_scsicmd(xs) 365 struct scsi_xfer *xs; 366 { 367 struct scsi_link *slp = xs->sc_link; 368 struct sbic_softc *dev = slp->adapter_softc; 369 struct sbic_acb *acb; 370 int flags = xs->flags, 371 s; 372 373 if ( flags & SCSI_DATA_UIO ) 374 panic("sbic: scsi data uio requested"); 375 376 if ( dev->sc_nexus && (flags & SCSI_POLL) ) 377 panic("sbic_scsicmd: busy"); 378 379 if ( slp->target == slp->adapter_target ) 380 return ESCAPE_NOT_SUPPORTED; 381 382 s = splbio(); 383 384 if ( (acb = dev->free_list.tqh_first) != NULL ) 385 TAILQ_REMOVE(&dev->free_list, acb, chain); 386 387 splx(s); 388 389 if ( acb == NULL ) { 390 #ifdef DEBUG 391 printf("sbic_scsicmd: unable to queue request for target %d\n", 392 slp->target); 393 #ifdef DDB 394 Debugger(); 395 #endif 396 #endif 397 xs->error = XS_DRIVER_STUFFUP; 398 399 return(TRY_AGAIN_LATER); 400 } 401 402 if ( flags & SCSI_DATA_IN ) 403 acb->flags = ACB_ACTIVE | ACB_DATAIN; 404 else 405 acb->flags = ACB_ACTIVE; 406 407 acb->xs = xs; 408 acb->clen = xs->cmdlen; 409 acb->sc_kv.dc_addr = xs->data; 410 acb->sc_kv.dc_count = xs->datalen; 411 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; 412 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 413 414 if ( flags & SCSI_POLL ) { 415 /* 416 * This has major side effects -- it locks up the machine 417 */ 418 int stat; 419 420 s = splbio(); 421 422 dev->sc_flags |= SBICF_ICMD; 423 424 do { 425 /* 426 * If we already had a nexus, while away the time until idle... 427 * This is likely only to happen if a reselection occurs between 428 * here and our earlier check for ICMD && sc_nexus (which would 429 * have resulted in a panic() had it been true). 430 */ 431 while ( dev->sc_nexus ) 432 sbicpoll(dev); 433 434 /* 435 * Fix up the new nexus 436 */ 437 dev->sc_nexus = acb; 438 dev->sc_xs = xs; 439 dev->target = slp->target; 440 dev->lun = slp->lun; 441 442 stat = sbicicmd(dev, &acb->cmd, acb->clen, 443 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 444 445 } while ( dev->sc_nexus != acb ); 446 447 sbic_scsidone(acb, stat); 448 449 splx(s); 450 451 return(COMPLETE); 452 } 453 454 s = splbio(); 455 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 456 457 /* 458 * If nothing is active, try to start it now. 459 */ 460 if ( dev->sc_nexus == NULL ) 461 sbic_sched(dev); 462 463 splx(s); 464 465 return(SUCCESSFULLY_QUEUED); 466 } 467 468 /* 469 * attempt to start the next available command 470 */ 471 void 472 sbic_sched(dev) 473 struct sbic_softc *dev; 474 { 475 struct scsi_xfer *xs; 476 struct scsi_link *slp = NULL; /* Gag the compiler */ 477 struct sbic_acb *acb; 478 int flags, 479 stat; 480 481 /* 482 * XXXSCW 483 * I'll keep this test here, even though I can't see any obvious way 484 * in which sbic_sched() could be called with sc_nexus non NULL 485 */ 486 if ( dev->sc_nexus ) 487 return; /* a command is current active */ 488 489 /* 490 * Loop through the ready list looking for work to do... 491 */ 492 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 493 int i, j; 494 495 slp = acb->xs->sc_link; 496 i = slp->target; 497 j = 1 << slp->lun; 498 499 /* 500 * We've found a potential command, but is the target/lun busy? 501 */ 502 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 503 /* 504 * Nope, it's not busy, so we can use it. 505 */ 506 dev->sc_tinfo[i].lubusy |= j; 507 TAILQ_REMOVE(&dev->ready_list, acb, chain); 508 dev->sc_nexus = acb; 509 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 510 break; 511 } 512 } 513 514 if ( acb == NULL ) { 515 QPRINTF(("sbicsched: no work\n")); 516 return; /* did not find an available command */ 517 } 518 519 #ifdef DEBUG 520 if ( data_pointer_debug > 1 ) 521 printf("sbic_sched(%d,%d)\n", slp->target, slp->lun); 522 #endif 523 524 dev->sc_xs = xs = acb->xs; 525 flags = xs->flags; 526 527 if ( flags & SCSI_RESET ) 528 sbicreset(dev); 529 530 dev->sc_stat[0] = -1; 531 dev->target = slp->target; 532 dev->lun = slp->lun; 533 534 if ( flags & SCSI_POLL || (!sbic_parallel_operations && 535 (sbicdmaok(dev, xs) == 0)) ) 536 stat = sbicicmd(dev, &acb->cmd, acb->clen, 537 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 538 else 539 if ( sbicgo(dev, xs) == 0 ) 540 return; 541 else 542 stat = dev->sc_stat[0]; 543 544 sbic_scsidone(acb, stat); 545 } 546 547 void 548 sbic_scsidone(acb, stat) 549 struct sbic_acb *acb; 550 int stat; 551 { 552 struct scsi_xfer *xs = acb->xs; 553 struct scsi_link *slp = xs->sc_link; 554 struct sbic_softc *dev = slp->adapter_softc; 555 int dosched = 0; 556 557 #ifdef DIAGNOSTIC 558 if ( acb == NULL || xs == NULL ) { 559 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", dev->target, dev->lun); 560 #ifdef DDB 561 Debugger(); 562 #endif 563 return; 564 } 565 #endif 566 567 if ( slp->device_softc && 568 ((struct device *)(slp->device_softc))->dv_unit < dk_ndrive) 569 ++dk_xfer[((struct device *)(slp->device_softc))->dv_unit]; 570 571 /* 572 * is this right? 573 */ 574 xs->status = stat; 575 576 #ifdef DEBUG 577 if ( data_pointer_debug > 1 ) 578 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", slp->target, slp->lun, 579 dev->target, dev->lun, stat); 580 581 if ( xs->sc_link->target == dev->sc_link.adapter_target ) 582 panic("target == hostid"); 583 #endif 584 585 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) == 0 ) { 586 587 if ( stat == SCSI_CHECK ) { 588 /* 589 * Schedule a REQUEST SENSE 590 */ 591 struct scsi_sense *ss = (void *)&acb->cmd; 592 593 #ifdef DEBUG 594 if ( report_sense ) 595 printf("sbic_scsidone: autosense %02x targ %d lun %d", 596 acb->cmd.opcode, slp->target, slp->lun); 597 #endif 598 599 bzero(ss, sizeof(*ss)); 600 601 ss->opcode = REQUEST_SENSE; 602 ss->byte2 = slp->lun << 5; 603 ss->length = sizeof(struct scsi_sense_data); 604 605 acb->clen = sizeof(*ss); 606 acb->sc_kv.dc_addr = (char *)&xs->sense; 607 acb->sc_kv.dc_count = sizeof(struct scsi_sense_data); 608 acb->pa_addr = (char *)kvtop(&xs->sense); /* XXX check */ 609 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 610 611 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 612 613 dev->sc_tinfo[slp->target].lubusy &= ~(1 << slp->lun); 614 dev->sc_tinfo[slp->target].senses++; 615 616 if ( dev->sc_nexus == acb ) { 617 dev->sc_nexus = NULL; 618 dev->sc_xs = NULL; 619 sbic_sched(dev); 620 } 621 return; 622 } 623 } 624 625 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) != 0 ) { 626 627 xs->error = XS_SENSE; 628 629 #ifdef DEBUG 630 if (report_sense) 631 printf(" => %02x %02x\n", xs->sense.flags, 632 xs->sense.extra_bytes[3]); 633 #endif 634 635 } else { 636 xs->resid = 0; /* XXXX */ 637 } 638 639 xs->flags |= ITSDONE; 640 641 /* 642 * Remove the ACB from whatever queue it's on. We have to do a bit of 643 * a hack to figure out which queue it's on. Note that it is *not* 644 * necessary to cdr down the ready queue, but we must cdr down the 645 * nexus queue and see if it's there, so we can mark the unit as no 646 * longer busy. This code is sickening, but it works. 647 */ 648 if ( acb == dev->sc_nexus ) { 649 650 dev->sc_nexus = NULL; 651 dev->sc_xs = NULL; 652 653 dev->sc_tinfo[slp->target].lubusy &= ~(1 << slp->lun); 654 655 if ( dev->ready_list.tqh_first ) 656 dosched = 1; /* start next command */ 657 658 } else 659 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 660 661 TAILQ_REMOVE(&dev->ready_list, acb, chain); 662 663 } else { 664 665 register struct sbic_acb *a; 666 667 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 668 if ( a == acb ) { 669 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 670 dev->sc_tinfo[slp->target].lubusy &= ~(1 << slp->lun); 671 break; 672 } 673 } 674 675 if ( a ) 676 ; 677 else if ( acb->chain.tqe_next ) { 678 TAILQ_REMOVE(&dev->ready_list, acb, chain); 679 } else { 680 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 681 #ifdef DDB 682 Debugger(); 683 #endif 684 } 685 } 686 687 /* 688 * Put it on the free list. 689 */ 690 acb->flags = ACB_FREE; 691 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 692 693 dev->sc_tinfo[slp->target].cmds++; 694 695 scsi_done(xs); 696 697 if ( dosched ) 698 sbic_sched(dev); 699 } 700 701 int 702 sbicdmaok(dev, xs) 703 struct sbic_softc *dev; 704 struct scsi_xfer *xs; 705 { 706 if ( sbic_no_dma || xs->datalen & 0x03 || (int)xs->data & 0x03) 707 return(0); 708 709 /* 710 * controller supports dma to any addresses? 711 */ 712 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 713 return(1); 714 715 /* 716 * this address is ok for dma? 717 */ 718 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 719 return(1); 720 721 return(0); 722 } 723 724 int 725 sbicwait(regs, until, timeo, line) 726 sbic_regmap_p regs; 727 u_char until; 728 int timeo; 729 int line; 730 { 731 u_char val; 732 733 if ( timeo == 0 ) 734 timeo = 1000000; /* some large value.. */ 735 736 GET_SBIC_asr(regs, val); 737 738 while ( (val & until) == 0 ) { 739 740 if ( timeo-- == 0 ) { 741 int csr; 742 GET_SBIC_csr(regs, csr); 743 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 744 #if defined(DDB) && defined(DEBUG) 745 Debugger(); 746 #endif 747 return(val); /* Maybe I should abort */ 748 break; 749 } 750 751 DELAY(1); 752 GET_SBIC_asr(regs, val); 753 } 754 755 return(val); 756 } 757 758 int 759 sbicabort(dev, where) 760 struct sbic_softc *dev; 761 char *where; 762 { 763 sbic_regmap_p regs = dev->sc_sbicp; 764 u_char csr, 765 asr; 766 767 GET_SBIC_asr(regs, asr); 768 GET_SBIC_csr(regs, csr); 769 770 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 771 dev->sc_dev.dv_xname, where, csr, asr); 772 773 /* 774 * Clean up chip itself 775 */ 776 if ( dev->sc_flags & SBICF_SELECTED ) { 777 778 while ( asr & SBIC_ASR_DBR ) { 779 /* 780 * sbic is jammed w/data. need to clear it 781 * But we don't know what direction it needs to go 782 */ 783 GET_SBIC_data(regs, asr); 784 printf("%s: abort %s: clearing data buffer 0x%02x\n", 785 dev->sc_dev.dv_xname, where, asr); 786 GET_SBIC_asr(regs, asr); 787 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 788 SET_SBIC_data(regs, asr); 789 GET_SBIC_asr(regs, asr); 790 } 791 792 WAIT_CIP(regs); 793 794 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 795 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 796 WAIT_CIP(regs); 797 798 GET_SBIC_asr(regs, asr); 799 800 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 801 /* 802 * ok, get more drastic.. 803 */ 804 printf("%s: sbicabort - asr %x, trying to reset\n", 805 dev->sc_dev.dv_xname, asr); 806 sbicreset(dev); 807 dev->sc_flags &= ~SBICF_SELECTED; 808 return SBIC_STATE_ERROR; 809 } 810 811 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 812 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 813 814 do { 815 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 816 GET_SBIC_asr(regs, asr); 817 GET_SBIC_csr (regs, csr); 818 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 819 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 820 (csr != SBIC_CSR_CMD_INVALID) ); 821 822 /* 823 * lets just hope it worked.. 824 */ 825 dev->sc_flags &= ~SBICF_SELECTED; 826 } 827 828 return SBIC_STATE_ERROR; 829 } 830 831 832 /* 833 * Initialize driver-private structures 834 */ 835 void 836 sbicinit(dev) 837 struct sbic_softc *dev; 838 { 839 u_int i; 840 841 extern u_long scsi_nosync; 842 extern int shift_nosync; 843 844 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 845 846 struct sbic_acb *acb; 847 848 TAILQ_INIT(&dev->ready_list); 849 TAILQ_INIT(&dev->nexus_list); 850 TAILQ_INIT(&dev->free_list); 851 852 dev->sc_nexus = NULL; 853 dev->sc_xs = NULL; 854 855 acb = dev->sc_acb; 856 bzero(acb, sizeof(dev->sc_acb)); 857 858 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 859 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 860 acb++; 861 } 862 863 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 864 865 #ifdef DEBUG 866 /* 867 * make sure timeout is really not needed 868 */ 869 timeout((void *)sbictimeout, dev, 30 * hz); 870 #endif 871 872 } else 873 panic("sbic: reinitializing driver!"); 874 875 dev->sc_flags |= SBICF_ALIVE; 876 dev->sc_flags &= ~SBICF_SELECTED; 877 878 /* 879 * initialize inhibit array 880 */ 881 if ( scsi_nosync ) { 882 883 u_int inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 884 885 shift_nosync += 8; 886 887 #ifdef DEBUG 888 if ( inhibit_sync ) 889 printf("%s: Inhibiting synchronous transfer %02x\n", 890 dev->sc_dev.dv_xname, inhibit_sync); 891 #endif 892 for (i = 0; i < 8; ++i) { 893 if ( inhibit_sync & (1 << i) ) 894 sbic_inhibit_sync[i] = 1; 895 } 896 } 897 898 sbicreset(dev); 899 } 900 901 void 902 sbicreset(dev) 903 struct sbic_softc *dev; 904 { 905 sbic_regmap_p regs = dev->sc_sbicp; 906 u_int my_id, 907 s; 908 u_char csr; 909 910 s = splbio(); 911 912 my_id = dev->sc_link.adapter_target & SBIC_ID_MASK; 913 914 if (dev->sc_clkfreq < 110) 915 my_id |= SBIC_ID_FS_8_10; 916 else if (dev->sc_clkfreq < 160) 917 my_id |= SBIC_ID_FS_12_15; 918 else if (dev->sc_clkfreq < 210) 919 my_id |= SBIC_ID_FS_16_20; 920 921 SET_SBIC_myid(regs, my_id); 922 923 /* 924 * Reset the chip 925 */ 926 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 927 DELAY(25); 928 929 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 930 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 931 932 /* 933 * Set up various chip parameters 934 */ 935 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 936 937 /* 938 * don't allow Selection (SBIC_RID_ES) 939 * until we can handle target mode!! 940 */ 941 SET_SBIC_rselid(regs, SBIC_RID_ER); 942 943 /* 944 * Asynchronous for now 945 */ 946 SET_SBIC_syn(regs, 0); 947 948 /* 949 * Anything else was zeroed by reset 950 */ 951 splx(s); 952 953 dev->sc_flags &= ~SBICF_SELECTED; 954 } 955 956 void 957 sbicerror(dev, csr) 958 struct sbic_softc *dev; 959 u_char csr; 960 { 961 struct scsi_xfer *xs = dev->sc_xs; 962 963 #ifdef DIAGNOSTIC 964 if ( xs == NULL ) 965 panic("sbicerror: dev->sc_xs == NULL"); 966 #endif 967 968 if ( xs->flags & SCSI_SILENT ) 969 return; 970 971 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 972 } 973 974 /* 975 * select the bus, return when selected or error. 976 * 977 * Returns the current CSR following selection and optionally MSG out phase. 978 * i.e. the returned CSR *should* indicate CMD phase... 979 * If the return value is 0, some error happened. 980 */ 981 u_char 982 sbicselectbus(dev) 983 struct sbic_softc *dev; 984 { 985 sbic_regmap_p regs = dev->sc_sbicp; 986 u_char target = dev->target, 987 lun = dev->lun, 988 asr, 989 csr, 990 id; 991 992 /* 993 * if we're already selected, return (XXXX panic maybe?) 994 */ 995 if ( dev->sc_flags & SBICF_SELECTED ) 996 return(0); 997 998 QPRINTF(("sbicselectbus %d: ", target)); 999 1000 /* 1001 * issue select 1002 */ 1003 SET_SBIC_selid(regs, target); 1004 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 1005 1006 GET_SBIC_asr(regs, asr); 1007 1008 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1009 /* 1010 * This means we got ourselves reselected upon 1011 */ 1012 QPRINTF(("WD busy (reselect?)\n")); 1013 return 0; 1014 } 1015 1016 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1017 1018 /* 1019 * wait for select (merged from seperate function may need 1020 * cleanup) 1021 */ 1022 WAIT_CIP(regs); 1023 1024 do { 1025 1026 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1027 1028 if ( asr & SBIC_ASR_LCI ) { 1029 QPRINTF(("late LCI: asr %02x\n", asr)); 1030 return 0; 1031 } 1032 1033 /* 1034 * Clear interrupt 1035 */ 1036 GET_SBIC_csr (regs, csr); 1037 1038 QPRINTF(("%02x ", csr)); 1039 1040 /* 1041 * Reselected from under our feet? 1042 */ 1043 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 1044 QPRINTF(("got reselected, asr %02x\n", asr)); 1045 /* 1046 * We need to handle this now so we don't lock up later 1047 */ 1048 sbicnextstate(dev, csr, asr); 1049 1050 return 0; 1051 } 1052 1053 /* 1054 * Whoops! 1055 */ 1056 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1057 panic("sbicselectbus: target issued select!"); 1058 return 0; 1059 } 1060 1061 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1062 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1063 csr != SBIC_CSR_SEL_TIMEO); 1064 1065 /* 1066 * Anyone at home? 1067 */ 1068 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1069 dev->sc_xs->error = XS_SELTIMEOUT; 1070 QPRINTF(("Selection Timeout\n")); 1071 return 0; 1072 } 1073 1074 QPRINTF(("Selection Complete\n")); 1075 1076 /* 1077 * Assume we're now selected 1078 */ 1079 GET_SBIC_selid(regs, id); 1080 dev->target = id; 1081 dev->lun = lun; 1082 dev->sc_flags |= SBICF_SELECTED; 1083 1084 /* 1085 * Enable (or not) reselection 1086 * XXXSCW This is probably not necessary since we don't use use the 1087 * Select-and-Xfer-with-ATN command to initiate a selection... 1088 */ 1089 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1090 SET_SBIC_rselid (regs, 0); 1091 else 1092 SET_SBIC_rselid (regs, SBIC_RID_ER); 1093 1094 /* 1095 * We only really need to do anything when the target goes to MSG out 1096 * If the device ignored ATN, it's probably old and brain-dead, 1097 * but we'll try to support it anyhow. 1098 * If it doesn't support message out, it definately doesn't 1099 * support synchronous transfers, so no point in even asking... 1100 */ 1101 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1102 /* 1103 * Send identify message (SCSI-2 requires an identify msg) 1104 */ 1105 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1106 /* 1107 * Handle drives that don't want to be asked 1108 * whether to go sync at all. 1109 */ 1110 dev->sc_sync[id].offset = 0; 1111 dev->sc_sync[id].period = sbic_min_period; 1112 dev->sc_sync[id].state = SYNC_DONE; 1113 } 1114 1115 /* 1116 * Do we need to negotiate Synchronous Xfers for this target? 1117 */ 1118 if ( dev->sc_sync[id].state != SYNC_START ) { 1119 /* 1120 * Nope, we've already negotiated. 1121 * Now see if we should allow the target to disconnect/reselect... 1122 */ 1123 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 1124 !sbic_enable_reselect ) 1125 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1126 else 1127 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1128 1129 } else { 1130 /* 1131 * try to initiate a sync transfer. 1132 * So compose the sync message we're going 1133 * to send to the target 1134 */ 1135 #ifdef DEBUG 1136 if ( sync_debug ) 1137 printf("\nSending sync request to target %d ... ", id); 1138 #endif 1139 /* 1140 * setup scsi message sync message request 1141 */ 1142 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1143 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1144 dev->sc_msg[2] = 3; 1145 dev->sc_msg[3] = MSG_SYNC_REQ; 1146 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1147 dev->sc_msg[5] = sbic_max_offset; 1148 1149 sbicxfout(regs, 6, dev->sc_msg); 1150 1151 dev->sc_sync[id].state = SYNC_SENT; 1152 #ifdef DEBUG 1153 if ( sync_debug ) 1154 printf ("sent\n"); 1155 #endif 1156 } 1157 1158 /* 1159 * There's one interrupt still to come: the change to CMD phase... 1160 */ 1161 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1162 GET_SBIC_csr(regs, csr); 1163 } 1164 1165 /* 1166 * set sync or async 1167 */ 1168 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1169 #ifdef DEBUG 1170 if ( sync_debug ) 1171 printf("select(%d): sync reg = 0x%02x\n", target, 1172 SBIC_SYN(dev->sc_sync[target].offset, 1173 dev->sc_sync[target].period)); 1174 #endif 1175 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1176 dev->sc_sync[target].period)); 1177 } else { 1178 #ifdef DEBUG 1179 if ( sync_debug ) 1180 printf("select(%d): sync reg = 0x%02x\n", target, 1181 SBIC_SYN(0,sbic_min_period)); 1182 #endif 1183 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1184 } 1185 1186 return csr; 1187 } 1188 1189 /* 1190 * Information Transfer *to* a Scsi Target. 1191 * 1192 * Note: Don't expect there to be an interrupt immediately after all 1193 * the data is transferred out. The WD spec sheet says that the Transfer- 1194 * Info command for non-MSG_IN phases only completes when the target 1195 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1196 * 1197 * This can have a nasty effect on commands which take a relatively long 1198 * time to complete, for example a START/STOP unit command may remain in 1199 * CMD phase until the disk has spun up. Only then will the target change 1200 * to STATUS phase. This is really only a problem for immediate commands 1201 * since we don't allow disconnection for them (yet). 1202 */ 1203 int 1204 sbicxfout(regs, len, bp) 1205 sbic_regmap_p regs; 1206 int len; 1207 void *bp; 1208 { 1209 int wait = sbic_data_wait; 1210 u_char asr, 1211 *buf = bp; 1212 1213 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1214 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1215 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1216 1217 /* 1218 * sigh.. WD-PROTO strikes again.. sending the command in one go 1219 * causes the chip to lock up if talking to certain (misbehaving?) 1220 * targets. Anyway, this procedure should work for all targets, but 1221 * it's slightly slower due to the overhead 1222 */ 1223 WAIT_CIP (regs); 1224 1225 SBIC_TC_PUT (regs, 0); 1226 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1227 SBIC_TC_PUT (regs, (unsigned)len); 1228 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1229 1230 /* 1231 * Loop for each byte transferred 1232 */ 1233 do { 1234 1235 GET_SBIC_asr (regs, asr); 1236 1237 if ( asr & SBIC_ASR_DBR ) { 1238 if ( len ) { 1239 SET_SBIC_data (regs, *buf); 1240 buf++; 1241 len--; 1242 } else { 1243 SET_SBIC_data (regs, 0); 1244 } 1245 wait = sbic_data_wait; 1246 } 1247 1248 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1249 1250 #ifdef DEBUG 1251 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1252 #endif 1253 1254 /* 1255 * Normally, an interrupt will be pending when this routing returns. 1256 */ 1257 return(len); 1258 } 1259 1260 /* 1261 * Information Transfer *from* a Scsi Target 1262 * returns # bytes left to read 1263 */ 1264 int 1265 sbicxfin(regs, len, bp) 1266 sbic_regmap_p regs; 1267 int len; 1268 void *bp; 1269 { 1270 int wait = sbic_data_wait; 1271 u_char *buf = bp; 1272 u_char asr; 1273 #ifdef DEBUG 1274 u_char *obp = bp; 1275 #endif 1276 1277 WAIT_CIP (regs); 1278 1279 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1280 SBIC_TC_PUT (regs, (unsigned)len); 1281 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1282 1283 /* 1284 * Loop for each byte transferred 1285 */ 1286 do { 1287 1288 GET_SBIC_asr (regs, asr); 1289 1290 if ( asr & SBIC_ASR_DBR ) { 1291 if ( len ) { 1292 GET_SBIC_data (regs, *buf); 1293 buf++; 1294 len--; 1295 } else { 1296 u_char foo; 1297 GET_SBIC_data (regs, foo); 1298 } 1299 wait = sbic_data_wait; 1300 } 1301 1302 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1303 1304 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1305 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1306 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1307 1308 SBIC_TC_PUT (regs, 0); 1309 1310 /* 1311 * this leaves with one csr to be read 1312 */ 1313 return len; 1314 } 1315 1316 /* 1317 * SCSI 'immediate' command: issue a command to some SCSI device 1318 * and get back an 'immediate' response (i.e., do programmed xfer 1319 * to get the response data). 'cbuf' is a buffer containing a scsi 1320 * command of length clen bytes. 'buf' is a buffer of length 'len' 1321 * bytes for data. The transfer direction is determined by the device 1322 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1323 * command must supply no data. 1324 * 1325 * Note that although this routine looks like it can handle disconnect/ 1326 * reselect, the fact is that it can't. There is still some work to be 1327 * done to clean this lot up. 1328 */ 1329 int 1330 sbicicmd(dev, cbuf, clen, buf, len) 1331 struct sbic_softc *dev; 1332 void *cbuf, 1333 *buf; 1334 int clen, 1335 len; 1336 { 1337 sbic_regmap_p regs = dev->sc_sbicp; 1338 struct sbic_acb *acb = dev->sc_nexus; 1339 u_char csr, 1340 asr; 1341 int still_busy = SBIC_STATE_RUNNING; 1342 #ifdef DEBUG 1343 int counter = 0; 1344 #endif 1345 1346 /* 1347 * Make sure pointers are OK 1348 */ 1349 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1350 dev->sc_tcnt = acb->sc_tcnt = 0; 1351 1352 acb->sc_dmacmd = 0; 1353 acb->sc_pa.dc_count = 0; /* No DMA */ 1354 acb->sc_kv.dc_addr = buf; 1355 acb->sc_kv.dc_count = len; 1356 1357 #ifdef DEBUG 1358 if ( data_pointer_debug > 1 ) 1359 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1360 #endif 1361 1362 /* 1363 * set the sbic into non-DMA mode 1364 */ 1365 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1366 1367 dev->sc_stat[0] = 0xff; 1368 dev->sc_msg[0] = 0xff; 1369 1370 /* 1371 * We're stealing the SCSI bus 1372 */ 1373 dev->sc_flags |= SBICF_ICMD; 1374 1375 do { 1376 GET_SBIC_asr (regs, asr); 1377 1378 /* 1379 * select the SCSI bus (it's an error if bus isn't free) 1380 */ 1381 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1382 still_busy != SBIC_STATE_DISCONNECT ) { 1383 if ( (csr = sbicselectbus(dev)) == 0 ) { 1384 dev->sc_flags &= ~SBICF_ICMD; 1385 return(-1); 1386 } 1387 } else 1388 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1389 GET_SBIC_csr(regs, csr); 1390 else 1391 csr = 0; 1392 1393 if ( csr ) { 1394 1395 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1396 1397 switch ( csr ) { 1398 1399 case SBIC_CSR_S_XFERRED: 1400 case SBIC_CSR_DISC: 1401 case SBIC_CSR_DISC_1: 1402 { 1403 u_char phase; 1404 1405 dev->sc_flags &= ~SBICF_SELECTED; 1406 GET_SBIC_cmd_phase (regs, phase); 1407 1408 if ( phase == 0x60 ) { 1409 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1410 still_busy = SBIC_STATE_DONE; /* done */ 1411 } else { 1412 #ifdef DEBUG 1413 if ( reselect_debug > 1 ) 1414 printf("sbicicmd: handling disconnect\n"); 1415 #endif 1416 still_busy = SBIC_STATE_DISCONNECT; 1417 } 1418 } 1419 break; 1420 1421 case SBIC_CSR_XFERRED | CMD_PHASE: 1422 case SBIC_CSR_MIS | CMD_PHASE: 1423 case SBIC_CSR_MIS_1 | CMD_PHASE: 1424 case SBIC_CSR_MIS_2 | CMD_PHASE: 1425 { 1426 if ( sbicxfout(regs, clen, cbuf) ) 1427 still_busy = sbicabort(dev, "icmd sending cmd"); 1428 } 1429 break; 1430 1431 case SBIC_CSR_XFERRED | STATUS_PHASE: 1432 case SBIC_CSR_MIS | STATUS_PHASE: 1433 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1434 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1435 { 1436 /* 1437 * The sbic does the status/cmd-complete reading ok, 1438 * so do this with its hi-level commands. 1439 */ 1440 #ifdef DEBUG 1441 if ( sbic_debug ) 1442 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1443 #endif 1444 SET_SBIC_cmd_phase(regs, 0x46); 1445 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1446 } 1447 break; 1448 1449 default: 1450 { 1451 still_busy = sbicnextstate(dev, csr, asr); 1452 } 1453 break; 1454 } 1455 1456 /* 1457 * make sure the last command was taken, 1458 * ie. we're not hunting after an ignored command.. 1459 */ 1460 GET_SBIC_asr(regs, asr); 1461 1462 /* 1463 * tapes may take a loooong time.. 1464 */ 1465 while (asr & SBIC_ASR_BSY ) { 1466 1467 if ( asr & SBIC_ASR_DBR ) { 1468 int i; 1469 1470 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1471 #ifdef DDB 1472 Debugger(); 1473 #endif 1474 /* 1475 * SBIC is jammed 1476 * DUNNO which direction 1477 * Try old direction 1478 */ 1479 GET_SBIC_data(regs, i); 1480 GET_SBIC_asr(regs, asr); 1481 1482 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1483 SET_SBIC_data(regs, i); 1484 } 1485 1486 GET_SBIC_asr(regs, asr); 1487 } 1488 } 1489 1490 /* 1491 * wait for last command to complete 1492 */ 1493 if ( asr & SBIC_ASR_LCI ) { 1494 printf("sbicicmd: last command ignored\n"); 1495 } 1496 else 1497 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1498 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1499 1500 /* 1501 * do it again 1502 */ 1503 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1504 1505 /* 1506 * Sometimes we need to do an extra read of the CSR 1507 */ 1508 GET_SBIC_csr(regs, csr); 1509 1510 #ifdef DEBUG 1511 if ( data_pointer_debug > 1 ) 1512 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1513 acb->sc_kv.dc_count, 1514 dev->sc_stat[0]); 1515 #endif 1516 1517 dev->sc_flags &= ~SBICF_ICMD; 1518 1519 return(dev->sc_stat[0]); 1520 } 1521 1522 /* 1523 * Finish SCSI xfer command: After the completion interrupt from 1524 * a read/write operation, sequence through the final phases in 1525 * programmed i/o. This routine is a lot like sbicicmd except we 1526 * skip (and don't allow) the select, cmd out and data in/out phases. 1527 */ 1528 void 1529 sbicxfdone(dev) 1530 struct sbic_softc *dev; 1531 { 1532 sbic_regmap_p regs = dev->sc_sbicp; 1533 u_char phase, 1534 csr; 1535 int s; 1536 1537 QPRINTF(("{")); 1538 s = splbio(); 1539 1540 /* 1541 * have the sbic complete on its own 1542 */ 1543 SBIC_TC_PUT(regs, 0); 1544 SET_SBIC_cmd_phase(regs, 0x46); 1545 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1546 1547 do { 1548 1549 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1550 GET_SBIC_csr (regs, csr); 1551 QPRINTF(("%02x:", csr)); 1552 1553 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1554 (csr != SBIC_CSR_S_XFERRED)); 1555 1556 dev->sc_flags &= ~SBICF_SELECTED; 1557 1558 GET_SBIC_cmd_phase (regs, phase); 1559 QPRINTF(("}%02x", phase)); 1560 1561 if ( phase == 0x60 ) 1562 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1563 else 1564 sbicerror(dev, csr); 1565 1566 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1567 1568 splx(s); 1569 } 1570 1571 /* 1572 * No DMA chains 1573 */ 1574 int 1575 sbicgo(dev, xs) 1576 struct sbic_softc *dev; 1577 struct scsi_xfer *xs; 1578 { 1579 struct sbic_acb *acb = dev->sc_nexus; 1580 sbic_regmap_p regs = dev->sc_sbicp; 1581 int i, 1582 dmaflags, 1583 count, 1584 usedma; 1585 u_char csr, 1586 asr, 1587 *addr; 1588 1589 dev->target = xs->sc_link->target; 1590 dev->lun = xs->sc_link->lun; 1591 1592 usedma = sbicdmaok(dev, xs); 1593 1594 #ifdef DEBUG 1595 if ( data_pointer_debug > 1 ) 1596 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1597 #endif 1598 1599 /* 1600 * select the SCSI bus (it's an error if bus isn't free) 1601 */ 1602 if ( (csr = sbicselectbus(dev)) == 0 ) 1603 return(0); /* Not done: needs to be rescheduled */ 1604 1605 dev->sc_stat[0] = 0xff; 1606 1607 /* 1608 * Calculate DMA chains now 1609 */ 1610 if ( acb->flags & ACB_DATAIN ) 1611 dmaflags = DMAGO_READ; 1612 else 1613 dmaflags = 0; 1614 1615 addr = acb->sc_kv.dc_addr; 1616 count = acb->sc_kv.dc_count; 1617 1618 if ( count && ((char *)kvtop(addr) != acb->sc_pa.dc_addr) ) { 1619 printf("sbic: DMA buffer mapping changed %x->%x\n", 1620 acb->sc_pa.dc_addr, kvtop(addr)); 1621 #ifdef DDB 1622 Debugger(); 1623 #endif 1624 } 1625 1626 #ifdef DEBUG 1627 ++sbicdma_ops; /* count total DMA operations */ 1628 #endif 1629 1630 /* 1631 * Allocate the DMA chain 1632 * Mark end of segment... 1633 */ 1634 acb->sc_tcnt = dev->sc_tcnt = 0; 1635 acb->sc_pa.dc_count = 0; 1636 1637 sbic_load_ptrs(dev); 1638 1639 /* 1640 * Enable interrupts but don't do any DMA 1641 * enintr() also enables interrupts for the sbic 1642 */ 1643 dev->sc_enintr(dev); 1644 1645 if ( usedma ) { 1646 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1647 acb->sc_pa.dc_count, dmaflags); 1648 #ifdef DEBUG 1649 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1650 #endif 1651 } else 1652 dev->sc_dmacmd = 0; /* Don't use DMA */ 1653 1654 acb->sc_dmacmd = dev->sc_dmacmd; 1655 1656 #ifdef DEBUG 1657 if ( data_pointer_debug > 1 ) { 1658 printf("sbicgo dmago:%d(%x:%x) dmacmd=0x%02x\n", dev->target, 1659 dev->sc_cur->dc_addr, 1660 dev->sc_tcnt, 1661 dev->sc_dmacmd); 1662 } 1663 #endif 1664 1665 /* 1666 * Lets cycle a while then let the interrupt handler take over. 1667 */ 1668 GET_SBIC_asr(regs, asr); 1669 1670 do { 1671 1672 QPRINTF(("go ")); 1673 1674 /* 1675 * Handle the new phase 1676 */ 1677 i = sbicnextstate(dev, csr, asr); 1678 #if 0 1679 WAIT_CIP(regs); 1680 #endif 1681 if ( i == SBIC_STATE_RUNNING ) { 1682 GET_SBIC_asr(regs, asr); 1683 1684 if ( asr & SBIC_ASR_LCI ) 1685 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1686 1687 if ( asr & SBIC_ASR_INT ) 1688 GET_SBIC_csr(regs, csr); 1689 } 1690 1691 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1692 1693 if ( i == SBIC_STATE_DONE ) { 1694 if ( dev->sc_stat[0] == 0xff ) 1695 #if 0 1696 printf("sbicgo: done & stat = 0xff\n"); 1697 #else 1698 ; 1699 #endif 1700 else 1701 return 1; /* Did we really finish that fast? */ 1702 } 1703 1704 return 0; 1705 } 1706 1707 1708 int 1709 sbicintr(dev) 1710 struct sbic_softc *dev; 1711 { 1712 sbic_regmap_p regs = dev->sc_sbicp; 1713 u_char asr, 1714 csr; 1715 int i; 1716 1717 /* 1718 * pending interrupt? 1719 */ 1720 GET_SBIC_asr (regs, asr); 1721 if ( (asr & SBIC_ASR_INT) == 0 ) 1722 return(0); 1723 1724 GET_SBIC_csr(regs, csr); 1725 1726 do { 1727 1728 QPRINTF(("intr[0x%x]", csr)); 1729 1730 i = sbicnextstate(dev, csr, asr); 1731 #if 0 1732 WAIT_CIP(regs); 1733 #endif 1734 if ( i == SBIC_STATE_RUNNING ) { 1735 GET_SBIC_asr(regs, asr); 1736 1737 if ( asr & SBIC_ASR_LCI ) 1738 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1739 1740 if ( asr & SBIC_ASR_INT ) 1741 GET_SBIC_csr(regs, csr); 1742 } 1743 1744 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1745 1746 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1747 1748 return(1); 1749 } 1750 1751 /* 1752 * Run commands and wait for disconnect. 1753 * This is only ever called when a command is in progress, when we 1754 * want to busy wait for it to finish. 1755 */ 1756 int 1757 sbicpoll(dev) 1758 struct sbic_softc *dev; 1759 { 1760 sbic_regmap_p regs = dev->sc_sbicp; 1761 u_char asr, 1762 csr; 1763 int i; 1764 1765 /* 1766 * Wait for the next interrupt 1767 */ 1768 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1769 1770 do { 1771 GET_SBIC_asr (regs, asr); 1772 1773 if ( asr & SBIC_ASR_INT ) 1774 GET_SBIC_csr(regs, csr); 1775 1776 QPRINTF(("poll[0x%x]", csr)); 1777 1778 /* 1779 * Handle it 1780 */ 1781 i = sbicnextstate(dev, csr, asr); 1782 1783 WAIT_CIP(regs); 1784 GET_SBIC_asr(regs, asr); 1785 1786 /* 1787 * tapes may take a loooong time.. 1788 */ 1789 while ( asr & SBIC_ASR_BSY ) { 1790 u_char z = 0; 1791 1792 if ( asr & SBIC_ASR_DBR ) { 1793 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1794 #ifdef DDB 1795 Debugger(); 1796 #endif 1797 /* 1798 * SBIC is jammed 1799 * DUNNO which direction 1800 * Try old direction 1801 */ 1802 GET_SBIC_data(regs, z); 1803 GET_SBIC_asr(regs, asr); 1804 1805 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1806 SET_SBIC_data(regs, z); 1807 } 1808 1809 GET_SBIC_asr(regs, asr); 1810 } 1811 1812 if ( asr & SBIC_ASR_LCI ) 1813 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1814 else 1815 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1816 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1817 1818 } while ( i == SBIC_STATE_RUNNING ); 1819 1820 return(1); 1821 } 1822 1823 /* 1824 * Handle a single msgin 1825 */ 1826 int 1827 sbicmsgin(dev) 1828 struct sbic_softc *dev; 1829 { 1830 sbic_regmap_p regs = dev->sc_sbicp; 1831 int recvlen = 1; 1832 u_char asr, 1833 csr, 1834 *tmpaddr, 1835 *msgaddr; 1836 1837 tmpaddr = msgaddr = dev->sc_msg; 1838 1839 tmpaddr[0] = 0xff; 1840 tmpaddr[1] = 0xff; 1841 1842 GET_SBIC_asr(regs, asr); 1843 1844 #ifdef DEBUG 1845 if ( reselect_debug > 1 ) 1846 printf("sbicmsgin asr=%02x\n", asr); 1847 #endif 1848 1849 GET_SBIC_selid (regs, csr); 1850 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1851 1852 SBIC_TC_PUT(regs, 0); 1853 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1854 1855 do { 1856 while( recvlen-- ) { 1857 1858 /* 1859 * Fetch the next byte of the message 1860 */ 1861 RECV_BYTE(regs, *tmpaddr); 1862 1863 /* 1864 * get the command completion interrupt, or we 1865 * can't send a new command (LCI) 1866 */ 1867 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1868 GET_SBIC_csr(regs, csr); 1869 1870 #ifdef DEBUG 1871 if ( reselect_debug > 1 ) 1872 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1873 #endif 1874 1875 tmpaddr++; 1876 1877 if ( recvlen ) { 1878 /* 1879 * Clear ACK, and wait for the interrupt for the next byte 1880 */ 1881 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1882 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1883 GET_SBIC_csr(regs, csr); 1884 } 1885 } 1886 1887 if ( msgaddr[0] == 0xff ) { 1888 printf("sbicmsgin: sbic swallowed our message\n"); 1889 break; 1890 } 1891 1892 #ifdef DEBUG 1893 if ( sync_debug ) { 1894 GET_SBIC_asr(regs, asr); 1895 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1896 } 1897 #endif 1898 /* 1899 * test whether this is a reply to our sync 1900 * request 1901 */ 1902 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1903 1904 /* 1905 * Got IFFY msg -- ack it 1906 */ 1907 QPRINTF(("IFFY")); 1908 1909 } else 1910 if ( msgaddr[0] == MSG_REJECT && 1911 dev->sc_sync[dev->target].state == SYNC_SENT) { 1912 1913 /* 1914 * Target probably rejected our Sync negotiation. 1915 */ 1916 QPRINTF(("REJECT of SYN")); 1917 1918 #ifdef DEBUG 1919 if ( sync_debug ) 1920 printf("target %d rejected sync, going async\n", dev->target); 1921 #endif 1922 1923 dev->sc_sync[dev->target].period = sbic_min_period; 1924 dev->sc_sync[dev->target].offset = 0; 1925 dev->sc_sync[dev->target].state = SYNC_DONE; 1926 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1927 dev->sc_sync[dev->target].period)); 1928 1929 } else 1930 if ( msgaddr[0] == MSG_REJECT ) { 1931 1932 /* 1933 * we'll never REJECt a REJECT message.. 1934 */ 1935 QPRINTF(("REJECT")); 1936 1937 } else 1938 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1939 1940 /* 1941 * don't reject this either. 1942 */ 1943 QPRINTF(("MSG_SAVE_DATA_PTR")); 1944 1945 } else 1946 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1947 1948 /* 1949 * don't reject this either. 1950 */ 1951 QPRINTF(("MSG_RESTORE_PTR")); 1952 1953 } else 1954 if ( msgaddr[0] == MSG_DISCONNECT ) { 1955 1956 /* 1957 * Target is disconnecting... 1958 */ 1959 QPRINTF(("DISCONNECT")); 1960 1961 #ifdef DEBUG 1962 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1963 printf("sbicmsgin: got disconnect msg %s\n", 1964 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1965 #endif 1966 1967 if ( dev->sc_flags & SBICF_ICMD ) { 1968 /* 1969 * We're in immediate mode. Prevent disconnects. 1970 * prepare to reject the message, NACK 1971 */ 1972 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1973 WAIT_CIP(regs); 1974 } 1975 1976 } else 1977 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1978 1979 /* 1980 * !! KLUDGE ALERT !! quite a few drives don't seem to 1981 * really like the current way of sending the 1982 * sync-handshake together with the ident-message, and 1983 * they react by sending command-complete and 1984 * disconnecting right after returning the valid sync 1985 * handshake. So, all I can do is reselect the drive, 1986 * and hope it won't disconnect again. I don't think 1987 * this is valid behavior, but I can't help fixing a 1988 * problem that apparently exists. 1989 * 1990 * Note: we should not get here on `normal' command 1991 * completion, as that condition is handled by the 1992 * high-level sel&xfer resume command used to walk 1993 * thru status/cc-phase. 1994 */ 1995 QPRINTF(("CMD_COMPLETE")); 1996 1997 #ifdef DEBUG 1998 if ( sync_debug ) 1999 printf ("GOT MSG %d! target %d acting weird.." 2000 " waiting for disconnect...\n", msgaddr[0], dev->target); 2001 #endif 2002 2003 /* 2004 * Check to see if sbic is handling this 2005 */ 2006 GET_SBIC_asr(regs, asr); 2007 2008 /* 2009 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 2010 */ 2011 if ( asr & SBIC_ASR_BSY ) 2012 return SBIC_STATE_RUNNING; 2013 2014 /* 2015 * Let's try this: Assume it works and set status to 00 2016 */ 2017 dev->sc_stat[0] = 0; 2018 2019 } else 2020 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 2021 2022 /* 2023 * Target is sending us an extended message. We'll assume it's 2024 * the response to our Sync. negotiation. 2025 */ 2026 QPRINTF(("ExtMSG\n")); 2027 2028 /* 2029 * Read in whole extended message. First, negate ACK to accept 2030 * the MSG_EXT_MESSAGE byte... 2031 */ 2032 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2033 2034 /* 2035 * Wait for the interrupt for the next byte (length) 2036 */ 2037 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2038 GET_SBIC_csr(regs, csr); 2039 2040 #ifdef DEBUG 2041 QPRINTF(("CLR ACK csr %02x\n", csr)); 2042 #endif 2043 2044 /* 2045 * Read the length byte 2046 */ 2047 RECV_BYTE(regs, *tmpaddr); 2048 2049 /* 2050 * Wait for command completion IRQ 2051 */ 2052 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2053 GET_SBIC_csr(regs, csr); 2054 2055 /* 2056 * Reload the loop counter 2057 */ 2058 recvlen = *tmpaddr++; 2059 2060 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2061 2062 } else 2063 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2064 msgaddr[2] == MSG_SYNC_REQ ) { 2065 2066 /* 2067 * We've received the complete Extended Message Sync. Request... 2068 */ 2069 QPRINTF(("SYN")); 2070 2071 /* 2072 * Compute the required Transfer Period for the WD chip... 2073 */ 2074 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2075 dev->sc_sync[dev->target].offset = msgaddr[4]; 2076 dev->sc_sync[dev->target].state = SYNC_DONE; 2077 2078 /* 2079 * Put the WD chip in synchronous mode 2080 */ 2081 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2082 dev->sc_sync[dev->target].period)); 2083 #ifdef DEBUG 2084 if ( sync_debug ) 2085 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2086 SBIC_SYN(dev->sc_sync[dev->target].offset, 2087 dev->sc_sync[dev->target].period)); 2088 #endif 2089 2090 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2091 dev->sc_dev.dv_xname, dev->target, 2092 msgaddr[3] * 4, msgaddr[4]); 2093 2094 } else { 2095 2096 /* 2097 * We don't support whatever this message is... 2098 */ 2099 #ifdef DEBUG 2100 if ( sbic_debug || sync_debug ) 2101 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2102 #endif 2103 2104 /* 2105 * prepare to reject the message, NACK 2106 */ 2107 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2108 WAIT_CIP(regs); 2109 } 2110 2111 /* 2112 * Negate ACK to complete the transfer 2113 */ 2114 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2115 2116 /* 2117 * Wait for the interrupt for the next byte, or phase change. 2118 * Only read the CSR if we have more data to transfer. 2119 * XXXSCW: We should really verify that we're still in MSG IN phase 2120 * before blindly going back around this loop, but that would mean 2121 * we read the CSR... <sigh> 2122 */ 2123 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2124 if ( recvlen > 0 ) 2125 GET_SBIC_csr(regs, csr); 2126 2127 } while ( recvlen > 0 ); 2128 2129 /* 2130 * Should still have one CSR to read 2131 */ 2132 return SBIC_STATE_RUNNING; 2133 } 2134 2135 2136 /* 2137 * sbicnextstate() 2138 * return: 2139 * SBIC_STATE_DONE == done 2140 * SBIC_STATE_RUNNING == working 2141 * SBIC_STATE_DISCONNECT == disconnected 2142 * SBIC_STATE_ERROR == error 2143 */ 2144 int 2145 sbicnextstate(dev, csr, asr) 2146 struct sbic_softc *dev; 2147 u_char csr, 2148 asr; 2149 { 2150 sbic_regmap_p regs = dev->sc_sbicp; 2151 struct sbic_acb *acb = dev->sc_nexus; 2152 2153 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2154 2155 switch (csr) { 2156 2157 case SBIC_CSR_XFERRED | CMD_PHASE: 2158 case SBIC_CSR_MIS | CMD_PHASE: 2159 case SBIC_CSR_MIS_1 | CMD_PHASE: 2160 case SBIC_CSR_MIS_2 | CMD_PHASE: 2161 { 2162 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2163 goto abort; 2164 } 2165 break; 2166 2167 case SBIC_CSR_XFERRED | STATUS_PHASE: 2168 case SBIC_CSR_MIS | STATUS_PHASE: 2169 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2170 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2171 { 2172 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2173 2174 /* 2175 * this should be the normal i/o completion case. 2176 * get the status & cmd complete msg then let the 2177 * device driver look at what happened. 2178 */ 2179 sbicxfdone(dev); 2180 2181 #ifdef DEBUG 2182 dev->sc_dmatimo = 0; 2183 if ( data_pointer_debug > 1 ) 2184 printf("next dmastop: %d(%x:%x)\n", dev->target, 2185 dev->sc_cur->dc_addr, 2186 dev->sc_tcnt); 2187 #endif 2188 /* 2189 * Stop the DMA chip 2190 */ 2191 dev->sc_dmastop(dev); 2192 2193 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2194 2195 /* 2196 * Indicate to the upper layers that the command is done 2197 */ 2198 sbic_scsidone(acb, dev->sc_stat[0]); 2199 2200 return SBIC_STATE_DONE; 2201 } 2202 2203 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2204 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2205 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2206 case SBIC_CSR_MIS | DATA_IN_PHASE: 2207 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2208 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2209 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2210 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2211 { 2212 /* 2213 * Verify that we expected to transfer data... 2214 */ 2215 if ( acb->sc_kv.dc_count <= 0 ) { 2216 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2217 acb->sc_kv.dc_count, asr, csr); 2218 goto abort; 2219 } 2220 2221 /* 2222 * Should we transfer using PIO or DMA ? 2223 */ 2224 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2225 acb->sc_dmacmd == 0 ) { 2226 2227 /* 2228 * Do PIO transfer 2229 */ 2230 int i; 2231 2232 #ifdef DEBUG 2233 if ( data_pointer_debug > 1 ) 2234 printf("next PIO: %d(%x:%x)\n", dev->target, 2235 acb->sc_kv.dc_addr, 2236 acb->sc_kv.dc_count); 2237 #endif 2238 2239 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2240 /* 2241 * data in 2242 */ 2243 i = sbicxfin(regs, acb->sc_kv.dc_count, 2244 acb->sc_kv.dc_addr); 2245 else 2246 /* 2247 * data out 2248 */ 2249 i = sbicxfout(regs, acb->sc_kv.dc_count, 2250 acb->sc_kv.dc_addr); 2251 2252 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2253 acb->sc_kv.dc_count = i; 2254 2255 /* 2256 * Update current count... 2257 */ 2258 acb->sc_tcnt = dev->sc_tcnt = i; 2259 2260 dev->sc_flags &= ~SBICF_INDMA; 2261 2262 } else { 2263 2264 /* 2265 * Do DMA transfer 2266 * set next dma addr and dec count 2267 */ 2268 sbic_save_ptrs(dev); 2269 sbic_load_ptrs(dev); 2270 2271 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2272 SBIC_MACHINE_DMA_MODE); 2273 2274 #ifdef DEBUG 2275 dev->sc_dmatimo = 1; 2276 if ( data_pointer_debug > 1 ) 2277 printf("next DMA: %d(%x:%x)\n", dev->target, 2278 dev->sc_cur->dc_addr, 2279 dev->sc_tcnt); 2280 #endif 2281 /* 2282 * Start the DMA chip going 2283 */ 2284 dev->sc_tcnt = dev->sc_dmanext(dev); 2285 2286 /* 2287 * Tell the WD chip how much to transfer this time around 2288 */ 2289 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2290 2291 /* 2292 * Start the transfer 2293 */ 2294 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2295 2296 /* 2297 * Indicate that we're in DMA mode 2298 */ 2299 dev->sc_flags |= SBICF_INDMA; 2300 } 2301 } 2302 break; 2303 2304 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2305 case SBIC_CSR_MIS | MESG_IN_PHASE: 2306 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2307 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2308 { 2309 sbic_save_ptrs(dev); 2310 2311 /* 2312 * Handle a single message in... 2313 */ 2314 return sbicmsgin(dev); 2315 } 2316 2317 case SBIC_CSR_MSGIN_W_ACK: 2318 { 2319 /* 2320 * We should never see this since it's handled in 'sbicmsgin()' 2321 * but just for the sake of paranoia... 2322 */ 2323 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2324 printf("Acking unknown msgin CSR:%02x",csr); 2325 } 2326 break; 2327 2328 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2329 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2330 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2331 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2332 { 2333 /* 2334 * We only ever handle a message out phase here for sending a 2335 * REJECT message. 2336 */ 2337 sbic_save_ptrs(dev); 2338 2339 #ifdef DEBUG 2340 if (sync_debug) 2341 printf ("sending REJECT msg to last msg.\n"); 2342 #endif 2343 2344 SEND_BYTE(regs, MSG_REJECT); 2345 WAIT_CIP(regs); 2346 } 2347 break; 2348 2349 case SBIC_CSR_DISC: 2350 case SBIC_CSR_DISC_1: 2351 { 2352 /* 2353 * Try to schedule another target 2354 */ 2355 sbic_save_ptrs(dev); 2356 2357 dev->sc_flags &= ~SBICF_SELECTED; 2358 2359 #ifdef DEBUG 2360 if ( reselect_debug > 1 ) 2361 printf("sbicnext target %d disconnected\n", dev->target); 2362 #endif 2363 2364 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2365 2366 ++dev->sc_tinfo[dev->target].dconns; 2367 2368 dev->sc_nexus = NULL; 2369 dev->sc_xs = NULL; 2370 2371 if ( acb->xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2372 !sbic_parallel_operations ) 2373 return SBIC_STATE_DISCONNECT; 2374 2375 QPRINTF(("sbicnext: calling sbic_sched\n")); 2376 2377 sbic_sched(dev); 2378 2379 QPRINTF(("sbicnext: sbic_sched returned\n")); 2380 2381 return SBIC_STATE_DISCONNECT; 2382 } 2383 2384 case SBIC_CSR_RSLT_NI: 2385 case SBIC_CSR_RSLT_IFY: 2386 { 2387 /* 2388 * A reselection. 2389 * Note that since we don't enable Advanced Features (assuming 2390 * the WD chip is at least the 'A' revision), we're only ever 2391 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2392 * hell of it, we'll handle it anyway, for all the extra code 2393 * it needs... 2394 */ 2395 u_char newtarget, 2396 newlun; 2397 2398 GET_SBIC_rselid(regs, newtarget); 2399 2400 /* 2401 * check SBIC_RID_SIV? 2402 */ 2403 newtarget &= SBIC_RID_MASK; 2404 2405 if ( csr == SBIC_CSR_RSLT_IFY ) { 2406 2407 /* 2408 * Read Identify msg to avoid lockup 2409 */ 2410 GET_SBIC_data(regs, newlun); 2411 WAIT_CIP(regs); 2412 newlun &= SBIC_TLUN_MASK; 2413 2414 } else { 2415 2416 /* 2417 * Need to read Identify message the hard way, assuming 2418 * the target even sends us one... 2419 */ 2420 for (newlun = 255; newlun; --newlun) { 2421 GET_SBIC_asr(regs, asr); 2422 if (asr & SBIC_ASR_INT) 2423 break; 2424 delay(10); 2425 } 2426 2427 /* 2428 * If we didn't get an interrupt, somethink's up 2429 */ 2430 if ( (asr & SBIC_ASR_INT) == 0 ) { 2431 printf("%s: Reselect without identify? asr %x\n", 2432 dev->sc_dev.dv_xname, asr); 2433 newlun = 0; /* XXXX */ 2434 } else { 2435 /* 2436 * We got an interrupt, verify that it's a change to 2437 * message in phase, and if so read the message. 2438 */ 2439 GET_SBIC_csr(regs,csr); 2440 2441 if ( csr == SBIC_CSR_MIS | MESG_IN_PHASE || 2442 csr == SBIC_CSR_MIS_1 | MESG_IN_PHASE || 2443 csr == SBIC_CSR_MIS_2 | MESG_IN_PHASE ) { 2444 /* 2445 * Yup, gone to message in. Fetch the target LUN 2446 */ 2447 sbicmsgin(dev); 2448 newlun = dev->sc_msg[0] & 0x07; 2449 2450 } else { 2451 /* 2452 * Whoops! Target didn't go to message in phase!! 2453 */ 2454 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2455 newlun = 0; /* XXXSCW */ 2456 } 2457 } 2458 } 2459 2460 /* 2461 * Ok, we have the identity of the reselecting target. 2462 */ 2463 #ifdef DEBUG 2464 if ( reselect_debug > 1 || 2465 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2466 printf("sbicnext: reselect %s from targ %d lun %d\n", 2467 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2468 } 2469 #endif 2470 2471 if ( dev->sc_nexus ) { 2472 /* 2473 * Whoops! We've been reselected with an command in progress! 2474 * The best we can do is to put the current command back on the 2475 * ready list and hope for the best. 2476 */ 2477 #ifdef DEBUG 2478 if ( reselect_debug > 1 ) { 2479 printf("%s: reselect %s with active command\n", 2480 dev->sc_dev.dv_xname, 2481 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2482 } 2483 #endif 2484 2485 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2486 2487 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2488 2489 dev->sc_nexus = NULL; 2490 dev->sc_xs = NULL; 2491 } 2492 2493 /* 2494 * Reload sync values for this target 2495 */ 2496 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2497 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2498 dev->sc_sync[newtarget].period)); 2499 else 2500 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2501 2502 /* 2503 * Loop through the nexus list until we find the saved entry 2504 * for the reselecting target... 2505 */ 2506 for (acb = dev->nexus_list.tqh_first; acb; 2507 acb = acb->chain.tqe_next) { 2508 2509 if ( acb->xs->sc_link->target == newtarget && 2510 acb->xs->sc_link->lun == newlun) { 2511 /* 2512 * We've found the saved entry. Dequeue it, and 2513 * make it current again. 2514 */ 2515 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2516 2517 dev->sc_nexus = acb; 2518 dev->sc_xs = acb->xs; 2519 dev->sc_flags |= SBICF_SELECTED; 2520 dev->target = newtarget; 2521 dev->lun = newlun; 2522 break; 2523 } 2524 } 2525 2526 if ( acb == NULL ) { 2527 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2528 dev->sc_dev.dv_xname, 2529 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2530 &dev->nexus_list.tqh_first); 2531 panic("bad reselect in sbic"); 2532 } 2533 2534 if ( csr == SBIC_CSR_RSLT_IFY ) 2535 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2536 } 2537 break; 2538 2539 default: 2540 abort: 2541 { 2542 /* 2543 * Something unexpected happened -- deal with it. 2544 */ 2545 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2546 2547 #ifdef DDB 2548 Debugger(); 2549 #endif 2550 2551 #ifdef DEBUG 2552 dev->sc_dmatimo = 0; 2553 if ( data_pointer_debug > 1 ) 2554 printf("next dmastop: %d(%x:%x)\n", dev->target, 2555 dev->sc_cur->dc_addr, 2556 dev->sc_tcnt); 2557 #endif 2558 2559 dev->sc_dmastop(dev); 2560 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2561 if ( dev->sc_xs ) sbicerror(dev, csr); 2562 sbicabort(dev, "next"); 2563 2564 if ( dev->sc_flags & SBICF_INDMA ) { 2565 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2566 2567 #ifdef DEBUG 2568 dev->sc_dmatimo = 0; 2569 if ( data_pointer_debug > 1 ) 2570 printf("next dmastop: %d(%x:%x)\n", dev->target, 2571 dev->sc_cur->dc_addr, 2572 dev->sc_tcnt); 2573 #endif 2574 sbic_scsidone(acb, -1); 2575 } 2576 2577 return SBIC_STATE_ERROR; 2578 } 2579 } 2580 2581 return(SBIC_STATE_RUNNING); 2582 } 2583 2584 2585 /* 2586 * Check if DMA can not be used with specified buffer 2587 */ 2588 int 2589 sbiccheckdmap(bp, len, mask) 2590 void *bp; 2591 u_long len, 2592 mask; 2593 { 2594 u_char *buffer; 2595 u_long phy_buf; 2596 u_long phy_len; 2597 2598 buffer = bp; 2599 2600 if ( len == 0 ) 2601 return(1); 2602 2603 while ( len ) { 2604 2605 phy_buf = kvtop(buffer); 2606 phy_len = NBPG - ((int) buffer & PGOFSET); 2607 2608 if ( len < phy_len ) 2609 phy_len = len; 2610 2611 if ( phy_buf & mask ) 2612 return(1); 2613 2614 buffer += phy_len; 2615 len -= phy_len; 2616 } 2617 2618 return(0); 2619 } 2620 2621 int 2622 sbictoscsiperiod(dev, a) 2623 struct sbic_softc *dev; 2624 int a; 2625 { 2626 unsigned int fs; 2627 2628 /* 2629 * cycle = DIV / (2 * CLK) 2630 * DIV = FS + 2 2631 * best we can do is 200ns at 20Mhz, 2 cycles 2632 */ 2633 2634 GET_SBIC_myid(dev->sc_sbicp, fs); 2635 2636 fs = (fs >> 6) + 2; /* DIV */ 2637 2638 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2639 2640 if ( a < 2 ) 2641 a = 8; /* map to Cycles */ 2642 2643 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2644 } 2645 2646 int 2647 sbicfromscsiperiod(dev, p) 2648 struct sbic_softc *dev; 2649 int p; 2650 { 2651 unsigned fs, 2652 ret; 2653 2654 /* 2655 * Just the inverse of the above 2656 */ 2657 GET_SBIC_myid(dev->sc_sbicp, fs); 2658 2659 fs = (fs >> 6) + 2; /* DIV */ 2660 2661 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2662 2663 ret = p << 2; /* in ns units */ 2664 ret = ret / fs; /* in Cycles */ 2665 2666 if ( ret < sbic_min_period ) 2667 return(sbic_min_period); 2668 2669 /* 2670 * verify rounding 2671 */ 2672 if ( sbictoscsiperiod(dev, ret) < p ) 2673 ret++; 2674 2675 return( (ret >= 8) ? 0 : ret ); 2676 } 2677 2678 #ifdef DEBUG 2679 void 2680 sbictimeout(dev) 2681 struct sbic_softc *dev; 2682 { 2683 int s, 2684 asr; 2685 2686 s = splbio(); 2687 2688 if ( dev->sc_dmatimo ) { 2689 2690 if ( dev->sc_dmatimo > 1 ) { 2691 2692 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2693 dev->sc_dmatimo - 1); 2694 2695 GET_SBIC_asr(dev->sc_sbicp, asr); 2696 2697 if ( asr & SBIC_ASR_INT ) { 2698 /* 2699 * We need to service a missed IRQ 2700 */ 2701 sbicintr(dev); 2702 } else { 2703 (void) sbicabort(dev, "timeout"); 2704 splx(s); 2705 return; 2706 } 2707 } 2708 2709 dev->sc_dmatimo++; 2710 } 2711 2712 splx(s); 2713 2714 timeout((void *)sbictimeout, dev, 30 * hz); 2715 } 2716 #endif 2717
Indexes created Sun Sep 28 16:09:52 GMT 2025