sbic.c revision 1.23
1 /* $NetBSD: sbic.c,v 1.23 2003/07/15 02:43:47 lukem Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: sbic.c,v 1.23 2003/07/15 02:43:47 lukem Exp $"); 58 59 #include "opt_ddb.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/device.h> 64 #include <sys/kernel.h> /* For hz */ 65 #include <sys/disklabel.h> 66 #include <sys/buf.h> 67 68 #include <dev/scsipi/scsi_all.h> 69 #include <dev/scsipi/scsipi_all.h> 70 #include <dev/scsipi/scsiconf.h> 71 72 #include <uvm/uvm_extern.h> 73 74 #include <mvme68k/mvme68k/isr.h> 75 #include <mvme68k/dev/dmavar.h> 76 #include <mvme68k/dev/sbicreg.h> 77 #include <mvme68k/dev/sbicvar.h> 78 79 80 /* 81 * Since I can't find this in any other header files 82 */ 83 #define SCSI_PHASE(reg) (reg&0x07) 84 85 /* 86 * SCSI delays 87 * In u-seconds, primarily for state changes on the SPC. 88 */ 89 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 90 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 91 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 92 93 /* 94 * Convenience macro for waiting for a particular sbic event 95 */ 96 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 97 98 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 99 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 100 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 101 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 102 int sbiccheckdmap __P((void *, u_long, u_long)); 103 u_char sbicselectbus __P((struct sbic_softc *)); 104 int sbicxfout __P((sbic_regmap_p, int, void *)); 105 int sbicxfin __P((sbic_regmap_p, int, void *)); 106 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 107 int sbictoscsiperiod __P((struct sbic_softc *, int)); 108 int sbicpoll __P((struct sbic_softc *)); 109 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 110 int sbicmsgin __P((struct sbic_softc *)); 111 int sbicabort __P((struct sbic_softc *, char *)); 112 void sbicxfdone __P((struct sbic_softc *)); 113 void sbicerror __P((struct sbic_softc *,u_char)); 114 void sbicreset __P((struct sbic_softc *)); 115 void sbic_scsidone __P((struct sbic_acb *, int)); 116 void sbic_sched __P((struct sbic_softc *)); 117 void sbic_save_ptrs __P((struct sbic_softc *)); 118 void sbic_load_ptrs __P((struct sbic_softc *)); 119 120 /* 121 * Synch xfer parameters, and timing conversions 122 */ 123 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 124 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 125 int sbic_cmd_wait = SBIC_CMD_WAIT; 126 int sbic_data_wait = SBIC_DATA_WAIT; 127 int sbic_init_wait = SBIC_INIT_WAIT; 128 129 /* 130 * was broken before.. now if you want this you get it for all drives 131 * on sbic controllers. 132 */ 133 u_char sbic_inhibit_sync[8]; 134 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 135 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 136 int sbic_parallel_operations = 1; /* Allow command queues */ 137 138 /* 139 * Some useful stuff for debugging purposes 140 */ 141 #ifdef DEBUG 142 int sbicdma_ops = 0; /* total DMA operations */ 143 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 144 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 145 int sbicdma_saves = 0; 146 147 #define QPRINTF(a) if (sbic_debug > 1) printf a 148 149 int sbic_debug = 0; /* Debug all chip related things */ 150 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 151 int reselect_debug = 0; /* Debug all reselection related things */ 152 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 153 154 void sbictimeout __P((struct sbic_softc *dev)); 155 156 #else 157 #define QPRINTF(a) /* */ 158 #endif 159 160 161 /* 162 * default minphys routine for sbic based controllers 163 */ 164 void 165 sbic_minphys(bp) 166 struct buf *bp; 167 { 168 /* 169 * No max transfer at this level. 170 */ 171 minphys(bp); 172 } 173 174 175 /* 176 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 177 */ 178 void 179 sbic_save_ptrs(dev) 180 struct sbic_softc *dev; 181 { 182 sbic_regmap_p regs; 183 struct sbic_acb* acb; 184 int count, 185 asr, 186 s; 187 188 /* 189 * Only need to save pointers if DMA was active... 190 */ 191 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 192 return; 193 194 regs = dev->sc_sbicp; 195 196 s = splbio(); 197 198 /* 199 * Wait until WD chip is idle 200 */ 201 do { 202 GET_SBIC_asr(regs, asr); 203 if( asr & SBIC_ASR_DBR ) { 204 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 205 splx(s); 206 return; 207 } 208 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 209 210 211 /* 212 * Save important state. 213 * must be done before dmastop 214 */ 215 acb = dev->sc_nexus; 216 acb->sc_dmacmd = dev->sc_dmacmd; 217 218 /* 219 * Fetch the residual count 220 */ 221 SBIC_TC_GET(regs, count); 222 223 /* 224 * Shut down DMA 225 */ 226 dev->sc_dmastop(dev); 227 228 /* 229 * No longer in DMA 230 */ 231 dev->sc_flags &= ~SBICF_INDMA; 232 233 /* 234 * Ensure the WD chip is back in polled I/O mode, with nothing to 235 * transfer. 236 */ 237 SBIC_TC_PUT(regs, 0); 238 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 239 240 /* 241 * Update current count... 242 */ 243 acb->sc_tcnt = count; 244 245 /* 246 * Work out how many bytes were actually transferred 247 */ 248 count = dev->sc_tcnt - count; 249 dev->sc_tcnt = acb->sc_tcnt; 250 251 /* 252 * Fixup partial xfers 253 */ 254 acb->sc_kv.dc_addr += count; 255 acb->sc_kv.dc_count -= count; 256 acb->sc_pa.dc_addr += count; 257 acb->sc_pa.dc_count -= count >> 1; 258 259 #ifdef DEBUG 260 if ( data_pointer_debug ) 261 printf("save at (%p,%x):%x\n", 262 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 263 sbicdma_saves++; 264 #endif 265 266 splx(s); 267 } 268 269 270 /* 271 * DOES NOT RESTART DMA!!! 272 */ 273 void 274 sbic_load_ptrs(dev) 275 struct sbic_softc *dev; 276 { 277 struct sbic_acb *acb = dev->sc_nexus; 278 int s; 279 280 if ( acb->sc_kv.dc_count == 0 ) { 281 /* 282 * No data to xfer 283 */ 284 return; 285 } 286 287 s = splbio(); 288 289 /* 290 * Reset the Scatter-Gather chain 291 */ 292 dev->sc_last = dev->sc_cur = &acb->sc_pa; 293 294 /* 295 * Restore the Transfer Count and DMA specific data 296 */ 297 dev->sc_tcnt = acb->sc_tcnt; 298 dev->sc_dmacmd = acb->sc_dmacmd; 299 300 #ifdef DEBUG 301 sbicdma_ops++; 302 #endif 303 304 /* 305 * Need to fixup new segment? 306 */ 307 if ( dev->sc_tcnt == 0 ) { 308 /* 309 * sc_tcnt == 0 implies end of segment 310 */ 311 char *vaddr, *paddr; 312 int count; 313 314 /* 315 * do kvm to pa mappings 316 */ 317 vaddr = acb->sc_kv.dc_addr; 318 paddr = acb->sc_pa.dc_addr = (char *) kvtop((caddr_t)vaddr); 319 320 for (count = (PAGE_SIZE - ((int)vaddr & PGOFSET)); 321 count < acb->sc_kv.dc_count && 322 (char*)kvtop((caddr_t)(vaddr + count + 4)) == paddr + count + 4; 323 count += PAGE_SIZE) 324 ; /* Do nothing */ 325 326 /* 327 * If it's all contiguous... 328 */ 329 if ( count > acb->sc_kv.dc_count ) { 330 count = acb->sc_kv.dc_count; 331 #ifdef DEBUG 332 sbicdma_hits++; 333 #endif 334 } 335 #ifdef DEBUG 336 else 337 sbicdma_misses++; 338 #endif 339 340 acb->sc_tcnt = count; 341 acb->sc_pa.dc_count = count >> 1; 342 343 #ifdef DEBUG 344 if ( data_pointer_debug ) 345 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", acb->sc_kv.dc_addr, 346 acb->sc_kv.dc_count, 347 acb->sc_pa.dc_addr, 348 acb->sc_tcnt); 349 #endif 350 351 } 352 353 splx(s); 354 } 355 356 /* 357 * used by specific sbic controller 358 * 359 * it appears that the higher level code does nothing with LUN's 360 * so I will too. I could plug it in, however so could they 361 * in scsi_scsipi_cmd(). 362 */ 363 void 364 sbic_scsi_request(chan, req, arg) 365 struct scsipi_channel *chan; 366 scsipi_adapter_req_t req; 367 void *arg; 368 { 369 struct scsipi_xfer *xs; 370 struct scsipi_periph *periph; 371 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 372 struct sbic_acb *acb; 373 int flags, s; 374 375 switch (req) { 376 case ADAPTER_REQ_RUN_XFER: 377 xs = arg; 378 periph = xs->xs_periph; 379 flags = xs->xs_control; 380 381 if ( flags & XS_CTL_DATA_UIO ) 382 panic("sbic: scsi data uio requested"); 383 384 if ( dev->sc_nexus && (flags & XS_CTL_POLL) ) 385 panic("sbic_scsicmd: busy"); 386 387 s = splbio(); 388 389 if ( (acb = dev->free_list.tqh_first) != NULL ) 390 TAILQ_REMOVE(&dev->free_list, acb, chain); 391 392 splx(s); 393 394 if ( acb == NULL ) { 395 #ifdef DEBUG 396 printf("sbic_scsicmd: unable to queue request for target %d\n", 397 periph->periph_target); 398 #ifdef DDB 399 Debugger(); 400 #endif 401 #endif 402 xs->error = XS_RESOURCE_SHORTAGE; 403 scsipi_done(xs); 404 return; 405 } 406 407 if ( flags & XS_CTL_DATA_IN ) 408 acb->flags = ACB_ACTIVE | ACB_DATAIN; 409 else 410 acb->flags = ACB_ACTIVE; 411 412 acb->xs = xs; 413 acb->clen = xs->cmdlen; 414 acb->sc_kv.dc_addr = xs->data; 415 acb->sc_kv.dc_count = xs->datalen; 416 acb->pa_addr = xs->data ? (char *)kvtop((caddr_t)xs->data) : 0; 417 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 418 419 if ( flags & XS_CTL_POLL ) { 420 /* 421 * This has major side effects -- it locks up the machine 422 */ 423 int stat; 424 425 s = splbio(); 426 427 dev->sc_flags |= SBICF_ICMD; 428 429 do { 430 /* 431 * If we already had a nexus, while away the time until idle... 432 * This is likely only to happen if a reselection occurs between 433 * here and our earlier check for ICMD && sc_nexus (which would 434 * have resulted in a panic() had it been true). 435 */ 436 while ( dev->sc_nexus ) 437 sbicpoll(dev); 438 439 /* 440 * Fix up the new nexus 441 */ 442 dev->sc_nexus = acb; 443 dev->sc_xs = xs; 444 dev->target = periph->periph_target; 445 dev->lun = periph->periph_lun; 446 447 stat = sbicicmd(dev, &acb->cmd, acb->clen, 448 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 449 450 } while ( dev->sc_nexus != acb ); 451 452 sbic_scsidone(acb, stat); 453 454 splx(s); 455 456 return; 457 } 458 459 s = splbio(); 460 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 461 462 /* 463 * If nothing is active, try to start it now. 464 */ 465 if ( dev->sc_nexus == NULL ) 466 sbic_sched(dev); 467 468 splx(s); 469 470 return; 471 472 case ADAPTER_REQ_GROW_RESOURCES: 473 /* XXX Not supported. */ 474 return; 475 476 case ADAPTER_REQ_SET_XFER_MODE: 477 /* XXX Not supported. */ 478 return; 479 } 480 481 } 482 483 /* 484 * attempt to start the next available command 485 */ 486 void 487 sbic_sched(dev) 488 struct sbic_softc *dev; 489 { 490 struct scsipi_xfer *xs; 491 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 492 struct sbic_acb *acb; 493 int flags, 494 stat; 495 496 /* 497 * XXXSCW 498 * I'll keep this test here, even though I can't see any obvious way 499 * in which sbic_sched() could be called with sc_nexus non NULL 500 */ 501 if ( dev->sc_nexus ) 502 return; /* a command is current active */ 503 504 /* 505 * Loop through the ready list looking for work to do... 506 */ 507 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 508 int i, j; 509 510 periph = acb->xs->xs_periph; 511 i = periph->periph_target; 512 j = 1 << periph->periph_lun; 513 514 /* 515 * We've found a potential command, but is the target/lun busy? 516 */ 517 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 518 /* 519 * Nope, it's not busy, so we can use it. 520 */ 521 dev->sc_tinfo[i].lubusy |= j; 522 TAILQ_REMOVE(&dev->ready_list, acb, chain); 523 dev->sc_nexus = acb; 524 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 525 break; 526 } 527 } 528 529 if ( acb == NULL ) { 530 QPRINTF(("sbicsched: no work\n")); 531 return; /* did not find an available command */ 532 } 533 534 #ifdef DEBUG 535 if ( data_pointer_debug > 1 ) 536 printf("sbic_sched(%d,%d)\n", periph->periph_target, 537 periph->periph_lun); 538 #endif 539 540 dev->sc_xs = xs = acb->xs; 541 flags = xs->xs_control; 542 543 if ( flags & XS_CTL_RESET ) 544 sbicreset(dev); 545 546 dev->sc_stat[0] = -1; 547 dev->target = periph->periph_target; 548 dev->lun = periph->periph_lun; 549 550 if ( flags & XS_CTL_POLL || (!sbic_parallel_operations && 551 (sbicdmaok(dev, xs) == 0)) ) 552 stat = sbicicmd(dev, &acb->cmd, acb->clen, 553 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 554 else 555 if ( sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT ) 556 return; 557 else 558 stat = dev->sc_stat[0]; 559 560 sbic_scsidone(acb, stat); 561 } 562 563 void 564 sbic_scsidone(acb, stat) 565 struct sbic_acb *acb; 566 int stat; 567 { 568 struct scsipi_xfer *xs = acb->xs; 569 struct scsipi_periph *periph = xs->xs_periph; 570 struct sbic_softc *dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; 571 int dosched = 0; 572 573 #ifdef DIAGNOSTIC 574 if ( acb == NULL || xs == NULL ) { 575 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); 576 #ifdef DDB 577 Debugger(); 578 #endif 579 return; 580 } 581 #endif 582 583 584 #ifdef DEBUG 585 if ( data_pointer_debug > 1 ) 586 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", periph->periph_target, 587 periph->periph_lun, 588 dev->target, dev->lun, stat); 589 590 if ( xs->xs_periph->periph_target == dev->sc_channel.chan_id) 591 panic("target == hostid"); 592 #endif 593 594 xs->status = stat; 595 xs->resid = 0; /* XXXX */ 596 if ( xs->error == XS_NOERROR) { 597 if ( stat == SCSI_CHECK || stat == SCSI_BUSY) 598 xs->error = XS_BUSY; 599 } 600 601 602 /* 603 * Remove the ACB from whatever queue it's on. We have to do a bit of 604 * a hack to figure out which queue it's on. Note that it is *not* 605 * necessary to cdr down the ready queue, but we must cdr down the 606 * nexus queue and see if it's there, so we can mark the unit as no 607 * longer busy. This code is sickening, but it works. 608 */ 609 if ( acb == dev->sc_nexus ) { 610 611 dev->sc_nexus = NULL; 612 dev->sc_xs = NULL; 613 614 dev->sc_tinfo[periph->periph_target].lubusy &= 615 ~(1 << periph->periph_lun); 616 617 if ( dev->ready_list.tqh_first ) 618 dosched = 1; /* start next command */ 619 620 } else 621 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 622 623 TAILQ_REMOVE(&dev->ready_list, acb, chain); 624 625 } else { 626 627 struct sbic_acb *a; 628 629 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 630 if ( a == acb ) { 631 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 632 dev->sc_tinfo[periph->periph_target].lubusy &= 633 ~(1 << periph->periph_lun); 634 break; 635 } 636 } 637 638 if ( a ) 639 ; 640 else if ( acb->chain.tqe_next ) { 641 TAILQ_REMOVE(&dev->ready_list, acb, chain); 642 } else { 643 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 644 #ifdef DDB 645 Debugger(); 646 #endif 647 } 648 } 649 650 /* 651 * Put it on the free list. 652 */ 653 acb->flags = ACB_FREE; 654 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 655 656 dev->sc_tinfo[periph->periph_target].cmds++; 657 658 scsipi_done(xs); 659 660 if ( dosched ) 661 sbic_sched(dev); 662 } 663 664 int 665 sbicdmaok(dev, xs) 666 struct sbic_softc *dev; 667 struct scsipi_xfer *xs; 668 { 669 if ( sbic_no_dma || xs->datalen == 0 || 670 xs->datalen & 0x03 || (int)xs->data & 0x03) 671 return(0); 672 673 /* 674 * controller supports DMA to any addresses? 675 */ 676 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 677 return(1); 678 679 /* 680 * this address is ok for DMA? 681 */ 682 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 683 return(1); 684 685 return(0); 686 } 687 688 int 689 sbicwait(regs, until, timeo, line) 690 sbic_regmap_p regs; 691 u_char until; 692 int timeo; 693 int line; 694 { 695 u_char val; 696 697 if ( timeo == 0 ) 698 timeo = 1000000; /* some large value.. */ 699 700 GET_SBIC_asr(regs, val); 701 702 while ( (val & until) == 0 ) { 703 704 if ( timeo-- == 0 ) { 705 int csr; 706 GET_SBIC_csr(regs, csr); 707 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 708 #if defined(DDB) && defined(DEBUG) 709 Debugger(); 710 #endif 711 return(val); /* Maybe I should abort */ 712 break; 713 } 714 715 DELAY(1); 716 GET_SBIC_asr(regs, val); 717 } 718 719 return(val); 720 } 721 722 int 723 sbicabort(dev, where) 724 struct sbic_softc *dev; 725 char *where; 726 { 727 sbic_regmap_p regs = dev->sc_sbicp; 728 u_char csr, 729 asr; 730 731 GET_SBIC_asr(regs, asr); 732 GET_SBIC_csr(regs, csr); 733 734 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 735 dev->sc_dev.dv_xname, where, csr, asr); 736 737 /* 738 * Clean up chip itself 739 */ 740 if ( dev->sc_flags & SBICF_SELECTED ) { 741 742 while ( asr & SBIC_ASR_DBR ) { 743 /* 744 * sbic is jammed w/data. need to clear it 745 * But we don't know what direction it needs to go 746 */ 747 GET_SBIC_data(regs, asr); 748 printf("%s: abort %s: clearing data buffer 0x%02x\n", 749 dev->sc_dev.dv_xname, where, asr); 750 GET_SBIC_asr(regs, asr); 751 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 752 SET_SBIC_data(regs, asr); 753 GET_SBIC_asr(regs, asr); 754 } 755 756 WAIT_CIP(regs); 757 758 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 759 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 760 WAIT_CIP(regs); 761 762 GET_SBIC_asr(regs, asr); 763 764 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 765 /* 766 * ok, get more drastic.. 767 */ 768 printf("%s: sbicabort - asr %x, trying to reset\n", 769 dev->sc_dev.dv_xname, asr); 770 sbicreset(dev); 771 dev->sc_flags &= ~SBICF_SELECTED; 772 return SBIC_STATE_ERROR; 773 } 774 775 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 776 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 777 778 do { 779 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 780 GET_SBIC_asr(regs, asr); 781 GET_SBIC_csr (regs, csr); 782 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 783 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 784 (csr != SBIC_CSR_CMD_INVALID) ); 785 786 /* 787 * lets just hope it worked.. 788 */ 789 dev->sc_flags &= ~SBICF_SELECTED; 790 } 791 792 return SBIC_STATE_ERROR; 793 } 794 795 796 /* 797 * Initialize driver-private structures 798 */ 799 void 800 sbicinit(dev) 801 struct sbic_softc *dev; 802 { 803 u_int i; 804 805 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 806 807 struct sbic_acb *acb; 808 809 TAILQ_INIT(&dev->ready_list); 810 TAILQ_INIT(&dev->nexus_list); 811 TAILQ_INIT(&dev->free_list); 812 callout_init(&dev->sc_timo_ch); 813 814 dev->sc_nexus = NULL; 815 dev->sc_xs = NULL; 816 817 acb = dev->sc_acb; 818 memset(acb, 0, sizeof(dev->sc_acb)); 819 820 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 821 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 822 acb++; 823 } 824 825 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 826 827 #ifdef DEBUG 828 /* 829 * make sure timeout is really not needed 830 */ 831 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 832 #endif 833 834 } else 835 panic("sbic: reinitializing driver!"); 836 837 dev->sc_flags |= SBICF_ALIVE; 838 dev->sc_flags &= ~SBICF_SELECTED; 839 840 /* 841 * initialize inhibit array 842 * Never enable Sync, since it just doesn't work on mvme147 :( 843 */ 844 for (i = 0; i < 8; ++i) 845 sbic_inhibit_sync[i] = 1; 846 847 sbicreset(dev); 848 } 849 850 void 851 sbicreset(dev) 852 struct sbic_softc *dev; 853 { 854 sbic_regmap_p regs = dev->sc_sbicp; 855 u_int my_id, 856 s; 857 u_char csr; 858 859 s = splbio(); 860 861 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 862 863 if (dev->sc_clkfreq < 110) 864 my_id |= SBIC_ID_FS_8_10; 865 else if (dev->sc_clkfreq < 160) 866 my_id |= SBIC_ID_FS_12_15; 867 else if (dev->sc_clkfreq < 210) 868 my_id |= SBIC_ID_FS_16_20; 869 870 SET_SBIC_myid(regs, my_id); 871 872 /* 873 * Reset the chip 874 */ 875 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 876 DELAY(25); 877 878 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 879 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 880 881 /* 882 * Set up various chip parameters 883 */ 884 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 885 886 /* 887 * don't allow Selection (SBIC_RID_ES) 888 * until we can handle target mode!! 889 */ 890 SET_SBIC_rselid(regs, SBIC_RID_ER); 891 892 /* 893 * Asynchronous for now 894 */ 895 SET_SBIC_syn(regs, 0); 896 897 /* 898 * Anything else was zeroed by reset 899 */ 900 splx(s); 901 902 dev->sc_flags &= ~SBICF_SELECTED; 903 } 904 905 void 906 sbicerror(dev, csr) 907 struct sbic_softc *dev; 908 u_char csr; 909 { 910 struct scsipi_xfer *xs = dev->sc_xs; 911 912 #ifdef DIAGNOSTIC 913 if ( xs == NULL ) 914 panic("sbicerror: dev->sc_xs == NULL"); 915 #endif 916 917 if ( xs->xs_control & XS_CTL_SILENT ) 918 return; 919 920 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 921 } 922 923 /* 924 * select the bus, return when selected or error. 925 * 926 * Returns the current CSR following selection and optionally MSG out phase. 927 * i.e. the returned CSR *should* indicate CMD phase... 928 * If the return value is 0, some error happened. 929 */ 930 u_char 931 sbicselectbus(dev) 932 struct sbic_softc *dev; 933 { 934 sbic_regmap_p regs = dev->sc_sbicp; 935 u_char target = dev->target, 936 lun = dev->lun, 937 asr, 938 csr, 939 id; 940 941 /* 942 * if we're already selected, return (XXXX panic maybe?) 943 */ 944 if ( dev->sc_flags & SBICF_SELECTED ) 945 return(0); 946 947 QPRINTF(("sbicselectbus %d: ", target)); 948 949 /* 950 * issue select 951 */ 952 SET_SBIC_selid(regs, target); 953 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 954 955 GET_SBIC_asr(regs, asr); 956 957 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 958 /* 959 * This means we got ourselves reselected upon 960 */ 961 QPRINTF(("WD busy (reselect?)\n")); 962 return 0; 963 } 964 965 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 966 967 /* 968 * wait for select (merged from separate function may need 969 * cleanup) 970 */ 971 WAIT_CIP(regs); 972 973 do { 974 975 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 976 977 if ( asr & SBIC_ASR_LCI ) { 978 QPRINTF(("late LCI: asr %02x\n", asr)); 979 return 0; 980 } 981 982 /* 983 * Clear interrupt 984 */ 985 GET_SBIC_csr (regs, csr); 986 987 QPRINTF(("%02x ", csr)); 988 989 /* 990 * Reselected from under our feet? 991 */ 992 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 993 QPRINTF(("got reselected, asr %02x\n", asr)); 994 /* 995 * We need to handle this now so we don't lock up later 996 */ 997 sbicnextstate(dev, csr, asr); 998 999 return 0; 1000 } 1001 1002 /* 1003 * Whoops! 1004 */ 1005 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1006 panic("sbicselectbus: target issued select!"); 1007 return 0; 1008 } 1009 1010 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1011 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1012 csr != SBIC_CSR_SEL_TIMEO); 1013 1014 /* 1015 * Anyone at home? 1016 */ 1017 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1018 dev->sc_xs->error = XS_SELTIMEOUT; 1019 QPRINTF(("Selection Timeout\n")); 1020 return 0; 1021 } 1022 1023 QPRINTF(("Selection Complete\n")); 1024 1025 /* 1026 * Assume we're now selected 1027 */ 1028 GET_SBIC_selid(regs, id); 1029 dev->target = id; 1030 dev->lun = lun; 1031 dev->sc_flags |= SBICF_SELECTED; 1032 1033 /* 1034 * Enable (or not) reselection 1035 * XXXSCW This is probably not necessary since we don't use use the 1036 * Select-and-Xfer-with-ATN command to initiate a selection... 1037 */ 1038 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1039 SET_SBIC_rselid (regs, 0); 1040 else 1041 SET_SBIC_rselid (regs, SBIC_RID_ER); 1042 1043 /* 1044 * We only really need to do anything when the target goes to MSG out 1045 * If the device ignored ATN, it's probably old and brain-dead, 1046 * but we'll try to support it anyhow. 1047 * If it doesn't support message out, it definately doesn't 1048 * support synchronous transfers, so no point in even asking... 1049 */ 1050 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1051 /* 1052 * Send identify message (SCSI-2 requires an identify msg) 1053 */ 1054 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1055 /* 1056 * Handle drives that don't want to be asked 1057 * whether to go sync at all. 1058 */ 1059 dev->sc_sync[id].offset = 0; 1060 dev->sc_sync[id].period = sbic_min_period; 1061 dev->sc_sync[id].state = SYNC_DONE; 1062 } 1063 1064 /* 1065 * Do we need to negotiate Synchronous Xfers for this target? 1066 */ 1067 if ( dev->sc_sync[id].state != SYNC_START ) { 1068 /* 1069 * Nope, we've already negotiated. 1070 * Now see if we should allow the target to disconnect/reselect... 1071 */ 1072 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 1073 !sbic_enable_reselect ) 1074 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1075 else 1076 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1077 1078 } else { 1079 /* 1080 * try to initiate a sync transfer. 1081 * So compose the sync message we're going 1082 * to send to the target 1083 */ 1084 #ifdef DEBUG 1085 if ( sync_debug ) 1086 printf("\nSending sync request to target %d ... ", id); 1087 #endif 1088 /* 1089 * setup scsi message sync message request 1090 */ 1091 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1092 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1093 dev->sc_msg[2] = 3; 1094 dev->sc_msg[3] = MSG_SYNC_REQ; 1095 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1096 dev->sc_msg[5] = sbic_max_offset; 1097 1098 sbicxfout(regs, 6, dev->sc_msg); 1099 1100 dev->sc_sync[id].state = SYNC_SENT; 1101 #ifdef DEBUG 1102 if ( sync_debug ) 1103 printf ("sent\n"); 1104 #endif 1105 } 1106 1107 /* 1108 * There's one interrupt still to come: the change to CMD phase... 1109 */ 1110 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1111 GET_SBIC_csr(regs, csr); 1112 } 1113 1114 /* 1115 * set sync or async 1116 */ 1117 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1118 #ifdef DEBUG 1119 if ( sync_debug ) 1120 printf("select(%d): sync reg = 0x%02x\n", target, 1121 SBIC_SYN(dev->sc_sync[target].offset, 1122 dev->sc_sync[target].period)); 1123 #endif 1124 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1125 dev->sc_sync[target].period)); 1126 } else { 1127 #ifdef DEBUG 1128 if ( sync_debug ) 1129 printf("select(%d): sync reg = 0x%02x\n", target, 1130 SBIC_SYN(0,sbic_min_period)); 1131 #endif 1132 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1133 } 1134 1135 return csr; 1136 } 1137 1138 /* 1139 * Information Transfer *to* a Scsi Target. 1140 * 1141 * Note: Don't expect there to be an interrupt immediately after all 1142 * the data is transferred out. The WD spec sheet says that the Transfer- 1143 * Info command for non-MSG_IN phases only completes when the target 1144 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1145 * 1146 * This can have a nasty effect on commands which take a relatively long 1147 * time to complete, for example a START/STOP unit command may remain in 1148 * CMD phase until the disk has spun up. Only then will the target change 1149 * to STATUS phase. This is really only a problem for immediate commands 1150 * since we don't allow disconnection for them (yet). 1151 */ 1152 int 1153 sbicxfout(regs, len, bp) 1154 sbic_regmap_p regs; 1155 int len; 1156 void *bp; 1157 { 1158 int wait = sbic_data_wait; 1159 u_char asr, 1160 *buf = bp; 1161 1162 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1163 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1164 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1165 1166 /* 1167 * sigh.. WD-PROTO strikes again.. sending the command in one go 1168 * causes the chip to lock up if talking to certain (misbehaving?) 1169 * targets. Anyway, this procedure should work for all targets, but 1170 * it's slightly slower due to the overhead 1171 */ 1172 WAIT_CIP (regs); 1173 1174 SBIC_TC_PUT (regs, 0); 1175 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1176 SBIC_TC_PUT (regs, (unsigned)len); 1177 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1178 1179 /* 1180 * Loop for each byte transferred 1181 */ 1182 do { 1183 1184 GET_SBIC_asr (regs, asr); 1185 1186 if ( asr & SBIC_ASR_DBR ) { 1187 if ( len ) { 1188 SET_SBIC_data (regs, *buf); 1189 buf++; 1190 len--; 1191 } else { 1192 SET_SBIC_data (regs, 0); 1193 } 1194 wait = sbic_data_wait; 1195 } 1196 1197 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1198 1199 #ifdef DEBUG 1200 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1201 #endif 1202 1203 /* 1204 * Normally, an interrupt will be pending when this routing returns. 1205 */ 1206 return(len); 1207 } 1208 1209 /* 1210 * Information Transfer *from* a Scsi Target 1211 * returns # bytes left to read 1212 */ 1213 int 1214 sbicxfin(regs, len, bp) 1215 sbic_regmap_p regs; 1216 int len; 1217 void *bp; 1218 { 1219 int wait = sbic_data_wait; 1220 u_char *buf = bp; 1221 u_char asr; 1222 #ifdef DEBUG 1223 u_char *obp = bp; 1224 #endif 1225 1226 WAIT_CIP (regs); 1227 1228 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1229 SBIC_TC_PUT (regs, (unsigned)len); 1230 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1231 1232 /* 1233 * Loop for each byte transferred 1234 */ 1235 do { 1236 1237 GET_SBIC_asr (regs, asr); 1238 1239 if ( asr & SBIC_ASR_DBR ) { 1240 if ( len ) { 1241 GET_SBIC_data (regs, *buf); 1242 buf++; 1243 len--; 1244 } else { 1245 u_char foo; 1246 GET_SBIC_data (regs, foo); 1247 } 1248 wait = sbic_data_wait; 1249 } 1250 1251 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1252 1253 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1254 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1255 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1256 1257 SBIC_TC_PUT (regs, 0); 1258 1259 /* 1260 * this leaves with one csr to be read 1261 */ 1262 return len; 1263 } 1264 1265 /* 1266 * SCSI 'immediate' command: issue a command to some SCSI device 1267 * and get back an 'immediate' response (i.e., do programmed xfer 1268 * to get the response data). 'cbuf' is a buffer containing a scsi 1269 * command of length clen bytes. 'buf' is a buffer of length 'len' 1270 * bytes for data. The transfer direction is determined by the device 1271 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1272 * command must supply no data. 1273 * 1274 * Note that although this routine looks like it can handle disconnect/ 1275 * reselect, the fact is that it can't. There is still some work to be 1276 * done to clean this lot up. 1277 */ 1278 int 1279 sbicicmd(dev, cbuf, clen, buf, len) 1280 struct sbic_softc *dev; 1281 void *cbuf, 1282 *buf; 1283 int clen, 1284 len; 1285 { 1286 sbic_regmap_p regs = dev->sc_sbicp; 1287 struct sbic_acb *acb = dev->sc_nexus; 1288 u_char csr, 1289 asr; 1290 int still_busy = SBIC_STATE_RUNNING; 1291 1292 /* 1293 * Make sure pointers are OK 1294 */ 1295 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1296 dev->sc_tcnt = acb->sc_tcnt = 0; 1297 1298 acb->sc_dmacmd = 0; 1299 acb->sc_pa.dc_count = 0; /* No DMA */ 1300 acb->sc_kv.dc_addr = buf; 1301 acb->sc_kv.dc_count = len; 1302 1303 #ifdef DEBUG 1304 if ( data_pointer_debug > 1 ) 1305 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1306 #endif 1307 1308 /* 1309 * set the sbic into non-DMA mode 1310 */ 1311 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1312 1313 dev->sc_stat[0] = 0xff; 1314 dev->sc_msg[0] = 0xff; 1315 1316 /* 1317 * We're stealing the SCSI bus 1318 */ 1319 dev->sc_flags |= SBICF_ICMD; 1320 1321 do { 1322 GET_SBIC_asr (regs, asr); 1323 1324 /* 1325 * select the SCSI bus (it's an error if bus isn't free) 1326 */ 1327 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1328 still_busy != SBIC_STATE_DISCONNECT ) { 1329 if ( (csr = sbicselectbus(dev)) == 0 ) { 1330 dev->sc_flags &= ~SBICF_ICMD; 1331 return(-1); 1332 } 1333 } else 1334 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1335 GET_SBIC_csr(regs, csr); 1336 else 1337 csr = 0; 1338 1339 if ( csr ) { 1340 1341 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1342 1343 switch ( csr ) { 1344 1345 case SBIC_CSR_S_XFERRED: 1346 case SBIC_CSR_DISC: 1347 case SBIC_CSR_DISC_1: 1348 { 1349 u_char phase; 1350 1351 dev->sc_flags &= ~SBICF_SELECTED; 1352 GET_SBIC_cmd_phase (regs, phase); 1353 1354 if ( phase == 0x60 ) { 1355 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1356 still_busy = SBIC_STATE_DONE; /* done */ 1357 } else { 1358 #ifdef DEBUG 1359 if ( reselect_debug > 1 ) 1360 printf("sbicicmd: handling disconnect\n"); 1361 #endif 1362 still_busy = SBIC_STATE_DISCONNECT; 1363 } 1364 } 1365 break; 1366 1367 case SBIC_CSR_XFERRED | CMD_PHASE: 1368 case SBIC_CSR_MIS | CMD_PHASE: 1369 case SBIC_CSR_MIS_1 | CMD_PHASE: 1370 case SBIC_CSR_MIS_2 | CMD_PHASE: 1371 { 1372 if ( sbicxfout(regs, clen, cbuf) ) 1373 still_busy = sbicabort(dev, "icmd sending cmd"); 1374 } 1375 break; 1376 1377 case SBIC_CSR_XFERRED | STATUS_PHASE: 1378 case SBIC_CSR_MIS | STATUS_PHASE: 1379 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1380 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1381 { 1382 /* 1383 * The sbic does the status/cmd-complete reading ok, 1384 * so do this with its hi-level commands. 1385 */ 1386 #ifdef DEBUG 1387 if ( sbic_debug ) 1388 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1389 #endif 1390 SET_SBIC_cmd_phase(regs, 0x46); 1391 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1392 } 1393 break; 1394 1395 default: 1396 { 1397 still_busy = sbicnextstate(dev, csr, asr); 1398 } 1399 break; 1400 } 1401 1402 /* 1403 * make sure the last command was taken, 1404 * ie. we're not hunting after an ignored command.. 1405 */ 1406 GET_SBIC_asr(regs, asr); 1407 1408 /* 1409 * tapes may take a loooong time.. 1410 */ 1411 while (asr & SBIC_ASR_BSY ) { 1412 1413 if ( asr & SBIC_ASR_DBR ) { 1414 int i; 1415 1416 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1417 #ifdef DDB 1418 Debugger(); 1419 #endif 1420 /* 1421 * SBIC is jammed 1422 * DUNNO which direction 1423 * Try old direction 1424 */ 1425 GET_SBIC_data(regs, i); 1426 GET_SBIC_asr(regs, asr); 1427 1428 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1429 SET_SBIC_data(regs, i); 1430 } 1431 1432 GET_SBIC_asr(regs, asr); 1433 } 1434 } 1435 1436 /* 1437 * wait for last command to complete 1438 */ 1439 if ( asr & SBIC_ASR_LCI ) { 1440 printf("sbicicmd: last command ignored\n"); 1441 } 1442 else 1443 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1444 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1445 1446 /* 1447 * do it again 1448 */ 1449 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1450 1451 /* 1452 * Sometimes we need to do an extra read of the CSR 1453 */ 1454 GET_SBIC_csr(regs, csr); 1455 1456 #ifdef DEBUG 1457 if ( data_pointer_debug > 1 ) 1458 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1459 acb->sc_kv.dc_count, 1460 dev->sc_stat[0]); 1461 #endif 1462 1463 dev->sc_flags &= ~SBICF_ICMD; 1464 1465 return(dev->sc_stat[0]); 1466 } 1467 1468 /* 1469 * Finish SCSI xfer command: After the completion interrupt from 1470 * a read/write operation, sequence through the final phases in 1471 * programmed i/o. This routine is a lot like sbicicmd except we 1472 * skip (and don't allow) the select, cmd out and data in/out phases. 1473 */ 1474 void 1475 sbicxfdone(dev) 1476 struct sbic_softc *dev; 1477 { 1478 sbic_regmap_p regs = dev->sc_sbicp; 1479 u_char phase, 1480 csr; 1481 int s; 1482 1483 QPRINTF(("{")); 1484 s = splbio(); 1485 1486 /* 1487 * have the sbic complete on its own 1488 */ 1489 SBIC_TC_PUT(regs, 0); 1490 SET_SBIC_cmd_phase(regs, 0x46); 1491 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1492 1493 do { 1494 1495 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1496 GET_SBIC_csr (regs, csr); 1497 QPRINTF(("%02x:", csr)); 1498 1499 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1500 (csr != SBIC_CSR_S_XFERRED)); 1501 1502 dev->sc_flags &= ~SBICF_SELECTED; 1503 1504 GET_SBIC_cmd_phase (regs, phase); 1505 QPRINTF(("}%02x", phase)); 1506 1507 if ( phase == 0x60 ) 1508 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1509 else 1510 sbicerror(dev, csr); 1511 1512 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1513 1514 splx(s); 1515 } 1516 1517 /* 1518 * No DMA chains 1519 */ 1520 int 1521 sbicgo(dev, xs) 1522 struct sbic_softc *dev; 1523 struct scsipi_xfer *xs; 1524 { 1525 struct sbic_acb *acb = dev->sc_nexus; 1526 sbic_regmap_p regs = dev->sc_sbicp; 1527 int i, 1528 dmaflags, 1529 count, 1530 usedma; 1531 u_char csr, 1532 asr, 1533 *addr; 1534 1535 dev->target = xs->xs_periph->periph_target; 1536 dev->lun = xs->xs_periph->periph_lun; 1537 1538 usedma = sbicdmaok(dev, xs); 1539 1540 #ifdef DEBUG 1541 if ( data_pointer_debug > 1 ) 1542 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1543 #endif 1544 1545 /* 1546 * select the SCSI bus (it's an error if bus isn't free) 1547 */ 1548 if ( (csr = sbicselectbus(dev)) == 0 ) 1549 return(0); /* Not done: needs to be rescheduled */ 1550 1551 dev->sc_stat[0] = 0xff; 1552 1553 /* 1554 * Calculate DMA chains now 1555 */ 1556 if ( acb->flags & ACB_DATAIN ) 1557 dmaflags = DMAGO_READ; 1558 else 1559 dmaflags = 0; 1560 1561 addr = acb->sc_kv.dc_addr; 1562 count = acb->sc_kv.dc_count; 1563 1564 if ( count && ((char *)kvtop((caddr_t)addr) != acb->sc_pa.dc_addr) ) { 1565 printf("sbic: DMA buffer mapping changed %p->%x\n", 1566 acb->sc_pa.dc_addr, kvtop((caddr_t)addr)); 1567 #ifdef DDB 1568 Debugger(); 1569 #endif 1570 } 1571 1572 #ifdef DEBUG 1573 ++sbicdma_ops; /* count total DMA operations */ 1574 #endif 1575 1576 /* 1577 * Allocate the DMA chain 1578 * Mark end of segment... 1579 */ 1580 acb->sc_tcnt = dev->sc_tcnt = 0; 1581 acb->sc_pa.dc_count = 0; 1582 1583 sbic_load_ptrs(dev); 1584 1585 /* 1586 * Enable interrupts but don't do any DMA 1587 * enintr() also enables interrupts for the sbic 1588 */ 1589 dev->sc_enintr(dev); 1590 1591 if ( usedma ) { 1592 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1593 acb->sc_pa.dc_count, dmaflags); 1594 #ifdef DEBUG 1595 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1596 #endif 1597 } else 1598 dev->sc_dmacmd = 0; /* Don't use DMA */ 1599 1600 acb->sc_dmacmd = dev->sc_dmacmd; 1601 1602 #ifdef DEBUG 1603 if ( data_pointer_debug > 1 ) { 1604 printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, 1605 dev->sc_cur->dc_addr, 1606 dev->sc_tcnt, 1607 dev->sc_dmacmd); 1608 } 1609 #endif 1610 1611 /* 1612 * Lets cycle a while then let the interrupt handler take over. 1613 */ 1614 GET_SBIC_asr(regs, asr); 1615 1616 do { 1617 1618 QPRINTF(("go ")); 1619 1620 /* 1621 * Handle the new phase 1622 */ 1623 i = sbicnextstate(dev, csr, asr); 1624 #if 0 1625 WAIT_CIP(regs); 1626 #endif 1627 if ( i == SBIC_STATE_RUNNING ) { 1628 GET_SBIC_asr(regs, asr); 1629 1630 if ( asr & SBIC_ASR_LCI ) 1631 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1632 1633 if ( asr & SBIC_ASR_INT ) 1634 GET_SBIC_csr(regs, csr); 1635 } 1636 1637 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1638 1639 if ( i == SBIC_STATE_DONE ) { 1640 if ( dev->sc_stat[0] == 0xff ) 1641 #if 0 1642 printf("sbicgo: done & stat = 0xff\n"); 1643 #else 1644 ; 1645 #endif 1646 else 1647 return 1; /* Did we really finish that fast? */ 1648 } 1649 1650 return 0; 1651 } 1652 1653 1654 int 1655 sbicintr(dev) 1656 struct sbic_softc *dev; 1657 { 1658 sbic_regmap_p regs = dev->sc_sbicp; 1659 u_char asr, 1660 csr; 1661 int i; 1662 1663 /* 1664 * pending interrupt? 1665 */ 1666 GET_SBIC_asr (regs, asr); 1667 if ( (asr & SBIC_ASR_INT) == 0 ) 1668 return(0); 1669 1670 GET_SBIC_csr(regs, csr); 1671 1672 do { 1673 1674 QPRINTF(("intr[0x%x]", csr)); 1675 1676 i = sbicnextstate(dev, csr, asr); 1677 #if 0 1678 WAIT_CIP(regs); 1679 #endif 1680 if ( i == SBIC_STATE_RUNNING ) { 1681 GET_SBIC_asr(regs, asr); 1682 1683 if ( asr & SBIC_ASR_LCI ) 1684 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1685 1686 if ( asr & SBIC_ASR_INT ) 1687 GET_SBIC_csr(regs, csr); 1688 } 1689 1690 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1691 1692 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1693 1694 return(1); 1695 } 1696 1697 /* 1698 * Run commands and wait for disconnect. 1699 * This is only ever called when a command is in progress, when we 1700 * want to busy wait for it to finish. 1701 */ 1702 int 1703 sbicpoll(dev) 1704 struct sbic_softc *dev; 1705 { 1706 sbic_regmap_p regs = dev->sc_sbicp; 1707 u_char asr, 1708 csr; 1709 int i; 1710 1711 /* 1712 * Wait for the next interrupt 1713 */ 1714 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1715 1716 do { 1717 GET_SBIC_asr (regs, asr); 1718 1719 if ( asr & SBIC_ASR_INT ) 1720 GET_SBIC_csr(regs, csr); 1721 1722 QPRINTF(("poll[0x%x]", csr)); 1723 1724 /* 1725 * Handle it 1726 */ 1727 i = sbicnextstate(dev, csr, asr); 1728 1729 WAIT_CIP(regs); 1730 GET_SBIC_asr(regs, asr); 1731 1732 /* 1733 * tapes may take a loooong time.. 1734 */ 1735 while ( asr & SBIC_ASR_BSY ) { 1736 u_char z = 0; 1737 1738 if ( asr & SBIC_ASR_DBR ) { 1739 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1740 #ifdef DDB 1741 Debugger(); 1742 #endif 1743 /* 1744 * SBIC is jammed 1745 * DUNNO which direction 1746 * Try old direction 1747 */ 1748 GET_SBIC_data(regs, z); 1749 GET_SBIC_asr(regs, asr); 1750 1751 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1752 SET_SBIC_data(regs, z); 1753 } 1754 1755 GET_SBIC_asr(regs, asr); 1756 } 1757 1758 if ( asr & SBIC_ASR_LCI ) 1759 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1760 else 1761 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1762 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1763 1764 } while ( i == SBIC_STATE_RUNNING ); 1765 1766 return(1); 1767 } 1768 1769 /* 1770 * Handle a single msgin 1771 */ 1772 int 1773 sbicmsgin(dev) 1774 struct sbic_softc *dev; 1775 { 1776 sbic_regmap_p regs = dev->sc_sbicp; 1777 int recvlen = 1; 1778 u_char asr, 1779 csr, 1780 *tmpaddr, 1781 *msgaddr; 1782 1783 tmpaddr = msgaddr = dev->sc_msg; 1784 1785 tmpaddr[0] = 0xff; 1786 tmpaddr[1] = 0xff; 1787 1788 GET_SBIC_asr(regs, asr); 1789 1790 #ifdef DEBUG 1791 if ( reselect_debug > 1 ) 1792 printf("sbicmsgin asr=%02x\n", asr); 1793 #endif 1794 1795 GET_SBIC_selid (regs, csr); 1796 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1797 1798 SBIC_TC_PUT(regs, 0); 1799 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1800 1801 do { 1802 while( recvlen-- ) { 1803 1804 /* 1805 * Fetch the next byte of the message 1806 */ 1807 RECV_BYTE(regs, *tmpaddr); 1808 1809 /* 1810 * get the command completion interrupt, or we 1811 * can't send a new command (LCI) 1812 */ 1813 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1814 GET_SBIC_csr(regs, csr); 1815 1816 #ifdef DEBUG 1817 if ( reselect_debug > 1 ) 1818 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1819 #endif 1820 1821 tmpaddr++; 1822 1823 if ( recvlen ) { 1824 /* 1825 * Clear ACK, and wait for the interrupt for the next byte 1826 */ 1827 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1828 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1829 GET_SBIC_csr(regs, csr); 1830 } 1831 } 1832 1833 if ( msgaddr[0] == 0xff ) { 1834 printf("sbicmsgin: sbic swallowed our message\n"); 1835 break; 1836 } 1837 1838 #ifdef DEBUG 1839 if ( sync_debug ) { 1840 GET_SBIC_asr(regs, asr); 1841 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1842 } 1843 #endif 1844 /* 1845 * test whether this is a reply to our sync 1846 * request 1847 */ 1848 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1849 1850 /* 1851 * Got IFFY msg -- ack it 1852 */ 1853 QPRINTF(("IFFY")); 1854 1855 } else 1856 if ( msgaddr[0] == MSG_REJECT && 1857 dev->sc_sync[dev->target].state == SYNC_SENT) { 1858 1859 /* 1860 * Target probably rejected our Sync negotiation. 1861 */ 1862 QPRINTF(("REJECT of SYN")); 1863 1864 #ifdef DEBUG 1865 if ( sync_debug ) 1866 printf("target %d rejected sync, going async\n", dev->target); 1867 #endif 1868 1869 dev->sc_sync[dev->target].period = sbic_min_period; 1870 dev->sc_sync[dev->target].offset = 0; 1871 dev->sc_sync[dev->target].state = SYNC_DONE; 1872 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1873 dev->sc_sync[dev->target].period)); 1874 1875 } else 1876 if ( msgaddr[0] == MSG_REJECT ) { 1877 1878 /* 1879 * we'll never REJECt a REJECT message.. 1880 */ 1881 QPRINTF(("REJECT")); 1882 1883 } else 1884 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1885 1886 /* 1887 * don't reject this either. 1888 */ 1889 QPRINTF(("MSG_SAVE_DATA_PTR")); 1890 1891 } else 1892 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1893 1894 /* 1895 * don't reject this either. 1896 */ 1897 QPRINTF(("MSG_RESTORE_PTR")); 1898 1899 } else 1900 if ( msgaddr[0] == MSG_DISCONNECT ) { 1901 1902 /* 1903 * Target is disconnecting... 1904 */ 1905 QPRINTF(("DISCONNECT")); 1906 1907 #ifdef DEBUG 1908 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1909 printf("sbicmsgin: got disconnect msg %s\n", 1910 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1911 #endif 1912 1913 if ( dev->sc_flags & SBICF_ICMD ) { 1914 /* 1915 * We're in immediate mode. Prevent disconnects. 1916 * prepare to reject the message, NACK 1917 */ 1918 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1919 WAIT_CIP(regs); 1920 } 1921 1922 } else 1923 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1924 1925 /* 1926 * !! KLUDGE ALERT !! quite a few drives don't seem to 1927 * really like the current way of sending the 1928 * sync-handshake together with the ident-message, and 1929 * they react by sending command-complete and 1930 * disconnecting right after returning the valid sync 1931 * handshake. So, all I can do is reselect the drive, 1932 * and hope it won't disconnect again. I don't think 1933 * this is valid behavior, but I can't help fixing a 1934 * problem that apparently exists. 1935 * 1936 * Note: we should not get here on `normal' command 1937 * completion, as that condition is handled by the 1938 * high-level sel&xfer resume command used to walk 1939 * thru status/cc-phase. 1940 */ 1941 QPRINTF(("CMD_COMPLETE")); 1942 1943 #ifdef DEBUG 1944 if ( sync_debug ) 1945 printf ("GOT MSG %d! target %d acting weird.." 1946 " waiting for disconnect...\n", msgaddr[0], dev->target); 1947 #endif 1948 1949 /* 1950 * Check to see if sbic is handling this 1951 */ 1952 GET_SBIC_asr(regs, asr); 1953 1954 /* 1955 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 1956 */ 1957 if ( asr & SBIC_ASR_BSY ) 1958 return SBIC_STATE_RUNNING; 1959 1960 /* 1961 * Let's try this: Assume it works and set status to 00 1962 */ 1963 dev->sc_stat[0] = 0; 1964 1965 } else 1966 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 1967 1968 /* 1969 * Target is sending us an extended message. We'll assume it's 1970 * the response to our Sync. negotiation. 1971 */ 1972 QPRINTF(("ExtMSG\n")); 1973 1974 /* 1975 * Read in whole extended message. First, negate ACK to accept 1976 * the MSG_EXT_MESSAGE byte... 1977 */ 1978 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1979 1980 /* 1981 * Wait for the interrupt for the next byte (length) 1982 */ 1983 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1984 GET_SBIC_csr(regs, csr); 1985 1986 #ifdef DEBUG 1987 QPRINTF(("CLR ACK csr %02x\n", csr)); 1988 #endif 1989 1990 /* 1991 * Read the length byte 1992 */ 1993 RECV_BYTE(regs, *tmpaddr); 1994 1995 /* 1996 * Wait for command completion IRQ 1997 */ 1998 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1999 GET_SBIC_csr(regs, csr); 2000 2001 /* 2002 * Reload the loop counter 2003 */ 2004 recvlen = *tmpaddr++; 2005 2006 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2007 2008 } else 2009 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2010 msgaddr[2] == MSG_SYNC_REQ ) { 2011 2012 /* 2013 * We've received the complete Extended Message Sync. Request... 2014 */ 2015 QPRINTF(("SYN")); 2016 2017 /* 2018 * Compute the required Transfer Period for the WD chip... 2019 */ 2020 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2021 dev->sc_sync[dev->target].offset = msgaddr[4]; 2022 dev->sc_sync[dev->target].state = SYNC_DONE; 2023 2024 /* 2025 * Put the WD chip in synchronous mode 2026 */ 2027 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2028 dev->sc_sync[dev->target].period)); 2029 #ifdef DEBUG 2030 if ( sync_debug ) 2031 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2032 SBIC_SYN(dev->sc_sync[dev->target].offset, 2033 dev->sc_sync[dev->target].period)); 2034 #endif 2035 2036 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2037 dev->sc_dev.dv_xname, dev->target, 2038 msgaddr[3] * 4, msgaddr[4]); 2039 2040 } else { 2041 2042 /* 2043 * We don't support whatever this message is... 2044 */ 2045 #ifdef DEBUG 2046 if ( sbic_debug || sync_debug ) 2047 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2048 #endif 2049 2050 /* 2051 * prepare to reject the message, NACK 2052 */ 2053 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2054 WAIT_CIP(regs); 2055 } 2056 2057 /* 2058 * Negate ACK to complete the transfer 2059 */ 2060 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2061 2062 /* 2063 * Wait for the interrupt for the next byte, or phase change. 2064 * Only read the CSR if we have more data to transfer. 2065 * XXXSCW: We should really verify that we're still in MSG IN phase 2066 * before blindly going back around this loop, but that would mean 2067 * we read the CSR... <sigh> 2068 */ 2069 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2070 if ( recvlen > 0 ) 2071 GET_SBIC_csr(regs, csr); 2072 2073 } while ( recvlen > 0 ); 2074 2075 /* 2076 * Should still have one CSR to read 2077 */ 2078 return SBIC_STATE_RUNNING; 2079 } 2080 2081 2082 /* 2083 * sbicnextstate() 2084 * return: 2085 * SBIC_STATE_DONE == done 2086 * SBIC_STATE_RUNNING == working 2087 * SBIC_STATE_DISCONNECT == disconnected 2088 * SBIC_STATE_ERROR == error 2089 */ 2090 int 2091 sbicnextstate(dev, csr, asr) 2092 struct sbic_softc *dev; 2093 u_char csr, 2094 asr; 2095 { 2096 sbic_regmap_p regs = dev->sc_sbicp; 2097 struct sbic_acb *acb = dev->sc_nexus; 2098 2099 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2100 2101 switch (csr) { 2102 2103 case SBIC_CSR_XFERRED | CMD_PHASE: 2104 case SBIC_CSR_MIS | CMD_PHASE: 2105 case SBIC_CSR_MIS_1 | CMD_PHASE: 2106 case SBIC_CSR_MIS_2 | CMD_PHASE: 2107 { 2108 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2109 goto abort; 2110 } 2111 break; 2112 2113 case SBIC_CSR_XFERRED | STATUS_PHASE: 2114 case SBIC_CSR_MIS | STATUS_PHASE: 2115 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2116 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2117 { 2118 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2119 2120 /* 2121 * this should be the normal i/o completion case. 2122 * get the status & cmd complete msg then let the 2123 * device driver look at what happened. 2124 */ 2125 sbicxfdone(dev); 2126 2127 #ifdef DEBUG 2128 dev->sc_dmatimo = 0; 2129 if ( data_pointer_debug > 1 ) 2130 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2131 dev->sc_cur->dc_addr, 2132 dev->sc_tcnt); 2133 #endif 2134 /* 2135 * Stop the DMA chip 2136 */ 2137 dev->sc_dmastop(dev); 2138 2139 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2140 2141 /* 2142 * Indicate to the upper layers that the command is done 2143 */ 2144 sbic_scsidone(acb, dev->sc_stat[0]); 2145 2146 return SBIC_STATE_DONE; 2147 } 2148 2149 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2150 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2151 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2152 case SBIC_CSR_MIS | DATA_IN_PHASE: 2153 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2154 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2155 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2156 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2157 { 2158 /* 2159 * Verify that we expected to transfer data... 2160 */ 2161 if ( acb->sc_kv.dc_count <= 0 ) { 2162 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2163 acb->sc_kv.dc_count, asr, csr); 2164 goto abort; 2165 } 2166 2167 /* 2168 * Should we transfer using PIO or DMA ? 2169 */ 2170 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2171 acb->sc_dmacmd == 0 ) { 2172 2173 /* 2174 * Do PIO transfer 2175 */ 2176 int i; 2177 2178 #ifdef DEBUG 2179 if ( data_pointer_debug > 1 ) 2180 printf("next PIO: %d(%p:%x)\n", dev->target, 2181 acb->sc_kv.dc_addr, 2182 acb->sc_kv.dc_count); 2183 #endif 2184 2185 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2186 /* 2187 * data in 2188 */ 2189 i = sbicxfin(regs, acb->sc_kv.dc_count, 2190 acb->sc_kv.dc_addr); 2191 else 2192 /* 2193 * data out 2194 */ 2195 i = sbicxfout(regs, acb->sc_kv.dc_count, 2196 acb->sc_kv.dc_addr); 2197 2198 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2199 acb->sc_kv.dc_count = i; 2200 2201 /* 2202 * Update current count... 2203 */ 2204 acb->sc_tcnt = dev->sc_tcnt = i; 2205 2206 dev->sc_flags &= ~SBICF_INDMA; 2207 2208 } else { 2209 2210 /* 2211 * Do DMA transfer 2212 * set next DMA addr and dec count 2213 */ 2214 sbic_save_ptrs(dev); 2215 sbic_load_ptrs(dev); 2216 2217 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2218 SBIC_MACHINE_DMA_MODE); 2219 2220 #ifdef DEBUG 2221 dev->sc_dmatimo = 1; 2222 if ( data_pointer_debug > 1 ) 2223 printf("next DMA: %d(%p:%lx)\n", dev->target, 2224 dev->sc_cur->dc_addr, 2225 dev->sc_tcnt); 2226 #endif 2227 /* 2228 * Start the DMA chip going 2229 */ 2230 dev->sc_tcnt = dev->sc_dmanext(dev); 2231 2232 /* 2233 * Tell the WD chip how much to transfer this time around 2234 */ 2235 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2236 2237 /* 2238 * Start the transfer 2239 */ 2240 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2241 2242 /* 2243 * Indicate that we're in DMA mode 2244 */ 2245 dev->sc_flags |= SBICF_INDMA; 2246 } 2247 } 2248 break; 2249 2250 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2251 case SBIC_CSR_MIS | MESG_IN_PHASE: 2252 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2253 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2254 { 2255 sbic_save_ptrs(dev); 2256 2257 /* 2258 * Handle a single message in... 2259 */ 2260 return sbicmsgin(dev); 2261 } 2262 2263 case SBIC_CSR_MSGIN_W_ACK: 2264 { 2265 /* 2266 * We should never see this since it's handled in 'sbicmsgin()' 2267 * but just for the sake of paranoia... 2268 */ 2269 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2270 printf("Acking unknown msgin CSR:%02x",csr); 2271 } 2272 break; 2273 2274 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2275 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2276 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2277 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2278 { 2279 /* 2280 * We only ever handle a message out phase here for sending a 2281 * REJECT message. 2282 */ 2283 sbic_save_ptrs(dev); 2284 2285 #ifdef DEBUG 2286 if (sync_debug) 2287 printf ("sending REJECT msg to last msg.\n"); 2288 #endif 2289 2290 SEND_BYTE(regs, MSG_REJECT); 2291 WAIT_CIP(regs); 2292 } 2293 break; 2294 2295 case SBIC_CSR_DISC: 2296 case SBIC_CSR_DISC_1: 2297 { 2298 /* 2299 * Try to schedule another target 2300 */ 2301 sbic_save_ptrs(dev); 2302 2303 dev->sc_flags &= ~SBICF_SELECTED; 2304 2305 #ifdef DEBUG 2306 if ( reselect_debug > 1 ) 2307 printf("sbicnext target %d disconnected\n", dev->target); 2308 #endif 2309 2310 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2311 2312 ++dev->sc_tinfo[dev->target].dconns; 2313 2314 dev->sc_nexus = NULL; 2315 dev->sc_xs = NULL; 2316 2317 if ( acb->xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2318 !sbic_parallel_operations ) 2319 return SBIC_STATE_DISCONNECT; 2320 2321 QPRINTF(("sbicnext: calling sbic_sched\n")); 2322 2323 sbic_sched(dev); 2324 2325 QPRINTF(("sbicnext: sbic_sched returned\n")); 2326 2327 return SBIC_STATE_DISCONNECT; 2328 } 2329 2330 case SBIC_CSR_RSLT_NI: 2331 case SBIC_CSR_RSLT_IFY: 2332 { 2333 /* 2334 * A reselection. 2335 * Note that since we don't enable Advanced Features (assuming 2336 * the WD chip is at least the 'A' revision), we're only ever 2337 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2338 * hell of it, we'll handle it anyway, for all the extra code 2339 * it needs... 2340 */ 2341 u_char newtarget, 2342 newlun; 2343 2344 GET_SBIC_rselid(regs, newtarget); 2345 2346 /* 2347 * check SBIC_RID_SIV? 2348 */ 2349 newtarget &= SBIC_RID_MASK; 2350 2351 if ( csr == SBIC_CSR_RSLT_IFY ) { 2352 2353 /* 2354 * Read Identify msg to avoid lockup 2355 */ 2356 GET_SBIC_data(regs, newlun); 2357 WAIT_CIP(regs); 2358 newlun &= SBIC_TLUN_MASK; 2359 2360 } else { 2361 2362 /* 2363 * Need to read Identify message the hard way, assuming 2364 * the target even sends us one... 2365 */ 2366 for (newlun = 255; newlun; --newlun) { 2367 GET_SBIC_asr(regs, asr); 2368 if (asr & SBIC_ASR_INT) 2369 break; 2370 delay(10); 2371 } 2372 2373 /* 2374 * If we didn't get an interrupt, somethink's up 2375 */ 2376 if ( (asr & SBIC_ASR_INT) == 0 ) { 2377 printf("%s: Reselect without identify? asr %x\n", 2378 dev->sc_dev.dv_xname, asr); 2379 newlun = 0; /* XXXX */ 2380 } else { 2381 /* 2382 * We got an interrupt, verify that it's a change to 2383 * message in phase, and if so read the message. 2384 */ 2385 GET_SBIC_csr(regs,csr); 2386 2387 if ( csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2388 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2389 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE) ) { 2390 /* 2391 * Yup, gone to message in. Fetch the target LUN 2392 */ 2393 sbicmsgin(dev); 2394 newlun = dev->sc_msg[0] & 0x07; 2395 2396 } else { 2397 /* 2398 * Whoops! Target didn't go to message in phase!! 2399 */ 2400 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2401 newlun = 0; /* XXXSCW */ 2402 } 2403 } 2404 } 2405 2406 /* 2407 * Ok, we have the identity of the reselecting target. 2408 */ 2409 #ifdef DEBUG 2410 if ( reselect_debug > 1 || 2411 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2412 printf("sbicnext: reselect %s from targ %d lun %d\n", 2413 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2414 } 2415 #endif 2416 2417 if ( dev->sc_nexus ) { 2418 /* 2419 * Whoops! We've been reselected with an command in progress! 2420 * The best we can do is to put the current command back on the 2421 * ready list and hope for the best. 2422 */ 2423 #ifdef DEBUG 2424 if ( reselect_debug > 1 ) { 2425 printf("%s: reselect %s with active command\n", 2426 dev->sc_dev.dv_xname, 2427 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2428 } 2429 #endif 2430 2431 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2432 2433 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2434 2435 dev->sc_nexus = NULL; 2436 dev->sc_xs = NULL; 2437 } 2438 2439 /* 2440 * Reload sync values for this target 2441 */ 2442 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2443 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2444 dev->sc_sync[newtarget].period)); 2445 else 2446 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2447 2448 /* 2449 * Loop through the nexus list until we find the saved entry 2450 * for the reselecting target... 2451 */ 2452 for (acb = dev->nexus_list.tqh_first; acb; 2453 acb = acb->chain.tqe_next) { 2454 2455 if ( acb->xs->xs_periph->periph_target == newtarget && 2456 acb->xs->xs_periph->periph_lun == newlun) { 2457 /* 2458 * We've found the saved entry. Dequeue it, and 2459 * make it current again. 2460 */ 2461 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2462 2463 dev->sc_nexus = acb; 2464 dev->sc_xs = acb->xs; 2465 dev->sc_flags |= SBICF_SELECTED; 2466 dev->target = newtarget; 2467 dev->lun = newlun; 2468 break; 2469 } 2470 } 2471 2472 if ( acb == NULL ) { 2473 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2474 dev->sc_dev.dv_xname, 2475 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2476 &dev->nexus_list.tqh_first); 2477 panic("bad reselect in sbic"); 2478 } 2479 2480 if ( csr == SBIC_CSR_RSLT_IFY ) 2481 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2482 } 2483 break; 2484 2485 default: 2486 abort: 2487 { 2488 /* 2489 * Something unexpected happened -- deal with it. 2490 */ 2491 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2492 2493 #ifdef DDB 2494 Debugger(); 2495 #endif 2496 2497 #ifdef DEBUG 2498 dev->sc_dmatimo = 0; 2499 if ( data_pointer_debug > 1 ) 2500 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2501 dev->sc_cur->dc_addr, 2502 dev->sc_tcnt); 2503 #endif 2504 2505 dev->sc_dmastop(dev); 2506 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2507 if ( dev->sc_xs ) sbicerror(dev, csr); 2508 sbicabort(dev, "next"); 2509 2510 if ( dev->sc_flags & SBICF_INDMA ) { 2511 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2512 2513 #ifdef DEBUG 2514 dev->sc_dmatimo = 0; 2515 if ( data_pointer_debug > 1 ) 2516 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2517 dev->sc_cur->dc_addr, 2518 dev->sc_tcnt); 2519 #endif 2520 sbic_scsidone(acb, -1); 2521 } 2522 2523 return SBIC_STATE_ERROR; 2524 } 2525 } 2526 2527 return(SBIC_STATE_RUNNING); 2528 } 2529 2530 2531 /* 2532 * Check if DMA can not be used with specified buffer 2533 */ 2534 int 2535 sbiccheckdmap(bp, len, mask) 2536 void *bp; 2537 u_long len, 2538 mask; 2539 { 2540 u_char *buffer; 2541 u_long phy_buf; 2542 u_long phy_len; 2543 2544 buffer = bp; 2545 2546 if ( len == 0 ) 2547 return(1); 2548 2549 while ( len ) { 2550 2551 phy_buf = kvtop((caddr_t)buffer); 2552 phy_len = PAGE_SIZE - ((int) buffer & PGOFSET); 2553 2554 if ( len < phy_len ) 2555 phy_len = len; 2556 2557 if ( phy_buf & mask ) 2558 return(1); 2559 2560 buffer += phy_len; 2561 len -= phy_len; 2562 } 2563 2564 return(0); 2565 } 2566 2567 int 2568 sbictoscsiperiod(dev, a) 2569 struct sbic_softc *dev; 2570 int a; 2571 { 2572 unsigned int fs; 2573 2574 /* 2575 * cycle = DIV / (2 * CLK) 2576 * DIV = FS + 2 2577 * best we can do is 200ns at 20Mhz, 2 cycles 2578 */ 2579 2580 GET_SBIC_myid(dev->sc_sbicp, fs); 2581 2582 fs = (fs >> 6) + 2; /* DIV */ 2583 2584 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2585 2586 if ( a < 2 ) 2587 a = 8; /* map to Cycles */ 2588 2589 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2590 } 2591 2592 int 2593 sbicfromscsiperiod(dev, p) 2594 struct sbic_softc *dev; 2595 int p; 2596 { 2597 unsigned fs, 2598 ret; 2599 2600 /* 2601 * Just the inverse of the above 2602 */ 2603 GET_SBIC_myid(dev->sc_sbicp, fs); 2604 2605 fs = (fs >> 6) + 2; /* DIV */ 2606 2607 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2608 2609 ret = p << 2; /* in ns units */ 2610 ret = ret / fs; /* in Cycles */ 2611 2612 if ( ret < sbic_min_period ) 2613 return(sbic_min_period); 2614 2615 /* 2616 * verify rounding 2617 */ 2618 if ( sbictoscsiperiod(dev, ret) < p ) 2619 ret++; 2620 2621 return( (ret >= 8) ? 0 : ret ); 2622 } 2623 2624 #ifdef DEBUG 2625 void 2626 sbictimeout(dev) 2627 struct sbic_softc *dev; 2628 { 2629 int s, 2630 asr; 2631 2632 s = splbio(); 2633 2634 if ( dev->sc_dmatimo ) { 2635 2636 if ( dev->sc_dmatimo > 1 ) { 2637 2638 printf("%s: DMA timeout #%d\n", dev->sc_dev.dv_xname, 2639 dev->sc_dmatimo - 1); 2640 2641 GET_SBIC_asr(dev->sc_sbicp, asr); 2642 2643 if ( asr & SBIC_ASR_INT ) { 2644 /* 2645 * We need to service a missed IRQ 2646 */ 2647 sbicintr(dev); 2648 } else { 2649 (void) sbicabort(dev, "timeout"); 2650 splx(s); 2651 return; 2652 } 2653 } 2654 2655 dev->sc_dmatimo++; 2656 } 2657 2658 splx(s); 2659 2660 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 2661 } 2662 #endif 2663
Indexes created Sat Sep 27 21:09:56 GMT 2025