sbic.c revision 1.35
1 /* $NetBSD: sbic.c,v 1.35 2018/03/08 03:12:02 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 1996 Steve Woodford 39 * Original Copyright (c) 1994 Christian E. Hopps 40 * 41 * This code is derived from software contributed to Berkeley by 42 * Van Jacobson of Lawrence Berkeley Laboratory. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by the University of 55 * California, Berkeley and its contributors. 56 * 4. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 73 */ 74 75 /* 76 * Steve Woodford (SCW), Apr, 1996 77 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 78 * 79 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 80 * 81 * The original driver used features which required at least a WD33C93A 82 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 83 * 84 * This version of the driver is pretty well generic, so should work with 85 * any flavour of WD33C93 chip. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: sbic.c,v 1.35 2018/03/08 03:12:02 mrg Exp $"); 90 91 #include "opt_ddb.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/device.h> 96 #include <sys/kernel.h> /* For hz */ 97 #include <sys/disklabel.h> 98 #include <sys/buf.h> 99 100 #include <dev/scsipi/scsi_all.h> 101 #include <dev/scsipi/scsipi_all.h> 102 #include <dev/scsipi/scsiconf.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <mvme68k/mvme68k/isr.h> 107 #include <mvme68k/dev/dmavar.h> 108 #include <mvme68k/dev/sbicreg.h> 109 #include <mvme68k/dev/sbicvar.h> 110 111 112 /* 113 * Since I can't find this in any other header files 114 */ 115 #define SCSI_PHASE(reg) (reg&0x07) 116 117 /* 118 * SCSI delays 119 * In u-seconds, primarily for state changes on the SPC. 120 */ 121 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 122 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 123 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 124 125 /* 126 * Convenience macro for waiting for a particular sbic event 127 */ 128 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 129 130 int sbicicmd (struct sbic_softc *, void *, int, void *, int); 131 int sbicgo (struct sbic_softc *, struct scsipi_xfer *); 132 int sbicdmaok (struct sbic_softc *, struct scsipi_xfer *); 133 int sbicwait (sbic_regmap_p, u_char, int , int); 134 int sbiccheckdmap (void *, u_long, u_long); 135 u_char sbicselectbus (struct sbic_softc *); 136 int sbicxfout (sbic_regmap_p, int, void *); 137 int sbicxfin (sbic_regmap_p, int, void *); 138 int sbicfromscsiperiod (struct sbic_softc *, int); 139 int sbictoscsiperiod (struct sbic_softc *, int); 140 int sbicpoll (struct sbic_softc *); 141 int sbicnextstate (struct sbic_softc *, u_char, u_char); 142 int sbicmsgin (struct sbic_softc *); 143 int sbicabort (struct sbic_softc *, const char *); 144 void sbicxfdone (struct sbic_softc *); 145 void sbicerror (struct sbic_softc *, u_char); 146 void sbicreset (struct sbic_softc *); 147 void sbic_scsidone (struct sbic_acb *, int); 148 void sbic_sched (struct sbic_softc *); 149 void sbic_save_ptrs (struct sbic_softc *); 150 void sbic_load_ptrs (struct sbic_softc *); 151 152 /* 153 * Synch xfer parameters, and timing conversions 154 */ 155 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 156 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 157 int sbic_cmd_wait = SBIC_CMD_WAIT; 158 int sbic_data_wait = SBIC_DATA_WAIT; 159 int sbic_init_wait = SBIC_INIT_WAIT; 160 161 /* 162 * was broken before.. now if you want this you get it for all drives 163 * on sbic controllers. 164 */ 165 u_char sbic_inhibit_sync[8]; 166 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 167 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 168 int sbic_parallel_operations = 1; /* Allow command queues */ 169 170 /* 171 * Some useful stuff for debugging purposes 172 */ 173 #ifdef DEBUG 174 int sbicdma_ops = 0; /* total DMA operations */ 175 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 176 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 177 int sbicdma_saves = 0; 178 179 #define QPRINTF(a) if (sbic_debug > 1) printf a 180 181 int sbic_debug = 0; /* Debug all chip related things */ 182 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 183 int reselect_debug = 0; /* Debug all reselection related things */ 184 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 185 186 void sbictimeout(struct sbic_softc *dev); 187 188 #else 189 #define QPRINTF(a) /* */ 190 #endif 191 192 193 /* 194 * default minphys routine for sbic based controllers 195 */ 196 void 197 sbic_minphys(struct buf *bp) 198 { 199 /* 200 * No max transfer at this level. 201 */ 202 minphys(bp); 203 } 204 205 206 /* 207 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 208 */ 209 void 210 sbic_save_ptrs(struct sbic_softc *dev) 211 { 212 sbic_regmap_p regs; 213 struct sbic_acb *acb; 214 int count, asr, s; 215 216 /* 217 * Only need to save pointers if DMA was active... 218 */ 219 if (dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0) 220 return; 221 222 regs = dev->sc_sbicp; 223 224 s = splbio(); 225 226 /* 227 * Wait until WD chip is idle 228 */ 229 do { 230 GET_SBIC_asr(regs, asr); 231 if (asr & SBIC_ASR_DBR) { 232 printf("%s: asr %02x canceled!\n", __func__, asr); 233 splx(s); 234 return; 235 } 236 } while(asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 237 238 239 /* 240 * Save important state. 241 * must be done before dmastop 242 */ 243 acb = dev->sc_nexus; 244 acb->sc_dmacmd = dev->sc_dmacmd; 245 246 /* 247 * Fetch the residual count 248 */ 249 SBIC_TC_GET(regs, count); 250 251 /* 252 * Shut down DMA 253 */ 254 dev->sc_dmastop(dev); 255 256 /* 257 * No longer in DMA 258 */ 259 dev->sc_flags &= ~SBICF_INDMA; 260 261 /* 262 * Ensure the WD chip is back in polled I/O mode, with nothing to 263 * transfer. 264 */ 265 SBIC_TC_PUT(regs, 0); 266 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 267 268 /* 269 * Update current count... 270 */ 271 acb->sc_tcnt = count; 272 273 /* 274 * Work out how many bytes were actually transferred 275 */ 276 count = dev->sc_tcnt - count; 277 dev->sc_tcnt = acb->sc_tcnt; 278 279 /* 280 * Fixup partial xfers 281 */ 282 acb->sc_kv.dc_addr += count; 283 acb->sc_kv.dc_count -= count; 284 acb->sc_pa.dc_addr += count; 285 acb->sc_pa.dc_count -= count >> 1; 286 287 #ifdef DEBUG 288 if (data_pointer_debug) 289 printf("save at (%p,%x):%x\n", 290 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 291 sbicdma_saves++; 292 #endif 293 294 splx(s); 295 } 296 297 298 /* 299 * DOES NOT RESTART DMA!!! 300 */ 301 void 302 sbic_load_ptrs(struct sbic_softc *dev) 303 { 304 struct sbic_acb *acb = dev->sc_nexus; 305 int s; 306 307 if (acb->sc_kv.dc_count == 0) { 308 /* 309 * No data to xfer 310 */ 311 return; 312 } 313 314 s = splbio(); 315 316 /* 317 * Reset the Scatter-Gather chain 318 */ 319 dev->sc_last = dev->sc_cur = &acb->sc_pa; 320 321 /* 322 * Restore the Transfer Count and DMA specific data 323 */ 324 dev->sc_tcnt = acb->sc_tcnt; 325 dev->sc_dmacmd = acb->sc_dmacmd; 326 327 #ifdef DEBUG 328 sbicdma_ops++; 329 #endif 330 331 /* 332 * Need to fixup new segment? 333 */ 334 if (dev->sc_tcnt == 0) { 335 /* 336 * sc_tcnt == 0 implies end of segment 337 */ 338 char *vaddr, *paddr; 339 int count; 340 341 /* 342 * do kvm to pa mappings 343 */ 344 vaddr = acb->sc_kv.dc_addr; 345 paddr = acb->sc_pa.dc_addr = (char *)kvtop((void *)vaddr); 346 347 for (count = (PAGE_SIZE - ((int)vaddr & PGOFSET)); 348 count < acb->sc_kv.dc_count && 349 (char *)kvtop((void *)(vaddr + count + 4)) == 350 paddr + count + 4; 351 count += PAGE_SIZE) 352 ; /* Do nothing */ 353 354 /* 355 * If it's all contiguous... 356 */ 357 if (count > acb->sc_kv.dc_count) { 358 count = acb->sc_kv.dc_count; 359 #ifdef DEBUG 360 sbicdma_hits++; 361 #endif 362 } 363 #ifdef DEBUG 364 else 365 sbicdma_misses++; 366 #endif 367 368 acb->sc_tcnt = count; 369 acb->sc_pa.dc_count = count >> 1; 370 371 #ifdef DEBUG 372 if (data_pointer_debug) 373 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 374 acb->sc_kv.dc_addr, 375 acb->sc_kv.dc_count, 376 acb->sc_pa.dc_addr, 377 acb->sc_tcnt); 378 #endif 379 380 } 381 382 splx(s); 383 } 384 385 /* 386 * used by specific sbic controller 387 * 388 * it appears that the higher level code does nothing with LUN's 389 * so I will too. I could plug it in, however so could they 390 * in scsi_scsipi_cmd(). 391 */ 392 void 393 sbic_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 394 void *arg) 395 { 396 struct scsipi_xfer *xs; 397 struct scsipi_periph *periph; 398 struct sbic_softc *dev = device_private(chan->chan_adapter->adapt_dev); 399 struct sbic_acb *acb; 400 int flags, s; 401 402 switch (req) { 403 case ADAPTER_REQ_RUN_XFER: 404 xs = arg; 405 periph = xs->xs_periph; 406 flags = xs->xs_control; 407 408 if (flags & XS_CTL_DATA_UIO) 409 panic("sbic: scsi data uio requested"); 410 411 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 412 panic("sbic_scsicmd: busy"); 413 414 s = splbio(); 415 416 if ((acb = dev->free_list.tqh_first) != NULL) 417 TAILQ_REMOVE(&dev->free_list, acb, chain); 418 419 splx(s); 420 421 if (acb == NULL) { 422 #ifdef DEBUG 423 printf("%s: unable to queue request for target %d\n", 424 __func__, periph->periph_target); 425 #ifdef DDB 426 Debugger(); 427 #endif 428 #endif 429 xs->error = XS_RESOURCE_SHORTAGE; 430 scsipi_done(xs); 431 return; 432 } 433 434 if (flags & XS_CTL_DATA_IN) 435 acb->flags = ACB_ACTIVE | ACB_DATAIN; 436 else 437 acb->flags = ACB_ACTIVE; 438 439 acb->xs = xs; 440 acb->clen = xs->cmdlen; 441 acb->sc_kv.dc_addr = xs->data; 442 acb->sc_kv.dc_count = xs->datalen; 443 acb->pa_addr = xs->data ? 444 (char *)kvtop((void *)xs->data) : 0; 445 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 446 447 if (flags & XS_CTL_POLL) { 448 /* 449 * This has major side effects 450 * -- it locks up the machine 451 */ 452 int stat; 453 454 s = splbio(); 455 456 dev->sc_flags |= SBICF_ICMD; 457 458 do { 459 /* 460 * If we already had a nexus, while away 461 * the time until idle... 462 * This is likely only to happen if 463 * a reselection occurs between 464 * here and our earlier check for 465 * ICMD && sc_nexus(which would 466 * have resulted in a panic() had it been true). 467 */ 468 while (dev->sc_nexus) 469 sbicpoll(dev); 470 471 /* 472 * Fix up the new nexus 473 */ 474 dev->sc_nexus = acb; 475 dev->sc_xs = xs; 476 dev->target = periph->periph_target; 477 dev->lun = periph->periph_lun; 478 479 stat = sbicicmd(dev, &acb->cmd, acb->clen, 480 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 481 482 } while (dev->sc_nexus != acb); 483 484 sbic_scsidone(acb, stat); 485 486 splx(s); 487 488 return; 489 } 490 491 s = splbio(); 492 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 493 494 /* 495 * If nothing is active, try to start it now. 496 */ 497 if (dev->sc_nexus == NULL) 498 sbic_sched(dev); 499 500 splx(s); 501 502 return; 503 504 case ADAPTER_REQ_GROW_RESOURCES: 505 /* XXX Not supported. */ 506 return; 507 508 case ADAPTER_REQ_SET_XFER_MODE: 509 /* XXX Not supported. */ 510 return; 511 } 512 } 513 514 /* 515 * attempt to start the next available command 516 */ 517 void 518 sbic_sched(struct sbic_softc *dev) 519 { 520 struct scsipi_xfer *xs; 521 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 522 struct sbic_acb *acb; 523 int flags, stat; 524 525 /* 526 * XXXSCW 527 * I'll keep this test here, even though I can't see any obvious way 528 * in which sbic_sched() could be called with sc_nexus non NULL 529 */ 530 if (dev->sc_nexus) 531 return; /* a command is current active */ 532 533 /* 534 * Loop through the ready list looking for work to do... 535 */ 536 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 537 int i, j; 538 539 periph = acb->xs->xs_periph; 540 i = periph->periph_target; 541 j = 1 << periph->periph_lun; 542 543 /* 544 * We've found a potential command, but is the target/lun busy? 545 */ 546 if ((dev->sc_tinfo[i].lubusy & j) == 0) { 547 /* 548 * Nope, it's not busy, so we can use it. 549 */ 550 dev->sc_tinfo[i].lubusy |= j; 551 TAILQ_REMOVE(&dev->ready_list, acb, chain); 552 dev->sc_nexus = acb; 553 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 554 break; 555 } 556 } 557 558 if (acb == NULL) { 559 QPRINTF(("sbicsched: no work\n")); 560 return; /* did not find an available command */ 561 } 562 563 #ifdef DEBUG 564 if (data_pointer_debug > 1) 565 printf("sbic_sched(%d,%d)\n", periph->periph_target, 566 periph->periph_lun); 567 #endif 568 569 dev->sc_xs = xs = acb->xs; 570 flags = xs->xs_control; 571 572 if (flags & XS_CTL_RESET) 573 sbicreset(dev); 574 575 dev->sc_stat[0] = -1; 576 dev->target = periph->periph_target; 577 dev->lun = periph->periph_lun; 578 579 if (flags & XS_CTL_POLL || (!sbic_parallel_operations && 580 (sbicdmaok(dev, xs) == 0)) ) 581 stat = sbicicmd(dev, &acb->cmd, acb->clen, 582 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 583 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) 584 return; 585 else 586 stat = dev->sc_stat[0]; 587 588 sbic_scsidone(acb, stat); 589 } 590 591 void 592 sbic_scsidone(struct sbic_acb *acb, int stat) 593 { 594 struct scsipi_xfer *xs = acb->xs; 595 struct scsipi_periph *periph = xs->xs_periph; 596 struct sbic_softc *dev = 597 device_private(periph->periph_channel->chan_adapter->adapt_dev); 598 int dosched = 0; 599 600 #ifdef DIAGNOSTIC 601 if (acb == NULL || xs == NULL) { 602 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", 603 dev->target, dev->lun); 604 #ifdef DDB 605 Debugger(); 606 #endif 607 return; 608 } 609 #endif 610 611 612 #ifdef DEBUG 613 if (data_pointer_debug > 1) 614 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 615 periph->periph_target, periph->periph_lun, 616 dev->target, dev->lun, stat); 617 618 if (xs->xs_periph->periph_target == dev->sc_channel.chan_id) 619 panic("target == hostid"); 620 #endif 621 622 xs->status = stat; 623 xs->resid = 0; /* XXXX */ 624 if (xs->error == XS_NOERROR) { 625 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 626 xs->error = XS_BUSY; 627 } 628 629 630 /* 631 * Remove the ACB from whatever queue it's on. We have to do a bit of 632 * a hack to figure out which queue it's on. Note that it is *not* 633 * necessary to cdr down the ready queue, but we must cdr down the 634 * nexus queue and see if it's there, so we can mark the unit as no 635 * longer busy. This code is sickening, but it works. 636 */ 637 if (acb == dev->sc_nexus ) { 638 639 dev->sc_nexus = NULL; 640 dev->sc_xs = NULL; 641 642 dev->sc_tinfo[periph->periph_target].lubusy &= 643 ~(1 << periph->periph_lun); 644 645 if (dev->ready_list.tqh_first) 646 dosched = 1; /* start next command */ 647 648 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 649 650 TAILQ_REMOVE(&dev->ready_list, acb, chain); 651 652 } else { 653 654 struct sbic_acb *a; 655 656 for (a = dev->nexus_list.tqh_first; a != NULL; 657 a = a->chain.tqe_next) { 658 if (a == acb) { 659 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 660 dev->sc_tinfo[periph->periph_target].lubusy &= 661 ~(1 << periph->periph_lun); 662 break; 663 } 664 } 665 666 if (a != NULL) 667 ; 668 else if ( acb->chain.tqe_next ) { 669 TAILQ_REMOVE(&dev->ready_list, acb, chain); 670 } else { 671 printf("%s: can't find matching acb\n", 672 device_xname(dev->sc_dev)); 673 #ifdef DDB 674 Debugger(); 675 #endif 676 } 677 } 678 679 /* 680 * Put it on the free list. 681 */ 682 acb->flags = ACB_FREE; 683 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 684 685 dev->sc_tinfo[periph->periph_target].cmds++; 686 687 scsipi_done(xs); 688 689 if (dosched) 690 sbic_sched(dev); 691 } 692 693 int 694 sbicdmaok(struct sbic_softc *dev, struct scsipi_xfer *xs) 695 { 696 697 if (sbic_no_dma || xs->datalen == 0 || 698 xs->datalen & 0x03 || (int)xs->data & 0x03) 699 return 0; 700 701 /* 702 * controller supports DMA to any addresses? 703 */ 704 if ((dev->sc_flags & SBICF_BADDMA) == 0) 705 return 1; 706 707 /* 708 * this address is ok for DMA? 709 */ 710 if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 711 return 1; 712 713 return 0; 714 } 715 716 int 717 sbicwait(sbic_regmap_p regs, u_char until, int timeo, int line) 718 { 719 u_char val; 720 721 if (timeo == 0) 722 timeo = 1000000; /* some large value.. */ 723 724 GET_SBIC_asr(regs, val); 725 726 while ((val & until) == 0) { 727 728 if (timeo-- == 0) { 729 int csr; 730 GET_SBIC_csr(regs, csr); 731 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 732 line, val, csr); 733 #if defined(DDB) && defined(DEBUG) 734 Debugger(); 735 #endif 736 return val; /* Maybe I should abort */ 737 break; 738 } 739 740 DELAY(1); 741 GET_SBIC_asr(regs, val); 742 } 743 744 return val; 745 } 746 747 int 748 sbicabort(struct sbic_softc *dev, const char *where) 749 { 750 sbic_regmap_p regs = dev->sc_sbicp; 751 u_char csr, asr; 752 753 GET_SBIC_asr(regs, asr); 754 GET_SBIC_csr(regs, csr); 755 756 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 757 device_xname(dev->sc_dev), where, csr, asr); 758 759 /* 760 * Clean up chip itself 761 */ 762 if (dev->sc_flags & SBICF_SELECTED) { 763 764 while (asr & SBIC_ASR_DBR) { 765 /* 766 * sbic is jammed w/data. need to clear it 767 * But we don't know what direction it needs to go 768 */ 769 GET_SBIC_data(regs, asr); 770 printf("%s: abort %s: clearing data buffer 0x%02x\n", 771 device_xname(dev->sc_dev), where, asr); 772 GET_SBIC_asr(regs, asr); 773 if (asr & SBIC_ASR_DBR) 774 /* Not the read direction, then */ 775 SET_SBIC_data(regs, asr); 776 GET_SBIC_asr(regs, asr); 777 } 778 779 WAIT_CIP(regs); 780 781 printf("%s: sbicabort - sending ABORT command\n", 782 device_xname(dev->sc_dev)); 783 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 784 WAIT_CIP(regs); 785 786 GET_SBIC_asr(regs, asr); 787 788 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 789 /* 790 * ok, get more drastic.. 791 */ 792 printf("%s: sbicabort - asr %x, trying to reset\n", 793 device_xname(dev->sc_dev), asr); 794 sbicreset(dev); 795 dev->sc_flags &= ~SBICF_SELECTED; 796 return SBIC_STATE_ERROR; 797 } 798 799 printf("%s: sbicabort - sending DISC command\n", 800 device_xname(dev->sc_dev)); 801 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 802 803 do { 804 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 805 GET_SBIC_asr(regs, asr); 806 GET_SBIC_csr (regs, csr); 807 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 808 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 809 (csr != SBIC_CSR_CMD_INVALID)); 810 811 /* 812 * lets just hope it worked.. 813 */ 814 dev->sc_flags &= ~SBICF_SELECTED; 815 } 816 817 return SBIC_STATE_ERROR; 818 } 819 820 821 /* 822 * Initialize driver-private structures 823 */ 824 void 825 sbicinit(struct sbic_softc *dev) 826 { 827 u_int i; 828 829 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 830 831 struct sbic_acb *acb; 832 833 TAILQ_INIT(&dev->ready_list); 834 TAILQ_INIT(&dev->nexus_list); 835 TAILQ_INIT(&dev->free_list); 836 callout_init(&dev->sc_timo_ch, 0); 837 838 dev->sc_nexus = NULL; 839 dev->sc_xs = NULL; 840 841 acb = dev->sc_acb; 842 memset(acb, 0, sizeof(dev->sc_acb)); 843 844 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 845 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 846 acb++; 847 } 848 849 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 850 851 #ifdef DEBUG 852 /* 853 * make sure timeout is really not needed 854 */ 855 callout_reset(&dev->sc_timo_ch, 30 * hz, 856 (void *)sbictimeout, dev); 857 #endif 858 859 } else 860 panic("sbic: reinitializing driver!"); 861 862 dev->sc_flags |= SBICF_ALIVE; 863 dev->sc_flags &= ~SBICF_SELECTED; 864 865 /* 866 * initialize inhibit array 867 * Never enable Sync, since it just doesn't work on mvme147 :( 868 */ 869 for (i = 0; i < 8; ++i) 870 sbic_inhibit_sync[i] = 1; 871 872 sbicreset(dev); 873 } 874 875 void 876 sbicreset(struct sbic_softc *dev) 877 { 878 sbic_regmap_p regs = dev->sc_sbicp; 879 u_int my_id, s; 880 u_char csr; 881 882 s = splbio(); 883 884 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 885 886 if (dev->sc_clkfreq < 110) 887 my_id |= SBIC_ID_FS_8_10; 888 else if (dev->sc_clkfreq < 160) 889 my_id |= SBIC_ID_FS_12_15; 890 else if (dev->sc_clkfreq < 210) 891 my_id |= SBIC_ID_FS_16_20; 892 893 SET_SBIC_myid(regs, my_id); 894 895 /* 896 * Reset the chip 897 */ 898 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 899 DELAY(25); 900 901 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 902 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 903 __USE(csr); 904 905 /* 906 * Set up various chip parameters 907 */ 908 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 909 910 /* 911 * don't allow Selection (SBIC_RID_ES) 912 * until we can handle target mode!! 913 */ 914 SET_SBIC_rselid(regs, SBIC_RID_ER); 915 916 /* 917 * Asynchronous for now 918 */ 919 SET_SBIC_syn(regs, 0); 920 921 /* 922 * Anything else was zeroed by reset 923 */ 924 splx(s); 925 926 dev->sc_flags &= ~SBICF_SELECTED; 927 } 928 929 void 930 sbicerror(struct sbic_softc *dev, u_char csr) 931 { 932 struct scsipi_xfer *xs = dev->sc_xs; 933 934 #ifdef DIAGNOSTIC 935 if (xs == NULL) 936 panic("sbicerror: dev->sc_xs == NULL"); 937 #endif 938 939 if ( xs->xs_control & XS_CTL_SILENT ) 940 return; 941 942 printf("%s: csr == 0x%02x\n", device_xname(dev->sc_dev), csr); 943 } 944 945 /* 946 * select the bus, return when selected or error. 947 * 948 * Returns the current CSR following selection and optionally MSG out phase. 949 * i.e. the returned CSR *should* indicate CMD phase... 950 * If the return value is 0, some error happened. 951 */ 952 u_char 953 sbicselectbus(struct sbic_softc *dev) 954 { 955 sbic_regmap_p regs = dev->sc_sbicp; 956 u_char target = dev->target, lun = dev->lun, asr, csr, id; 957 958 /* 959 * if we're already selected, return (XXXX panic maybe?) 960 */ 961 if (dev->sc_flags & SBICF_SELECTED) 962 return 0; 963 964 QPRINTF(("sbicselectbus %d: ", target)); 965 966 /* 967 * issue select 968 */ 969 SET_SBIC_selid(regs, target); 970 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 971 972 GET_SBIC_asr(regs, asr); 973 974 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 975 /* 976 * This means we got ourselves reselected upon 977 */ 978 QPRINTF(("WD busy (reselect?)\n")); 979 return 0; 980 } 981 982 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 983 984 /* 985 * wait for select (merged from separate function may need 986 * cleanup) 987 */ 988 WAIT_CIP(regs); 989 990 do { 991 992 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 993 994 if (asr & SBIC_ASR_LCI) { 995 QPRINTF(("late LCI: asr %02x\n", asr)); 996 return 0; 997 } 998 999 /* 1000 * Clear interrupt 1001 */ 1002 GET_SBIC_csr (regs, csr); 1003 1004 QPRINTF(("%02x ", csr)); 1005 1006 /* 1007 * Reselected from under our feet? 1008 */ 1009 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1010 QPRINTF(("got reselected, asr %02x\n", asr)); 1011 /* 1012 * We need to handle this now so we don't lock up later 1013 */ 1014 sbicnextstate(dev, csr, asr); 1015 1016 return 0; 1017 } 1018 1019 /* 1020 * Whoops! 1021 */ 1022 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1023 panic("sbicselectbus: target issued select!"); 1024 return 0; 1025 } 1026 1027 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1028 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1029 csr != SBIC_CSR_SEL_TIMEO); 1030 1031 /* 1032 * Anyone at home? 1033 */ 1034 if (csr == SBIC_CSR_SEL_TIMEO) { 1035 dev->sc_xs->error = XS_SELTIMEOUT; 1036 QPRINTF(("Selection Timeout\n")); 1037 return 0; 1038 } 1039 1040 QPRINTF(("Selection Complete\n")); 1041 1042 /* 1043 * Assume we're now selected 1044 */ 1045 GET_SBIC_selid(regs, id); 1046 dev->target = id; 1047 dev->lun = lun; 1048 dev->sc_flags |= SBICF_SELECTED; 1049 1050 /* 1051 * Enable (or not) reselection 1052 * XXXSCW This is probably not necessary since we don't use use the 1053 * Select-and-Xfer-with-ATN command to initiate a selection... 1054 */ 1055 if (!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1056 SET_SBIC_rselid (regs, 0); 1057 else 1058 SET_SBIC_rselid (regs, SBIC_RID_ER); 1059 1060 /* 1061 * We only really need to do anything when the target goes to MSG out 1062 * If the device ignored ATN, it's probably old and brain-dead, 1063 * but we'll try to support it anyhow. 1064 * If it doesn't support message out, it definately doesn't 1065 * support synchronous transfers, so no point in even asking... 1066 */ 1067 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1068 /* 1069 * Send identify message (SCSI-2 requires an identify msg) 1070 */ 1071 if (sbic_inhibit_sync[id] && 1072 dev->sc_sync[id].state == SYNC_START) { 1073 /* 1074 * Handle drives that don't want to be asked 1075 * whether to go sync at all. 1076 */ 1077 dev->sc_sync[id].offset = 0; 1078 dev->sc_sync[id].period = sbic_min_period; 1079 dev->sc_sync[id].state = SYNC_DONE; 1080 } 1081 1082 /* 1083 * Do we need to negotiate Synchronous Xfers for this target? 1084 */ 1085 if (dev->sc_sync[id].state != SYNC_START) { 1086 /* 1087 * Nope, we've already negotiated. 1088 * Now see if we should allow the target to 1089 * disconnect/reselect... 1090 */ 1091 if (dev->sc_xs->xs_control & XS_CTL_POLL || 1092 dev->sc_flags & SBICF_ICMD || 1093 !sbic_enable_reselect) 1094 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1095 else 1096 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1097 1098 } else { 1099 /* 1100 * try to initiate a sync transfer. 1101 * So compose the sync message we're going 1102 * to send to the target 1103 */ 1104 #ifdef DEBUG 1105 if (sync_debug) 1106 printf("\nSending sync request " 1107 "to target %d ... ", id); 1108 #endif 1109 /* 1110 * setup scsi message sync message request 1111 */ 1112 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1113 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1114 dev->sc_msg[2] = 3; 1115 dev->sc_msg[3] = MSG_SYNC_REQ; 1116 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1117 dev->sc_msg[5] = sbic_max_offset; 1118 1119 sbicxfout(regs, 6, dev->sc_msg); 1120 1121 dev->sc_sync[id].state = SYNC_SENT; 1122 #ifdef DEBUG 1123 if (sync_debug) 1124 printf ("sent\n"); 1125 #endif 1126 } 1127 1128 /* 1129 * There's one interrupt still to come: the change to 1130 * CMD phase... 1131 */ 1132 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1133 GET_SBIC_csr(regs, csr); 1134 } 1135 1136 /* 1137 * set sync or async 1138 */ 1139 if (dev->sc_sync[target].state == SYNC_DONE) { 1140 #ifdef DEBUG 1141 if (sync_debug) 1142 printf("select(%d): sync reg = 0x%02x\n", target, 1143 SBIC_SYN(dev->sc_sync[target].offset, 1144 dev->sc_sync[target].period)); 1145 #endif 1146 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1147 dev->sc_sync[target].period)); 1148 } else { 1149 #ifdef DEBUG 1150 if (sync_debug) 1151 printf("select(%d): sync reg = 0x%02x\n", target, 1152 SBIC_SYN(0,sbic_min_period)); 1153 #endif 1154 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1155 } 1156 1157 return csr; 1158 } 1159 1160 /* 1161 * Information Transfer *to* a Scsi Target. 1162 * 1163 * Note: Don't expect there to be an interrupt immediately after all 1164 * the data is transferred out. The WD spec sheet says that the Transfer- 1165 * Info command for non-MSG_IN phases only completes when the target 1166 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1167 * 1168 * This can have a nasty effect on commands which take a relatively long 1169 * time to complete, for example a START/STOP unit command may remain in 1170 * CMD phase until the disk has spun up. Only then will the target change 1171 * to STATUS phase. This is really only a problem for immediate commands 1172 * since we don't allow disconnection for them (yet). 1173 */ 1174 int 1175 sbicxfout(sbic_regmap_p regs, int len, void *bp) 1176 { 1177 int wait = sbic_data_wait; 1178 u_char asr, *buf = bp; 1179 1180 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1181 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1182 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1183 1184 /* 1185 * sigh.. WD-PROTO strikes again.. sending the command in one go 1186 * causes the chip to lock up if talking to certain (misbehaving?) 1187 * targets. Anyway, this procedure should work for all targets, but 1188 * it's slightly slower due to the overhead 1189 */ 1190 WAIT_CIP (regs); 1191 1192 SBIC_TC_PUT (regs, 0); 1193 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1194 SBIC_TC_PUT (regs, (unsigned)len); 1195 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1196 1197 /* 1198 * Loop for each byte transferred 1199 */ 1200 do { 1201 1202 GET_SBIC_asr(regs, asr); 1203 1204 if (asr & SBIC_ASR_DBR) { 1205 if (len) { 1206 SET_SBIC_data (regs, *buf); 1207 buf++; 1208 len--; 1209 } else { 1210 SET_SBIC_data (regs, 0); 1211 } 1212 wait = sbic_data_wait; 1213 } 1214 1215 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1216 1217 #ifdef DEBUG 1218 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1219 #endif 1220 1221 /* 1222 * Normally, an interrupt will be pending when this routing returns. 1223 */ 1224 return len; 1225 } 1226 1227 /* 1228 * Information Transfer *from* a Scsi Target 1229 * returns # bytes left to read 1230 */ 1231 int 1232 sbicxfin(sbic_regmap_p regs, int len, void *bp) 1233 { 1234 int wait = sbic_data_wait; 1235 u_char *buf = bp; 1236 u_char asr; 1237 #ifdef DEBUG 1238 u_char *obp = bp; 1239 #endif 1240 1241 WAIT_CIP(regs); 1242 1243 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1244 SBIC_TC_PUT(regs, (unsigned int)len); 1245 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1246 1247 /* 1248 * Loop for each byte transferred 1249 */ 1250 do { 1251 1252 GET_SBIC_asr(regs, asr); 1253 1254 if (asr & SBIC_ASR_DBR) { 1255 if (len) { 1256 GET_SBIC_data (regs, *buf); 1257 buf++; 1258 len--; 1259 } else { 1260 u_char foo; 1261 GET_SBIC_data (regs, foo); 1262 __USE(foo); 1263 } 1264 wait = sbic_data_wait; 1265 } 1266 1267 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1268 1269 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1270 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1271 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1272 1273 SBIC_TC_PUT (regs, 0); 1274 1275 /* 1276 * this leaves with one csr to be read 1277 */ 1278 return len; 1279 } 1280 1281 /* 1282 * SCSI 'immediate' command: issue a command to some SCSI device 1283 * and get back an 'immediate' response (i.e., do programmed xfer 1284 * to get the response data). 'cbuf' is a buffer containing a scsi 1285 * command of length clen bytes. 'buf' is a buffer of length 'len' 1286 * bytes for data. The transfer direction is determined by the device 1287 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1288 * command must supply no data. 1289 * 1290 * Note that although this routine looks like it can handle disconnect/ 1291 * reselect, the fact is that it can't. There is still some work to be 1292 * done to clean this lot up. 1293 */ 1294 int 1295 sbicicmd(struct sbic_softc *dev, void *cbuf, int clen, void *buf, int len) 1296 { 1297 sbic_regmap_p regs = dev->sc_sbicp; 1298 struct sbic_acb *acb = dev->sc_nexus; 1299 u_char csr, asr; 1300 int still_busy = SBIC_STATE_RUNNING; 1301 1302 /* 1303 * Make sure pointers are OK 1304 */ 1305 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1306 dev->sc_tcnt = acb->sc_tcnt = 0; 1307 1308 acb->sc_dmacmd = 0; 1309 acb->sc_pa.dc_count = 0; /* No DMA */ 1310 acb->sc_kv.dc_addr = buf; 1311 acb->sc_kv.dc_count = len; 1312 1313 #ifdef DEBUG 1314 if (data_pointer_debug > 1) 1315 printf("sbicicmd(%d,%d):%d\n", 1316 dev->target, dev->lun, acb->sc_kv.dc_count); 1317 #endif 1318 1319 /* 1320 * set the sbic into non-DMA mode 1321 */ 1322 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1323 1324 dev->sc_stat[0] = 0xff; 1325 dev->sc_msg[0] = 0xff; 1326 1327 /* 1328 * We're stealing the SCSI bus 1329 */ 1330 dev->sc_flags |= SBICF_ICMD; 1331 1332 do { 1333 GET_SBIC_asr(regs, asr); 1334 1335 /* 1336 * select the SCSI bus (it's an error if bus isn't free) 1337 */ 1338 if ((dev->sc_flags & SBICF_SELECTED) == 0 && 1339 still_busy != SBIC_STATE_DISCONNECT) { 1340 if ((csr = sbicselectbus(dev)) == 0) { 1341 dev->sc_flags &= ~SBICF_ICMD; 1342 return -1; 1343 } 1344 } else if ((asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == 1345 SBIC_ASR_INT) 1346 GET_SBIC_csr(regs, csr); 1347 else 1348 csr = 0; 1349 1350 if (csr) { 1351 1352 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1353 1354 switch (csr) { 1355 1356 case SBIC_CSR_S_XFERRED: 1357 case SBIC_CSR_DISC: 1358 case SBIC_CSR_DISC_1: 1359 { 1360 u_char phase; 1361 1362 dev->sc_flags &= ~SBICF_SELECTED; 1363 GET_SBIC_cmd_phase(regs, phase); 1364 1365 if (phase == 0x60) { 1366 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1367 still_busy = SBIC_STATE_DONE; /* done */ 1368 } else { 1369 #ifdef DEBUG 1370 if (reselect_debug > 1) 1371 printf("sbicicmd: " 1372 "handling disconnect\n"); 1373 #endif 1374 still_busy = SBIC_STATE_DISCONNECT; 1375 } 1376 break; 1377 } 1378 1379 case SBIC_CSR_XFERRED | CMD_PHASE: 1380 case SBIC_CSR_MIS | CMD_PHASE: 1381 case SBIC_CSR_MIS_1 | CMD_PHASE: 1382 case SBIC_CSR_MIS_2 | CMD_PHASE: 1383 1384 if (sbicxfout(regs, clen, cbuf)) 1385 still_busy = sbicabort(dev, 1386 "icmd sending cmd"); 1387 break; 1388 1389 case SBIC_CSR_XFERRED | STATUS_PHASE: 1390 case SBIC_CSR_MIS | STATUS_PHASE: 1391 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1392 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1393 1394 /* 1395 * The sbic does the status/cmd-complete 1396 * reading ok, so do this with its 1397 * hi-level commands. 1398 */ 1399 #ifdef DEBUG 1400 if (sbic_debug) 1401 printf("SBICICMD status phase " 1402 "(bsy=%d)\n", still_busy); 1403 #endif 1404 SET_SBIC_cmd_phase(regs, 0x46); 1405 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1406 break; 1407 1408 default: 1409 still_busy = sbicnextstate(dev, csr, asr); 1410 break; 1411 } 1412 1413 /* 1414 * make sure the last command was taken, 1415 * ie. we're not hunting after an ignored command.. 1416 */ 1417 GET_SBIC_asr(regs, asr); 1418 1419 /* 1420 * tapes may take a loooong time.. 1421 */ 1422 while (asr & SBIC_ASR_BSY) { 1423 1424 if (asr & SBIC_ASR_DBR) { 1425 int i; 1426 1427 printf("sbicicmd: " 1428 "Waiting while sbic is jammed, " 1429 "CSR:%02x,ASR:%02x\n", csr, asr); 1430 #ifdef DDB 1431 Debugger(); 1432 #endif 1433 /* 1434 * SBIC is jammed 1435 * DUNNO which direction 1436 * Try old direction 1437 */ 1438 GET_SBIC_data(regs, i); 1439 GET_SBIC_asr(regs, asr); 1440 1441 if (asr & SBIC_ASR_DBR) 1442 /* Wants us to write */ 1443 SET_SBIC_data(regs, i); 1444 } 1445 1446 GET_SBIC_asr(regs, asr); 1447 } 1448 } 1449 1450 /* 1451 * wait for last command to complete 1452 */ 1453 if (asr & SBIC_ASR_LCI) { 1454 printf("sbicicmd: last command ignored\n"); 1455 } else if (still_busy >= SBIC_STATE_RUNNING) /* Bsy */ 1456 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1457 1458 /* 1459 * do it again 1460 */ 1461 } while (still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff); 1462 1463 /* 1464 * Sometimes we need to do an extra read of the CSR 1465 */ 1466 GET_SBIC_csr(regs, csr); 1467 1468 #ifdef DEBUG 1469 if (data_pointer_debug > 1) 1470 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1471 acb->sc_kv.dc_count, dev->sc_stat[0]); 1472 #endif 1473 1474 dev->sc_flags &= ~SBICF_ICMD; 1475 1476 return dev->sc_stat[0]; 1477 } 1478 1479 /* 1480 * Finish SCSI xfer command: After the completion interrupt from 1481 * a read/write operation, sequence through the final phases in 1482 * programmed i/o. This routine is a lot like sbicicmd except we 1483 * skip (and don't allow) the select, cmd out and data in/out phases. 1484 */ 1485 void 1486 sbicxfdone(struct sbic_softc *dev) 1487 { 1488 sbic_regmap_p regs = dev->sc_sbicp; 1489 u_char phase, csr; 1490 int s; 1491 1492 QPRINTF(("{")); 1493 s = splbio(); 1494 1495 /* 1496 * have the sbic complete on its own 1497 */ 1498 SBIC_TC_PUT(regs, 0); 1499 SET_SBIC_cmd_phase(regs, 0x46); 1500 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1501 1502 do { 1503 1504 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1505 GET_SBIC_csr(regs, csr); 1506 QPRINTF(("%02x:", csr)); 1507 1508 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1509 (csr != SBIC_CSR_S_XFERRED)); 1510 1511 dev->sc_flags &= ~SBICF_SELECTED; 1512 1513 GET_SBIC_cmd_phase (regs, phase); 1514 QPRINTF(("}%02x", phase)); 1515 1516 if (phase == 0x60) 1517 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1518 else 1519 sbicerror(dev, csr); 1520 1521 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1522 1523 splx(s); 1524 } 1525 1526 /* 1527 * No DMA chains 1528 */ 1529 int 1530 sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1531 { 1532 struct sbic_acb *acb = dev->sc_nexus; 1533 sbic_regmap_p regs = dev->sc_sbicp; 1534 int i, dmaflags, count, usedma; 1535 u_char csr, asr, *addr; 1536 1537 dev->target = xs->xs_periph->periph_target; 1538 dev->lun = xs->xs_periph->periph_lun; 1539 1540 usedma = sbicdmaok(dev, xs); 1541 1542 #ifdef DEBUG 1543 if (data_pointer_debug > 1) 1544 printf("sbicgo(%d,%d): usedma=%d\n", 1545 dev->target, dev->lun, usedma); 1546 #endif 1547 1548 /* 1549 * select the SCSI bus (it's an error if bus isn't free) 1550 */ 1551 if ((csr = sbicselectbus(dev)) == 0) 1552 return 0; /* Not done: needs to be rescheduled */ 1553 1554 dev->sc_stat[0] = 0xff; 1555 1556 /* 1557 * Calculate DMA chains now 1558 */ 1559 if (acb->flags & ACB_DATAIN) 1560 dmaflags = DMAGO_READ; 1561 else 1562 dmaflags = 0; 1563 1564 addr = acb->sc_kv.dc_addr; 1565 count = acb->sc_kv.dc_count; 1566 1567 if (count && ((char *)kvtop((void *)addr) != acb->sc_pa.dc_addr)) { 1568 printf("sbic: DMA buffer mapping changed %p->%x\n", 1569 acb->sc_pa.dc_addr, kvtop((void *)addr)); 1570 #ifdef DDB 1571 Debugger(); 1572 #endif 1573 } 1574 1575 #ifdef DEBUG 1576 ++sbicdma_ops; /* count total DMA operations */ 1577 #endif 1578 1579 /* 1580 * Allocate the DMA chain 1581 * Mark end of segment... 1582 */ 1583 acb->sc_tcnt = dev->sc_tcnt = 0; 1584 acb->sc_pa.dc_count = 0; 1585 1586 sbic_load_ptrs(dev); 1587 1588 /* 1589 * Enable interrupts but don't do any DMA 1590 * enintr() also enables interrupts for the sbic 1591 */ 1592 dev->sc_enintr(dev); 1593 1594 if (usedma) { 1595 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1596 acb->sc_pa.dc_count, dmaflags); 1597 #ifdef DEBUG 1598 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1599 #endif 1600 } else 1601 dev->sc_dmacmd = 0; /* Don't use DMA */ 1602 1603 acb->sc_dmacmd = dev->sc_dmacmd; 1604 1605 #ifdef DEBUG 1606 if (data_pointer_debug > 1) { 1607 printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, 1608 dev->sc_cur->dc_addr, 1609 dev->sc_tcnt, 1610 dev->sc_dmacmd); 1611 } 1612 #endif 1613 1614 /* 1615 * Lets cycle a while then let the interrupt handler take over. 1616 */ 1617 GET_SBIC_asr(regs, asr); 1618 1619 do { 1620 1621 QPRINTF(("go ")); 1622 1623 /* 1624 * Handle the new phase 1625 */ 1626 i = sbicnextstate(dev, csr, asr); 1627 #if 0 1628 WAIT_CIP(regs); 1629 #endif 1630 if (i == SBIC_STATE_RUNNING) { 1631 GET_SBIC_asr(regs, asr); 1632 1633 if (asr & SBIC_ASR_LCI) 1634 printf("sbicgo: LCI asr:%02x csr:%02x\n", 1635 asr, csr); 1636 1637 if (asr & SBIC_ASR_INT) 1638 GET_SBIC_csr(regs, csr); 1639 } 1640 1641 } while (i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1642 1643 if (i == SBIC_STATE_DONE) { 1644 if (dev->sc_stat[0] == 0xff) 1645 #if 0 1646 printf("sbicgo: done & stat = 0xff\n"); 1647 #else 1648 ; 1649 #endif 1650 else 1651 return 1; /* Did we really finish that fast? */ 1652 } 1653 1654 return 0; 1655 } 1656 1657 1658 int 1659 sbicintr(struct sbic_softc *dev) 1660 { 1661 sbic_regmap_p regs = dev->sc_sbicp; 1662 u_char asr, csr; 1663 int i; 1664 1665 /* 1666 * pending interrupt? 1667 */ 1668 GET_SBIC_asr (regs, asr); 1669 if ((asr & SBIC_ASR_INT) == 0) 1670 return 0; 1671 1672 GET_SBIC_csr(regs, csr); 1673 1674 do { 1675 1676 QPRINTF(("intr[0x%x]", csr)); 1677 1678 i = sbicnextstate(dev, csr, asr); 1679 #if 0 1680 WAIT_CIP(regs); 1681 #endif 1682 if (i == SBIC_STATE_RUNNING) { 1683 GET_SBIC_asr(regs, asr); 1684 1685 if (asr & SBIC_ASR_LCI) 1686 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1687 1688 if (asr & SBIC_ASR_INT) 1689 GET_SBIC_csr(regs, csr); 1690 } 1691 1692 } while (i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1693 1694 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1695 1696 return 1; 1697 } 1698 1699 /* 1700 * Run commands and wait for disconnect. 1701 * This is only ever called when a command is in progress, when we 1702 * want to busy wait for it to finish. 1703 */ 1704 int 1705 sbicpoll(struct sbic_softc *dev) 1706 { 1707 sbic_regmap_p regs = dev->sc_sbicp; 1708 u_char asr, csr = SBIC_CSR_RESET; /* XXX: Quell un-init warning */ 1709 int i; 1710 1711 /* 1712 * Wait for the next interrupt 1713 */ 1714 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1715 1716 do { 1717 GET_SBIC_asr (regs, asr); 1718 1719 if (asr & SBIC_ASR_INT) 1720 GET_SBIC_csr(regs, csr); 1721 1722 QPRINTF(("poll[0x%x]", csr)); 1723 1724 /* 1725 * Handle it 1726 */ 1727 i = sbicnextstate(dev, csr, asr); 1728 1729 WAIT_CIP(regs); 1730 GET_SBIC_asr(regs, asr); 1731 1732 /* 1733 * tapes may take a loooong time.. 1734 */ 1735 while (asr & SBIC_ASR_BSY) { 1736 u_char z = 0; 1737 1738 if (asr & SBIC_ASR_DBR) { 1739 printf("sbipoll: Waiting while sbic is jammed," 1740 " CSR:%02x,ASR:%02x\n", csr, asr); 1741 #ifdef DDB 1742 Debugger(); 1743 #endif 1744 /* 1745 * SBIC is jammed 1746 * DUNNO which direction 1747 * Try old direction 1748 */ 1749 GET_SBIC_data(regs, z); 1750 GET_SBIC_asr(regs, asr); 1751 1752 if (asr & SBIC_ASR_DBR) /* Wants us to write */ 1753 SET_SBIC_data(regs, z); 1754 } 1755 1756 GET_SBIC_asr(regs, asr); 1757 } 1758 1759 if (asr & SBIC_ASR_LCI) 1760 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1761 else if (i == SBIC_STATE_RUNNING) /* BSY */ 1762 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1763 1764 } while (i == SBIC_STATE_RUNNING); 1765 1766 return 1; 1767 } 1768 1769 /* 1770 * Handle a single msgin 1771 */ 1772 int 1773 sbicmsgin(struct sbic_softc *dev) 1774 { 1775 sbic_regmap_p regs = dev->sc_sbicp; 1776 int recvlen = 1; 1777 u_char asr, csr, *tmpaddr, *msgaddr; 1778 1779 tmpaddr = msgaddr = dev->sc_msg; 1780 1781 tmpaddr[0] = 0xff; 1782 tmpaddr[1] = 0xff; 1783 1784 GET_SBIC_asr(regs, asr); 1785 1786 #ifdef DEBUG 1787 if (reselect_debug > 1) 1788 printf("sbicmsgin asr=%02x\n", asr); 1789 #endif 1790 1791 GET_SBIC_selid (regs, csr); 1792 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1793 1794 SBIC_TC_PUT(regs, 0); 1795 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1796 1797 do { 1798 while (recvlen--) { 1799 1800 /* 1801 * Fetch the next byte of the message 1802 */ 1803 RECV_BYTE(regs, *tmpaddr); 1804 1805 /* 1806 * get the command completion interrupt, or we 1807 * can't send a new command (LCI) 1808 */ 1809 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1810 GET_SBIC_csr(regs, csr); 1811 1812 #ifdef DEBUG 1813 if (reselect_debug > 1) 1814 printf("sbicmsgin: got %02x csr %02x\n", 1815 *tmpaddr, csr); 1816 #endif 1817 1818 tmpaddr++; 1819 1820 if (recvlen) { 1821 /* 1822 * Clear ACK, and wait for the interrupt 1823 * for the next byte 1824 */ 1825 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1826 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1827 GET_SBIC_csr(regs, csr); 1828 } 1829 } 1830 1831 if (msgaddr[0] == 0xff) { 1832 printf("sbicmsgin: sbic swallowed our message\n"); 1833 break; 1834 } 1835 1836 #ifdef DEBUG 1837 if (sync_debug) { 1838 GET_SBIC_asr(regs, asr); 1839 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 1840 csr, asr, msgaddr[0]); 1841 } 1842 #endif 1843 /* 1844 * test whether this is a reply to our sync 1845 * request 1846 */ 1847 if (MSG_ISIDENTIFY(msgaddr[0])) { 1848 1849 /* 1850 * Got IFFY msg -- ack it 1851 */ 1852 QPRINTF(("IFFY")); 1853 1854 } else if (msgaddr[0] == MSG_REJECT && 1855 dev->sc_sync[dev->target].state == SYNC_SENT) { 1856 1857 /* 1858 * Target probably rejected our Sync negotiation. 1859 */ 1860 QPRINTF(("REJECT of SYN")); 1861 1862 #ifdef DEBUG 1863 if (sync_debug) 1864 printf("target %d rejected sync, going async\n", 1865 dev->target); 1866 #endif 1867 1868 dev->sc_sync[dev->target].period = sbic_min_period; 1869 dev->sc_sync[dev->target].offset = 0; 1870 dev->sc_sync[dev->target].state = SYNC_DONE; 1871 SET_SBIC_syn(regs, 1872 SBIC_SYN(dev->sc_sync[dev->target].offset, 1873 dev->sc_sync[dev->target].period)); 1874 1875 } else if (msgaddr[0] == MSG_REJECT) { 1876 1877 /* 1878 * we'll never REJECt a REJECT message.. 1879 */ 1880 QPRINTF(("REJECT")); 1881 1882 } else if (msgaddr[0] == MSG_SAVE_DATA_PTR) { 1883 1884 /* 1885 * don't reject this either. 1886 */ 1887 QPRINTF(("MSG_SAVE_DATA_PTR")); 1888 1889 } else if (msgaddr[0] == MSG_RESTORE_PTR) { 1890 1891 /* 1892 * don't reject this either. 1893 */ 1894 QPRINTF(("MSG_RESTORE_PTR")); 1895 1896 } else if (msgaddr[0] == MSG_DISCONNECT) { 1897 1898 /* 1899 * Target is disconnecting... 1900 */ 1901 QPRINTF(("DISCONNECT")); 1902 1903 #ifdef DEBUG 1904 if (reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT) 1905 printf("sbicmsgin: got disconnect msg %s\n", 1906 (dev->sc_flags & SBICF_ICMD) ? 1907 "rejecting" : ""); 1908 #endif 1909 1910 if (dev->sc_flags & SBICF_ICMD) { 1911 /* 1912 * We're in immediate mode. Prevent disconnects. 1913 * prepare to reject the message, NACK 1914 */ 1915 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1916 WAIT_CIP(regs); 1917 } 1918 1919 } else if (msgaddr[0] == MSG_CMD_COMPLETE) { 1920 1921 /* 1922 * !! KLUDGE ALERT !! quite a few drives don't seem to 1923 * really like the current way of sending the 1924 * sync-handshake together with the ident-message, and 1925 * they react by sending command-complete and 1926 * disconnecting right after returning the valid sync 1927 * handshake. So, all I can do is reselect the drive, 1928 * and hope it won't disconnect again. I don't think 1929 * this is valid behavior, but I can't help fixing a 1930 * problem that apparently exists. 1931 * 1932 * Note: we should not get here on `normal' command 1933 * completion, as that condition is handled by the 1934 * high-level sel&xfer resume command used to walk 1935 * thru status/cc-phase. 1936 */ 1937 QPRINTF(("CMD_COMPLETE")); 1938 1939 #ifdef DEBUG 1940 if (sync_debug) 1941 printf("GOT MSG %d! target %d acting weird.." 1942 " waiting for disconnect...\n", 1943 msgaddr[0], dev->target); 1944 #endif 1945 1946 /* 1947 * Check to see if sbic is handling this 1948 */ 1949 GET_SBIC_asr(regs, asr); 1950 1951 /* 1952 * XXXSCW: I'm not convinced of this, 1953 * we haven't negated ACK yet... 1954 */ 1955 if (asr & SBIC_ASR_BSY) 1956 return SBIC_STATE_RUNNING; 1957 1958 /* 1959 * Let's try this: Assume it works and set status to 00 1960 */ 1961 dev->sc_stat[0] = 0; 1962 1963 } else if (msgaddr[0] == MSG_EXT_MESSAGE && 1964 tmpaddr == &(msgaddr[1])) { 1965 1966 /* 1967 * Target is sending us an extended message. 1968 * We'll assume it's the response to our Sync. 1969 * negotiation. 1970 */ 1971 QPRINTF(("ExtMSG\n")); 1972 1973 /* 1974 * Read in whole extended message. 1975 * First, negate ACK to accept 1976 * the MSG_EXT_MESSAGE byte... 1977 */ 1978 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1979 1980 /* 1981 * Wait for the interrupt for the next byte (length) 1982 */ 1983 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1984 GET_SBIC_csr(regs, csr); 1985 1986 #ifdef DEBUG 1987 QPRINTF(("CLR ACK csr %02x\n", csr)); 1988 #endif 1989 1990 /* 1991 * Read the length byte 1992 */ 1993 RECV_BYTE(regs, *tmpaddr); 1994 1995 /* 1996 * Wait for command completion IRQ 1997 */ 1998 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1999 GET_SBIC_csr(regs, csr); 2000 2001 /* 2002 * Reload the loop counter 2003 */ 2004 recvlen = *tmpaddr++; 2005 2006 QPRINTF(("Recving ext msg, csr %02x len %02x\n", 2007 csr, recvlen)); 2008 2009 } else if (msgaddr[0] == MSG_EXT_MESSAGE && 2010 msgaddr[1] == 3 && 2011 msgaddr[2] == MSG_SYNC_REQ ) { 2012 2013 /* 2014 * We've received the complete Extended Message Sync. 2015 * Request... 2016 */ 2017 QPRINTF(("SYN")); 2018 2019 /* 2020 * Compute the required Transfer Period for 2021 * the WD chip... 2022 */ 2023 dev->sc_sync[dev->target].period = 2024 sbicfromscsiperiod(dev, msgaddr[3]); 2025 dev->sc_sync[dev->target].offset = msgaddr[4]; 2026 dev->sc_sync[dev->target].state = SYNC_DONE; 2027 2028 /* 2029 * Put the WD chip in synchronous mode 2030 */ 2031 SET_SBIC_syn(regs, 2032 SBIC_SYN(dev->sc_sync[dev->target].offset, 2033 dev->sc_sync[dev->target].period)); 2034 #ifdef DEBUG 2035 if (sync_debug) 2036 printf("msgin(%d): sync reg = 0x%02x\n", 2037 dev->target, 2038 SBIC_SYN(dev->sc_sync[dev->target].offset, 2039 dev->sc_sync[dev->target].period)); 2040 #endif 2041 2042 printf("%s: target %d now synchronous, " 2043 "period=%dns, offset=%d.\n", 2044 device_xname(dev->sc_dev), dev->target, 2045 msgaddr[3] * 4, msgaddr[4]); 2046 2047 } else { 2048 2049 /* 2050 * We don't support whatever this message is... 2051 */ 2052 #ifdef DEBUG 2053 if (sbic_debug || sync_debug) 2054 printf("sbicmsgin: Rejecting message 0x%02x\n", 2055 msgaddr[0]); 2056 #endif 2057 2058 /* 2059 * prepare to reject the message, NACK 2060 */ 2061 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2062 WAIT_CIP(regs); 2063 } 2064 2065 /* 2066 * Negate ACK to complete the transfer 2067 */ 2068 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2069 2070 /* 2071 * Wait for the interrupt for the next byte, or phase change. 2072 * Only read the CSR if we have more data to transfer. 2073 * XXXSCW: We should really verify that we're still in 2074 * MSG IN phase before blindly going back around this loop, 2075 * but that would mean we read the CSR... <sigh> 2076 */ 2077 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2078 if (recvlen > 0) 2079 GET_SBIC_csr(regs, csr); 2080 2081 } while (recvlen > 0); 2082 2083 /* 2084 * Should still have one CSR to read 2085 */ 2086 return SBIC_STATE_RUNNING; 2087 } 2088 2089 2090 /* 2091 * sbicnextstate() 2092 * return: 2093 * SBIC_STATE_DONE == done 2094 * SBIC_STATE_RUNNING == working 2095 * SBIC_STATE_DISCONNECT == disconnected 2096 * SBIC_STATE_ERROR == error 2097 */ 2098 int 2099 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 2100 { 2101 sbic_regmap_p regs = dev->sc_sbicp; 2102 struct sbic_acb *acb = dev->sc_nexus; 2103 2104 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2105 2106 switch (csr) { 2107 2108 case SBIC_CSR_XFERRED | CMD_PHASE: 2109 case SBIC_CSR_MIS | CMD_PHASE: 2110 case SBIC_CSR_MIS_1 | CMD_PHASE: 2111 case SBIC_CSR_MIS_2 | CMD_PHASE: 2112 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2113 goto abort; 2114 break; 2115 2116 case SBIC_CSR_XFERRED | STATUS_PHASE: 2117 case SBIC_CSR_MIS | STATUS_PHASE: 2118 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2119 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2120 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2121 2122 /* 2123 * this should be the normal i/o completion case. 2124 * get the status & cmd complete msg then let the 2125 * device driver look at what happened. 2126 */ 2127 sbicxfdone(dev); 2128 2129 #ifdef DEBUG 2130 dev->sc_dmatimo = 0; 2131 if (data_pointer_debug > 1) 2132 printf("next dmastop: %d(%p:%lx)\n", 2133 dev->target, 2134 dev->sc_cur->dc_addr, 2135 dev->sc_tcnt); 2136 #endif 2137 /* 2138 * Stop the DMA chip 2139 */ 2140 dev->sc_dmastop(dev); 2141 2142 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2143 2144 /* 2145 * Indicate to the upper layers that the command is done 2146 */ 2147 sbic_scsidone(acb, dev->sc_stat[0]); 2148 2149 return SBIC_STATE_DONE; 2150 2151 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2152 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2153 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2154 case SBIC_CSR_MIS | DATA_IN_PHASE: 2155 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2156 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2157 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2158 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2159 /* 2160 * Verify that we expected to transfer data... 2161 */ 2162 if (acb->sc_kv.dc_count <= 0) { 2163 printf("next: DATA phase with xfer count == %d, " 2164 "asr:0x%02x csr:0x%02x\n", 2165 acb->sc_kv.dc_count, asr, csr); 2166 goto abort; 2167 } 2168 2169 /* 2170 * Should we transfer using PIO or DMA ? 2171 */ 2172 if (dev->sc_xs->xs_control & XS_CTL_POLL || 2173 dev->sc_flags & SBICF_ICMD || 2174 acb->sc_dmacmd == 0 ) { 2175 2176 /* 2177 * Do PIO transfer 2178 */ 2179 int i; 2180 2181 #ifdef DEBUG 2182 if (data_pointer_debug > 1) 2183 printf("next PIO: %d(%p:%x)\n", dev->target, 2184 acb->sc_kv.dc_addr, 2185 acb->sc_kv.dc_count); 2186 #endif 2187 2188 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 2189 /* 2190 * data in 2191 */ 2192 i = sbicxfin(regs, acb->sc_kv.dc_count, 2193 acb->sc_kv.dc_addr); 2194 else 2195 /* 2196 * data out 2197 */ 2198 i = sbicxfout(regs, acb->sc_kv.dc_count, 2199 acb->sc_kv.dc_addr); 2200 2201 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2202 acb->sc_kv.dc_count = i; 2203 2204 /* 2205 * Update current count... 2206 */ 2207 acb->sc_tcnt = dev->sc_tcnt = i; 2208 2209 dev->sc_flags &= ~SBICF_INDMA; 2210 2211 } else { 2212 2213 /* 2214 * Do DMA transfer 2215 * set next DMA addr and dec count 2216 */ 2217 sbic_save_ptrs(dev); 2218 sbic_load_ptrs(dev); 2219 2220 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2221 SBIC_MACHINE_DMA_MODE); 2222 2223 #ifdef DEBUG 2224 dev->sc_dmatimo = 1; 2225 if (data_pointer_debug > 1) 2226 printf("next DMA: %d(%p:%lx)\n", dev->target, 2227 dev->sc_cur->dc_addr, 2228 dev->sc_tcnt); 2229 #endif 2230 /* 2231 * Start the DMA chip going 2232 */ 2233 dev->sc_tcnt = dev->sc_dmanext(dev); 2234 2235 /* 2236 * Tell the WD chip how much to transfer 2237 * this time around 2238 */ 2239 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2240 2241 /* 2242 * Start the transfer 2243 */ 2244 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2245 2246 /* 2247 * Indicate that we're in DMA mode 2248 */ 2249 dev->sc_flags |= SBICF_INDMA; 2250 } 2251 break; 2252 2253 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2254 case SBIC_CSR_MIS | MESG_IN_PHASE: 2255 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2256 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2257 sbic_save_ptrs(dev); 2258 2259 /* 2260 * Handle a single message in... 2261 */ 2262 return sbicmsgin(dev); 2263 2264 case SBIC_CSR_MSGIN_W_ACK: 2265 /* 2266 * We should never see this since it's handled in 'sbicmsgin()' 2267 * but just for the sake of paranoia... 2268 */ 2269 /* Dunno what I'm ACKing */ 2270 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2271 printf("Acking unknown msgin CSR:%02x",csr); 2272 break; 2273 2274 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2275 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2276 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2277 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2278 /* 2279 * We only ever handle a message out phase here for sending a 2280 * REJECT message. 2281 */ 2282 sbic_save_ptrs(dev); 2283 2284 #ifdef DEBUG 2285 if (sync_debug) 2286 printf("sending REJECT msg to last msg.\n"); 2287 #endif 2288 2289 SEND_BYTE(regs, MSG_REJECT); 2290 WAIT_CIP(regs); 2291 break; 2292 2293 case SBIC_CSR_DISC: 2294 case SBIC_CSR_DISC_1: 2295 /* 2296 * Try to schedule another target 2297 */ 2298 sbic_save_ptrs(dev); 2299 2300 dev->sc_flags &= ~SBICF_SELECTED; 2301 2302 #ifdef DEBUG 2303 if (reselect_debug > 1) 2304 printf("sbicnext target %d disconnected\n", 2305 dev->target); 2306 #endif 2307 2308 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2309 2310 ++dev->sc_tinfo[dev->target].dconns; 2311 2312 dev->sc_nexus = NULL; 2313 dev->sc_xs = NULL; 2314 2315 if (acb->xs->xs_control & XS_CTL_POLL || 2316 dev->sc_flags & SBICF_ICMD || 2317 !sbic_parallel_operations ) 2318 return SBIC_STATE_DISCONNECT; 2319 2320 QPRINTF(("sbicnext: calling sbic_sched\n")); 2321 2322 sbic_sched(dev); 2323 2324 QPRINTF(("sbicnext: sbic_sched returned\n")); 2325 2326 return SBIC_STATE_DISCONNECT; 2327 2328 case SBIC_CSR_RSLT_NI: 2329 case SBIC_CSR_RSLT_IFY: 2330 { 2331 /* 2332 * A reselection. 2333 * Note that since we don't enable Advanced Features (assuming 2334 * the WD chip is at least the 'A' revision), we're only ever 2335 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2336 * hell of it, we'll handle it anyway, for all the extra code 2337 * it needs... 2338 */ 2339 u_char newtarget, newlun; 2340 2341 GET_SBIC_rselid(regs, newtarget); 2342 2343 /* 2344 * check SBIC_RID_SIV? 2345 */ 2346 newtarget &= SBIC_RID_MASK; 2347 2348 if (csr == SBIC_CSR_RSLT_IFY) { 2349 2350 /* 2351 * Read Identify msg to avoid lockup 2352 */ 2353 GET_SBIC_data(regs, newlun); 2354 WAIT_CIP(regs); 2355 newlun &= SBIC_TLUN_MASK; 2356 2357 } else { 2358 2359 /* 2360 * Need to read Identify message the hard way, assuming 2361 * the target even sends us one... 2362 */ 2363 for (newlun = 255; newlun; --newlun) { 2364 GET_SBIC_asr(regs, asr); 2365 if (asr & SBIC_ASR_INT) 2366 break; 2367 delay(10); 2368 } 2369 2370 /* 2371 * If we didn't get an interrupt, somethink's up 2372 */ 2373 if ((asr & SBIC_ASR_INT) == 0) { 2374 printf("%s: Reselect without identify?" 2375 " asr %x\n", device_xname(dev->sc_dev), asr); 2376 newlun = 0; /* XXXX */ 2377 } else { 2378 /* 2379 * We got an interrupt, verify that 2380 * it's a change to message in phase, 2381 * and if so read the message. 2382 */ 2383 GET_SBIC_csr(regs,csr); 2384 2385 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2386 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2387 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2388 /* 2389 * Yup, gone to message in. 2390 * Fetch the target LUN 2391 */ 2392 sbicmsgin(dev); 2393 newlun = dev->sc_msg[0] & 0x07; 2394 2395 } else { 2396 /* 2397 * Whoops! Target didn't go to 2398 * message in phase!! 2399 */ 2400 printf("RSLT_NI - " 2401 "not MESG_IN_PHASE %x\n", csr); 2402 newlun = 0; /* XXXSCW */ 2403 } 2404 } 2405 } 2406 2407 /* 2408 * Ok, we have the identity of the reselecting target. 2409 */ 2410 #ifdef DEBUG 2411 if (reselect_debug > 1 || 2412 (reselect_debug && csr == SBIC_CSR_RSLT_NI)) { 2413 printf("sbicnext: reselect %s from targ %d lun %d\n", 2414 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2415 newtarget, newlun); 2416 } 2417 #endif 2418 2419 if (dev->sc_nexus) { 2420 /* 2421 * Whoops! We've been reselected with 2422 * an command in progress! 2423 * The best we can do is to put the current command 2424 * back on the ready list and hope for the best. 2425 */ 2426 #ifdef DEBUG 2427 if (reselect_debug > 1) { 2428 printf("%s: reselect %s with active command\n", 2429 device_xname(dev->sc_dev), 2430 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2431 } 2432 #endif 2433 2434 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, 2435 chain); 2436 2437 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2438 2439 dev->sc_nexus = NULL; 2440 dev->sc_xs = NULL; 2441 } 2442 2443 /* 2444 * Reload sync values for this target 2445 */ 2446 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2447 SET_SBIC_syn(regs, 2448 SBIC_SYN(dev->sc_sync[newtarget].offset, 2449 dev->sc_sync[newtarget].period)); 2450 else 2451 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2452 2453 /* 2454 * Loop through the nexus list until we find the saved entry 2455 * for the reselecting target... 2456 */ 2457 for (acb = dev->nexus_list.tqh_first; acb; 2458 acb = acb->chain.tqe_next) { 2459 2460 if ( acb->xs->xs_periph->periph_target == newtarget && 2461 acb->xs->xs_periph->periph_lun == newlun) { 2462 /* 2463 * We've found the saved entry. Dequeue it, and 2464 * make it current again. 2465 */ 2466 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2467 2468 dev->sc_nexus = acb; 2469 dev->sc_xs = acb->xs; 2470 dev->sc_flags |= SBICF_SELECTED; 2471 dev->target = newtarget; 2472 dev->lun = newlun; 2473 break; 2474 } 2475 } 2476 2477 if (acb == NULL) { 2478 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2479 device_xname(dev->sc_dev), 2480 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2481 &dev->nexus_list.tqh_first); 2482 panic("bad reselect in sbic"); 2483 } 2484 2485 if (csr == SBIC_CSR_RSLT_IFY) 2486 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2487 break; 2488 } 2489 default: 2490 abort: 2491 /* 2492 * Something unexpected happened -- deal with it. 2493 */ 2494 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2495 2496 #ifdef DDB 2497 Debugger(); 2498 #endif 2499 2500 #ifdef DEBUG 2501 dev->sc_dmatimo = 0; 2502 if (data_pointer_debug > 1) 2503 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2504 dev->sc_cur->dc_addr, 2505 dev->sc_tcnt); 2506 #endif 2507 2508 dev->sc_dmastop(dev); 2509 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2510 if (dev->sc_xs) 2511 sbicerror(dev, csr); 2512 sbicabort(dev, "next"); 2513 2514 if (dev->sc_flags & SBICF_INDMA) { 2515 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2516 2517 #ifdef DEBUG 2518 dev->sc_dmatimo = 0; 2519 if (data_pointer_debug > 1) 2520 printf("next dmastop: %d(%p:%lx)\n", 2521 dev->target, 2522 dev->sc_cur->dc_addr, 2523 dev->sc_tcnt); 2524 #endif 2525 sbic_scsidone(acb, -1); 2526 } 2527 2528 return SBIC_STATE_ERROR; 2529 } 2530 2531 return SBIC_STATE_RUNNING; 2532 } 2533 2534 2535 /* 2536 * Check if DMA can not be used with specified buffer 2537 */ 2538 int 2539 sbiccheckdmap(void *bp, u_long len, u_long mask) 2540 { 2541 u_char *buffer; 2542 u_long phy_buf; 2543 u_long phy_len; 2544 2545 buffer = bp; 2546 2547 if (len == 0) 2548 return 1; 2549 2550 while (len) { 2551 2552 phy_buf = kvtop((void *)buffer); 2553 phy_len = PAGE_SIZE - ((int)buffer & PGOFSET); 2554 2555 if (len < phy_len) 2556 phy_len = len; 2557 2558 if (phy_buf & mask) 2559 return 1; 2560 2561 buffer += phy_len; 2562 len -= phy_len; 2563 } 2564 2565 return 0; 2566 } 2567 2568 int 2569 sbictoscsiperiod(struct sbic_softc *dev, int a) 2570 { 2571 unsigned int fs; 2572 2573 /* 2574 * cycle = DIV / (2 * CLK) 2575 * DIV = FS + 2 2576 * best we can do is 200ns at 20 MHz, 2 cycles 2577 */ 2578 2579 GET_SBIC_myid(dev->sc_sbicp, fs); 2580 2581 fs = (fs >> 6) + 2; /* DIV */ 2582 2583 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2584 2585 if (a < 2) 2586 a = 8; /* map to Cycles */ 2587 2588 return (fs * a) >> 2; /* in 4 ns units */ 2589 } 2590 2591 int 2592 sbicfromscsiperiod(struct sbic_softc *dev, int p) 2593 { 2594 unsigned int fs, ret; 2595 2596 /* 2597 * Just the inverse of the above 2598 */ 2599 GET_SBIC_myid(dev->sc_sbicp, fs); 2600 2601 fs = (fs >> 6) + 2; /* DIV */ 2602 2603 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2604 2605 ret = p << 2; /* in ns units */ 2606 ret = ret / fs; /* in Cycles */ 2607 2608 if (ret < sbic_min_period) 2609 return(sbic_min_period); 2610 2611 /* 2612 * verify rounding 2613 */ 2614 if (sbictoscsiperiod(dev, ret) < p) 2615 ret++; 2616 2617 return (ret >= 8) ? 0 : ret; 2618 } 2619 2620 #ifdef DEBUG 2621 void 2622 sbictimeout(struct sbic_softc *dev) 2623 { 2624 int s, asr; 2625 2626 s = splbio(); 2627 2628 if (dev->sc_dmatimo) { 2629 2630 if (dev->sc_dmatimo > 1) { 2631 2632 printf("%s: DMA timeout #%d\n", device_xname(dev->sc_dev), 2633 dev->sc_dmatimo - 1); 2634 2635 GET_SBIC_asr(dev->sc_sbicp, asr); 2636 2637 if (asr & SBIC_ASR_INT) { 2638 /* 2639 * We need to service a missed IRQ 2640 */ 2641 sbicintr(dev); 2642 } else { 2643 (void)sbicabort(dev, "timeout"); 2644 splx(s); 2645 return; 2646 } 2647 } 2648 2649 dev->sc_dmatimo++; 2650 } 2651 2652 splx(s); 2653 2654 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 2655 } 2656 #endif 2657
Indexes created Sat Sep 27 21:09:56 GMT 2025