sbic.c revision 1.5
1 /* $NetBSD: sbic.c,v 1.5 1996/10/13 03:30:20 christos Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/kernel.h> /* For hz */ 60 #include <sys/disklabel.h> 61 #include <sys/dkstat.h> 62 #include <sys/buf.h> 63 #include <scsi/scsi_all.h> 64 #include <scsi/scsiconf.h> 65 #include <vm/vm.h> 66 #include <vm/vm_kern.h> 67 #include <vm/vm_page.h> 68 #include <vm/pmap.h> 69 #include <machine/pmap.h> 70 #include <mvme68k/mvme68k/isr.h> 71 #include <mvme68k/dev/dmavar.h> 72 #include <mvme68k/dev/sbicreg.h> 73 #include <mvme68k/dev/sbicvar.h> 74 75 76 /* 77 * Since I can't find this in any other header files 78 */ 79 #define SCSI_PHASE(reg) (reg&0x07) 80 81 /* 82 * SCSI delays 83 * In u-seconds, primarily for state changes on the SPC. 84 */ 85 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 86 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 87 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 88 89 /* 90 * Convenience macro for waiting for a particular sbic event 91 */ 92 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 93 94 extern u_int kvtop(); 95 96 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 97 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 98 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 99 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 100 int sbiccheckdmap __P((void *, u_long, u_long)); 101 u_char sbicselectbus __P((struct sbic_softc *)); 102 int sbicxfout __P((sbic_regmap_p, int, void *)); 103 int sbicxfin __P((sbic_regmap_p, int, void *)); 104 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 105 int sbictoscsiperiod __P((struct sbic_softc *, int)); 106 int sbicintr __P((struct sbic_softc *)); 107 int sbicpoll __P((struct sbic_softc *)); 108 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 109 int sbicmsgin __P((struct sbic_softc *)); 110 int sbicabort __P((struct sbic_softc *, char *)); 111 void sbicxfdone __P((struct sbic_softc *)); 112 void sbicerror __P((struct sbic_softc *,u_char)); 113 void sbicreset __P((struct sbic_softc *)); 114 void sbic_scsidone __P((struct sbic_acb *, int)); 115 void sbic_sched __P((struct sbic_softc *)); 116 void sbic_save_ptrs __P((struct sbic_softc *)); 117 void sbic_load_ptrs __P((struct sbic_softc *)); 118 119 /* 120 * Synch xfer parameters, and timing conversions 121 */ 122 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 123 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 124 int sbic_cmd_wait = SBIC_CMD_WAIT; 125 int sbic_data_wait = SBIC_DATA_WAIT; 126 int sbic_init_wait = SBIC_INIT_WAIT; 127 128 /* 129 * was broken before.. now if you want this you get it for all drives 130 * on sbic controllers. 131 */ 132 u_char sbic_inhibit_sync[8]; 133 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 134 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 135 int sbic_parallel_operations = 1; /* Allow command queues */ 136 137 /* 138 * Some useful stuff for debugging purposes 139 */ 140 #ifdef DEBUG 141 int sbicdma_ops = 0; /* total DMA operations */ 142 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 143 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 144 int sbicdma_saves = 0; 145 146 #define QPRINTF(a) if (sbic_debug > 1) printf a 147 148 int sbic_debug = 0; /* Debug all chip related things */ 149 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 150 int reselect_debug = 0; /* Debug all reselection related things */ 151 int report_sense = 0; /* Always print Sense information */ 152 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 153 154 void sbictimeout __P((struct sbic_softc *dev)); 155 156 #else 157 #define QPRINTF(a) /* */ 158 #endif 159 160 161 /* 162 * default minphys routine for sbic based controllers 163 */ 164 void 165 sbic_minphys(bp) 166 struct buf *bp; 167 { 168 /* 169 * No max transfer at this level. 170 */ 171 minphys(bp); 172 } 173 174 175 /* 176 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 177 */ 178 void 179 sbic_save_ptrs(dev) 180 struct sbic_softc *dev; 181 { 182 sbic_regmap_p regs; 183 struct sbic_acb* acb; 184 int count, 185 asr, 186 s; 187 188 /* 189 * Only need to save pointers if DMA was active... 190 */ 191 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 192 return; 193 194 regs = dev->sc_sbicp; 195 196 s = splbio(); 197 198 /* 199 * Wait until WD chip is idle 200 */ 201 do { 202 GET_SBIC_asr(regs, asr); 203 if( asr & SBIC_ASR_DBR ) { 204 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 205 splx(s); 206 return; 207 } 208 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 209 210 211 /* 212 * Save important state. 213 * must be done before dmastop 214 */ 215 acb = dev->sc_nexus; 216 acb->sc_dmacmd = dev->sc_dmacmd; 217 218 /* 219 * Fetch the residual count 220 */ 221 SBIC_TC_GET(regs, count); 222 223 /* 224 * Shut down DMA 225 */ 226 dev->sc_dmastop(dev); 227 228 /* 229 * No longer in DMA 230 */ 231 dev->sc_flags &= ~SBICF_INDMA; 232 233 /* 234 * Ensure the WD chip is back in polled I/O mode, with nothing to 235 * transfer. 236 */ 237 SBIC_TC_PUT(regs, 0); 238 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 239 240 /* 241 * Update current count... 242 */ 243 acb->sc_tcnt = count; 244 245 /* 246 * Work out how many bytes were actually transferred 247 */ 248 count = dev->sc_tcnt - count; 249 dev->sc_tcnt = acb->sc_tcnt; 250 251 /* 252 * Fixup partial xfers 253 */ 254 acb->sc_kv.dc_addr += count; 255 acb->sc_kv.dc_count -= count; 256 acb->sc_pa.dc_addr += count; 257 acb->sc_pa.dc_count -= count >> 1; 258 259 #ifdef DEBUG 260 if ( data_pointer_debug ) 261 printf("save at (%x,%x):%x\n", 262 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 263 sbicdma_saves++; 264 #endif 265 266 splx(s); 267 } 268 269 270 /* 271 * DOES NOT RESTART DMA!!! 272 */ 273 void 274 sbic_load_ptrs(dev) 275 struct sbic_softc *dev; 276 { 277 struct sbic_acb *acb = dev->sc_nexus; 278 int s; 279 280 if ( acb->sc_kv.dc_count == 0 ) { 281 /* 282 * No data to xfer 283 */ 284 return; 285 } 286 287 s = splbio(); 288 289 /* 290 * Reset the Scatter-Gather chain 291 */ 292 dev->sc_last = dev->sc_cur = &acb->sc_pa; 293 294 /* 295 * Restore the Transfer Count and DMA specific data 296 */ 297 dev->sc_tcnt = acb->sc_tcnt; 298 dev->sc_dmacmd = acb->sc_dmacmd; 299 300 #ifdef DEBUG 301 sbicdma_ops++; 302 #endif 303 304 /* 305 * Need to fixup new segment? 306 */ 307 if ( dev->sc_tcnt == 0 ) { 308 /* 309 * sc_tcnt == 0 implies end of segment 310 */ 311 char *vaddr, *paddr; 312 int count; 313 314 /* 315 * do kvm to pa mappings 316 */ 317 vaddr = acb->sc_kv.dc_addr; 318 paddr = acb->sc_pa.dc_addr = (char *) kvtop(vaddr); 319 320 for (count = (NBPG - ((int)vaddr & PGOFSET)); 321 count < acb->sc_kv.dc_count && 322 (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 323 count += NBPG) 324 ; /* Do nothing */ 325 326 /* 327 * If it's all contiguous... 328 */ 329 if ( count > acb->sc_kv.dc_count ) { 330 count = acb->sc_kv.dc_count; 331 #ifdef DEBUG 332 sbicdma_hits++; 333 #endif 334 } 335 #ifdef DEBUG 336 else 337 sbicdma_misses++; 338 #endif 339 340 acb->sc_tcnt = count; 341 acb->sc_pa.dc_count = count >> 1; 342 343 #ifdef DEBUG 344 if ( data_pointer_debug ) 345 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", acb->sc_kv.dc_addr, 346 acb->sc_kv.dc_count, 347 acb->sc_pa.dc_addr, 348 acb->sc_tcnt); 349 #endif 350 351 } 352 353 splx(s); 354 } 355 356 /* 357 * used by specific sbic controller 358 * 359 * it appears that the higher level code does nothing with LUN's 360 * so I will too. I could plug it in, however so could they 361 * in scsi_scsi_cmd(). 362 */ 363 int 364 sbic_scsicmd(xs) 365 struct scsi_xfer *xs; 366 { 367 struct scsi_link *slp = xs->sc_link; 368 struct sbic_softc *dev = slp->adapter_softc; 369 struct sbic_acb *acb; 370 int flags = xs->flags, 371 s; 372 373 if ( flags & SCSI_DATA_UIO ) 374 panic("sbic: scsi data uio requested"); 375 376 if ( dev->sc_nexus && (flags & SCSI_POLL) ) 377 panic("sbic_scsicmd: busy"); 378 379 if ( slp->target == slp->adapter_target ) 380 return ESCAPE_NOT_SUPPORTED; 381 382 s = splbio(); 383 384 if ( (acb = dev->free_list.tqh_first) != NULL ) 385 TAILQ_REMOVE(&dev->free_list, acb, chain); 386 387 splx(s); 388 389 if ( acb == NULL ) { 390 #ifdef DEBUG 391 printf("sbic_scsicmd: unable to queue request for target %d\n", 392 slp->target); 393 #ifdef DDB 394 Debugger(); 395 #endif 396 #endif 397 xs->error = XS_DRIVER_STUFFUP; 398 399 return(TRY_AGAIN_LATER); 400 } 401 402 if ( flags & SCSI_DATA_IN ) 403 acb->flags = ACB_ACTIVE | ACB_DATAIN; 404 else 405 acb->flags = ACB_ACTIVE; 406 407 acb->xs = xs; 408 acb->clen = xs->cmdlen; 409 acb->sc_kv.dc_addr = xs->data; 410 acb->sc_kv.dc_count = xs->datalen; 411 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; 412 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 413 414 if ( flags & SCSI_POLL ) { 415 /* 416 * This has major side effects -- it locks up the machine 417 */ 418 int stat; 419 420 s = splbio(); 421 422 dev->sc_flags |= SBICF_ICMD; 423 424 do { 425 /* 426 * If we already had a nexus, while away the time until idle... 427 * This is likely only to happen if a reselection occurs between 428 * here and our earlier check for ICMD && sc_nexus (which would 429 * have resulted in a panic() had it been true). 430 */ 431 while ( dev->sc_nexus ) 432 sbicpoll(dev); 433 434 /* 435 * Fix up the new nexus 436 */ 437 dev->sc_nexus = acb; 438 dev->sc_xs = xs; 439 dev->target = slp->target; 440 dev->lun = slp->lun; 441 442 stat = sbicicmd(dev, &acb->cmd, acb->clen, 443 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 444 445 } while ( dev->sc_nexus != acb ); 446 447 sbic_scsidone(acb, stat); 448 449 splx(s); 450 451 return(COMPLETE); 452 } 453 454 s = splbio(); 455 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 456 457 /* 458 * If nothing is active, try to start it now. 459 */ 460 if ( dev->sc_nexus == NULL ) 461 sbic_sched(dev); 462 463 splx(s); 464 465 return(SUCCESSFULLY_QUEUED); 466 } 467 468 /* 469 * attempt to start the next available command 470 */ 471 void 472 sbic_sched(dev) 473 struct sbic_softc *dev; 474 { 475 struct scsi_xfer *xs; 476 struct scsi_link *slp = NULL; /* Gag the compiler */ 477 struct sbic_acb *acb; 478 int flags, 479 stat; 480 481 /* 482 * XXXSCW 483 * I'll keep this test here, even though I can't see any obvious way 484 * in which sbic_sched() could be called with sc_nexus non NULL 485 */ 486 if ( dev->sc_nexus ) 487 return; /* a command is current active */ 488 489 /* 490 * Loop through the ready list looking for work to do... 491 */ 492 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 493 int i, j; 494 495 slp = acb->xs->sc_link; 496 i = slp->target; 497 j = 1 << slp->lun; 498 499 /* 500 * We've found a potential command, but is the target/lun busy? 501 */ 502 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 503 /* 504 * Nope, it's not busy, so we can use it. 505 */ 506 dev->sc_tinfo[i].lubusy |= j; 507 TAILQ_REMOVE(&dev->ready_list, acb, chain); 508 dev->sc_nexus = acb; 509 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 510 break; 511 } 512 } 513 514 if ( acb == NULL ) { 515 QPRINTF(("sbicsched: no work\n")); 516 return; /* did not find an available command */ 517 } 518 519 #ifdef DEBUG 520 if ( data_pointer_debug > 1 ) 521 printf("sbic_sched(%d,%d)\n", slp->target, slp->lun); 522 #endif 523 524 dev->sc_xs = xs = acb->xs; 525 flags = xs->flags; 526 527 if ( flags & SCSI_RESET ) 528 sbicreset(dev); 529 530 dev->sc_stat[0] = -1; 531 dev->target = slp->target; 532 dev->lun = slp->lun; 533 534 if ( flags & SCSI_POLL || (!sbic_parallel_operations && 535 (sbicdmaok(dev, xs) == 0)) ) 536 stat = sbicicmd(dev, &acb->cmd, acb->clen, 537 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 538 else 539 if ( sbicgo(dev, xs) == 0 ) 540 return; 541 else 542 stat = dev->sc_stat[0]; 543 544 sbic_scsidone(acb, stat); 545 } 546 547 void 548 sbic_scsidone(acb, stat) 549 struct sbic_acb *acb; 550 int stat; 551 { 552 struct scsi_xfer *xs = acb->xs; 553 struct scsi_link *slp = xs->sc_link; 554 struct sbic_softc *dev = slp->adapter_softc; 555 int dosched = 0; 556 557 #ifdef DIAGNOSTIC 558 if ( acb == NULL || xs == NULL ) { 559 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", dev->target, dev->lun); 560 #ifdef DDB 561 Debugger(); 562 #endif 563 return; 564 } 565 #endif 566 567 /* 568 * is this right? 569 */ 570 xs->status = stat; 571 572 #ifdef DEBUG 573 if ( data_pointer_debug > 1 ) 574 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", slp->target, slp->lun, 575 dev->target, dev->lun, stat); 576 577 if ( xs->sc_link->target == dev->sc_link.adapter_target ) 578 panic("target == hostid"); 579 #endif 580 581 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) == 0 ) { 582 583 if ( stat == SCSI_CHECK ) { 584 /* 585 * Schedule a REQUEST SENSE 586 */ 587 struct scsi_sense *ss = (void *)&acb->cmd; 588 589 #ifdef DEBUG 590 if ( report_sense ) 591 printf("sbic_scsidone: autosense %02x targ %d lun %d", 592 acb->cmd.opcode, slp->target, slp->lun); 593 #endif 594 595 bzero(ss, sizeof(*ss)); 596 597 ss->opcode = REQUEST_SENSE; 598 ss->byte2 = slp->lun << 5; 599 ss->length = sizeof(struct scsi_sense_data); 600 601 acb->clen = sizeof(*ss); 602 acb->sc_kv.dc_addr = (char *)&xs->sense; 603 acb->sc_kv.dc_count = sizeof(struct scsi_sense_data); 604 acb->pa_addr = (char *)kvtop(&xs->sense); /* XXX check */ 605 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 606 607 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 608 609 dev->sc_tinfo[slp->target].lubusy &= ~(1 << slp->lun); 610 dev->sc_tinfo[slp->target].senses++; 611 612 if ( dev->sc_nexus == acb ) { 613 dev->sc_nexus = NULL; 614 dev->sc_xs = NULL; 615 sbic_sched(dev); 616 } 617 return; 618 } 619 } 620 621 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) != 0 ) { 622 623 xs->error = XS_SENSE; 624 625 #ifdef DEBUG 626 if (report_sense) 627 printf(" => %02x %02x\n", xs->sense.flags, 628 xs->sense.extra_bytes[3]); 629 #endif 630 631 } else { 632 xs->resid = 0; /* XXXX */ 633 } 634 635 xs->flags |= ITSDONE; 636 637 /* 638 * Remove the ACB from whatever queue it's on. We have to do a bit of 639 * a hack to figure out which queue it's on. Note that it is *not* 640 * necessary to cdr down the ready queue, but we must cdr down the 641 * nexus queue and see if it's there, so we can mark the unit as no 642 * longer busy. This code is sickening, but it works. 643 */ 644 if ( acb == dev->sc_nexus ) { 645 646 dev->sc_nexus = NULL; 647 dev->sc_xs = NULL; 648 649 dev->sc_tinfo[slp->target].lubusy &= ~(1 << slp->lun); 650 651 if ( dev->ready_list.tqh_first ) 652 dosched = 1; /* start next command */ 653 654 } else 655 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 656 657 TAILQ_REMOVE(&dev->ready_list, acb, chain); 658 659 } else { 660 661 register struct sbic_acb *a; 662 663 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 664 if ( a == acb ) { 665 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 666 dev->sc_tinfo[slp->target].lubusy &= ~(1 << slp->lun); 667 break; 668 } 669 } 670 671 if ( a ) 672 ; 673 else if ( acb->chain.tqe_next ) { 674 TAILQ_REMOVE(&dev->ready_list, acb, chain); 675 } else { 676 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 677 #ifdef DDB 678 Debugger(); 679 #endif 680 } 681 } 682 683 /* 684 * Put it on the free list. 685 */ 686 acb->flags = ACB_FREE; 687 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 688 689 dev->sc_tinfo[slp->target].cmds++; 690 691 scsi_done(xs); 692 693 if ( dosched ) 694 sbic_sched(dev); 695 } 696 697 int 698 sbicdmaok(dev, xs) 699 struct sbic_softc *dev; 700 struct scsi_xfer *xs; 701 { 702 if ( sbic_no_dma || xs->datalen & 0x03 || (int)xs->data & 0x03) 703 return(0); 704 705 /* 706 * controller supports dma to any addresses? 707 */ 708 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 709 return(1); 710 711 /* 712 * this address is ok for dma? 713 */ 714 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 715 return(1); 716 717 return(0); 718 } 719 720 int 721 sbicwait(regs, until, timeo, line) 722 sbic_regmap_p regs; 723 u_char until; 724 int timeo; 725 int line; 726 { 727 u_char val; 728 729 if ( timeo == 0 ) 730 timeo = 1000000; /* some large value.. */ 731 732 GET_SBIC_asr(regs, val); 733 734 while ( (val & until) == 0 ) { 735 736 if ( timeo-- == 0 ) { 737 int csr; 738 GET_SBIC_csr(regs, csr); 739 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 740 #if defined(DDB) && defined(DEBUG) 741 Debugger(); 742 #endif 743 return(val); /* Maybe I should abort */ 744 break; 745 } 746 747 DELAY(1); 748 GET_SBIC_asr(regs, val); 749 } 750 751 return(val); 752 } 753 754 int 755 sbicabort(dev, where) 756 struct sbic_softc *dev; 757 char *where; 758 { 759 sbic_regmap_p regs = dev->sc_sbicp; 760 u_char csr, 761 asr; 762 763 GET_SBIC_asr(regs, asr); 764 GET_SBIC_csr(regs, csr); 765 766 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 767 dev->sc_dev.dv_xname, where, csr, asr); 768 769 /* 770 * Clean up chip itself 771 */ 772 if ( dev->sc_flags & SBICF_SELECTED ) { 773 774 while ( asr & SBIC_ASR_DBR ) { 775 /* 776 * sbic is jammed w/data. need to clear it 777 * But we don't know what direction it needs to go 778 */ 779 GET_SBIC_data(regs, asr); 780 printf("%s: abort %s: clearing data buffer 0x%02x\n", 781 dev->sc_dev.dv_xname, where, asr); 782 GET_SBIC_asr(regs, asr); 783 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 784 SET_SBIC_data(regs, asr); 785 GET_SBIC_asr(regs, asr); 786 } 787 788 WAIT_CIP(regs); 789 790 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 791 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 792 WAIT_CIP(regs); 793 794 GET_SBIC_asr(regs, asr); 795 796 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 797 /* 798 * ok, get more drastic.. 799 */ 800 printf("%s: sbicabort - asr %x, trying to reset\n", 801 dev->sc_dev.dv_xname, asr); 802 sbicreset(dev); 803 dev->sc_flags &= ~SBICF_SELECTED; 804 return SBIC_STATE_ERROR; 805 } 806 807 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 808 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 809 810 do { 811 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 812 GET_SBIC_asr(regs, asr); 813 GET_SBIC_csr (regs, csr); 814 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 815 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 816 (csr != SBIC_CSR_CMD_INVALID) ); 817 818 /* 819 * lets just hope it worked.. 820 */ 821 dev->sc_flags &= ~SBICF_SELECTED; 822 } 823 824 return SBIC_STATE_ERROR; 825 } 826 827 828 /* 829 * Initialize driver-private structures 830 */ 831 void 832 sbicinit(dev) 833 struct sbic_softc *dev; 834 { 835 u_int i; 836 837 extern u_long scsi_nosync; 838 extern int shift_nosync; 839 840 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 841 842 struct sbic_acb *acb; 843 844 TAILQ_INIT(&dev->ready_list); 845 TAILQ_INIT(&dev->nexus_list); 846 TAILQ_INIT(&dev->free_list); 847 848 dev->sc_nexus = NULL; 849 dev->sc_xs = NULL; 850 851 acb = dev->sc_acb; 852 bzero(acb, sizeof(dev->sc_acb)); 853 854 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 855 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 856 acb++; 857 } 858 859 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 860 861 #ifdef DEBUG 862 /* 863 * make sure timeout is really not needed 864 */ 865 timeout((void *)sbictimeout, dev, 30 * hz); 866 #endif 867 868 } else 869 panic("sbic: reinitializing driver!"); 870 871 dev->sc_flags |= SBICF_ALIVE; 872 dev->sc_flags &= ~SBICF_SELECTED; 873 874 /* 875 * initialize inhibit array 876 */ 877 if ( scsi_nosync ) { 878 879 u_int inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 880 881 shift_nosync += 8; 882 883 #ifdef DEBUG 884 if ( inhibit_sync ) 885 printf("%s: Inhibiting synchronous transfer %02x\n", 886 dev->sc_dev.dv_xname, inhibit_sync); 887 #endif 888 for (i = 0; i < 8; ++i) { 889 if ( inhibit_sync & (1 << i) ) 890 sbic_inhibit_sync[i] = 1; 891 } 892 } 893 894 sbicreset(dev); 895 } 896 897 void 898 sbicreset(dev) 899 struct sbic_softc *dev; 900 { 901 sbic_regmap_p regs = dev->sc_sbicp; 902 u_int my_id, 903 s; 904 u_char csr; 905 906 s = splbio(); 907 908 my_id = dev->sc_link.adapter_target & SBIC_ID_MASK; 909 910 if (dev->sc_clkfreq < 110) 911 my_id |= SBIC_ID_FS_8_10; 912 else if (dev->sc_clkfreq < 160) 913 my_id |= SBIC_ID_FS_12_15; 914 else if (dev->sc_clkfreq < 210) 915 my_id |= SBIC_ID_FS_16_20; 916 917 SET_SBIC_myid(regs, my_id); 918 919 /* 920 * Reset the chip 921 */ 922 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 923 DELAY(25); 924 925 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 926 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 927 928 /* 929 * Set up various chip parameters 930 */ 931 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 932 933 /* 934 * don't allow Selection (SBIC_RID_ES) 935 * until we can handle target mode!! 936 */ 937 SET_SBIC_rselid(regs, SBIC_RID_ER); 938 939 /* 940 * Asynchronous for now 941 */ 942 SET_SBIC_syn(regs, 0); 943 944 /* 945 * Anything else was zeroed by reset 946 */ 947 splx(s); 948 949 dev->sc_flags &= ~SBICF_SELECTED; 950 } 951 952 void 953 sbicerror(dev, csr) 954 struct sbic_softc *dev; 955 u_char csr; 956 { 957 struct scsi_xfer *xs = dev->sc_xs; 958 959 #ifdef DIAGNOSTIC 960 if ( xs == NULL ) 961 panic("sbicerror: dev->sc_xs == NULL"); 962 #endif 963 964 if ( xs->flags & SCSI_SILENT ) 965 return; 966 967 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 968 } 969 970 /* 971 * select the bus, return when selected or error. 972 * 973 * Returns the current CSR following selection and optionally MSG out phase. 974 * i.e. the returned CSR *should* indicate CMD phase... 975 * If the return value is 0, some error happened. 976 */ 977 u_char 978 sbicselectbus(dev) 979 struct sbic_softc *dev; 980 { 981 sbic_regmap_p regs = dev->sc_sbicp; 982 u_char target = dev->target, 983 lun = dev->lun, 984 asr, 985 csr, 986 id; 987 988 /* 989 * if we're already selected, return (XXXX panic maybe?) 990 */ 991 if ( dev->sc_flags & SBICF_SELECTED ) 992 return(0); 993 994 QPRINTF(("sbicselectbus %d: ", target)); 995 996 /* 997 * issue select 998 */ 999 SET_SBIC_selid(regs, target); 1000 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 1001 1002 GET_SBIC_asr(regs, asr); 1003 1004 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1005 /* 1006 * This means we got ourselves reselected upon 1007 */ 1008 QPRINTF(("WD busy (reselect?)\n")); 1009 return 0; 1010 } 1011 1012 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1013 1014 /* 1015 * wait for select (merged from seperate function may need 1016 * cleanup) 1017 */ 1018 WAIT_CIP(regs); 1019 1020 do { 1021 1022 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1023 1024 if ( asr & SBIC_ASR_LCI ) { 1025 QPRINTF(("late LCI: asr %02x\n", asr)); 1026 return 0; 1027 } 1028 1029 /* 1030 * Clear interrupt 1031 */ 1032 GET_SBIC_csr (regs, csr); 1033 1034 QPRINTF(("%02x ", csr)); 1035 1036 /* 1037 * Reselected from under our feet? 1038 */ 1039 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 1040 QPRINTF(("got reselected, asr %02x\n", asr)); 1041 /* 1042 * We need to handle this now so we don't lock up later 1043 */ 1044 sbicnextstate(dev, csr, asr); 1045 1046 return 0; 1047 } 1048 1049 /* 1050 * Whoops! 1051 */ 1052 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1053 panic("sbicselectbus: target issued select!"); 1054 return 0; 1055 } 1056 1057 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1058 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1059 csr != SBIC_CSR_SEL_TIMEO); 1060 1061 /* 1062 * Anyone at home? 1063 */ 1064 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1065 dev->sc_xs->error = XS_SELTIMEOUT; 1066 QPRINTF(("Selection Timeout\n")); 1067 return 0; 1068 } 1069 1070 QPRINTF(("Selection Complete\n")); 1071 1072 /* 1073 * Assume we're now selected 1074 */ 1075 GET_SBIC_selid(regs, id); 1076 dev->target = id; 1077 dev->lun = lun; 1078 dev->sc_flags |= SBICF_SELECTED; 1079 1080 /* 1081 * Enable (or not) reselection 1082 * XXXSCW This is probably not necessary since we don't use use the 1083 * Select-and-Xfer-with-ATN command to initiate a selection... 1084 */ 1085 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1086 SET_SBIC_rselid (regs, 0); 1087 else 1088 SET_SBIC_rselid (regs, SBIC_RID_ER); 1089 1090 /* 1091 * We only really need to do anything when the target goes to MSG out 1092 * If the device ignored ATN, it's probably old and brain-dead, 1093 * but we'll try to support it anyhow. 1094 * If it doesn't support message out, it definately doesn't 1095 * support synchronous transfers, so no point in even asking... 1096 */ 1097 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1098 /* 1099 * Send identify message (SCSI-2 requires an identify msg) 1100 */ 1101 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1102 /* 1103 * Handle drives that don't want to be asked 1104 * whether to go sync at all. 1105 */ 1106 dev->sc_sync[id].offset = 0; 1107 dev->sc_sync[id].period = sbic_min_period; 1108 dev->sc_sync[id].state = SYNC_DONE; 1109 } 1110 1111 /* 1112 * Do we need to negotiate Synchronous Xfers for this target? 1113 */ 1114 if ( dev->sc_sync[id].state != SYNC_START ) { 1115 /* 1116 * Nope, we've already negotiated. 1117 * Now see if we should allow the target to disconnect/reselect... 1118 */ 1119 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 1120 !sbic_enable_reselect ) 1121 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1122 else 1123 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1124 1125 } else { 1126 /* 1127 * try to initiate a sync transfer. 1128 * So compose the sync message we're going 1129 * to send to the target 1130 */ 1131 #ifdef DEBUG 1132 if ( sync_debug ) 1133 printf("\nSending sync request to target %d ... ", id); 1134 #endif 1135 /* 1136 * setup scsi message sync message request 1137 */ 1138 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1139 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1140 dev->sc_msg[2] = 3; 1141 dev->sc_msg[3] = MSG_SYNC_REQ; 1142 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1143 dev->sc_msg[5] = sbic_max_offset; 1144 1145 sbicxfout(regs, 6, dev->sc_msg); 1146 1147 dev->sc_sync[id].state = SYNC_SENT; 1148 #ifdef DEBUG 1149 if ( sync_debug ) 1150 printf ("sent\n"); 1151 #endif 1152 } 1153 1154 /* 1155 * There's one interrupt still to come: the change to CMD phase... 1156 */ 1157 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1158 GET_SBIC_csr(regs, csr); 1159 } 1160 1161 /* 1162 * set sync or async 1163 */ 1164 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1165 #ifdef DEBUG 1166 if ( sync_debug ) 1167 printf("select(%d): sync reg = 0x%02x\n", target, 1168 SBIC_SYN(dev->sc_sync[target].offset, 1169 dev->sc_sync[target].period)); 1170 #endif 1171 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1172 dev->sc_sync[target].period)); 1173 } else { 1174 #ifdef DEBUG 1175 if ( sync_debug ) 1176 printf("select(%d): sync reg = 0x%02x\n", target, 1177 SBIC_SYN(0,sbic_min_period)); 1178 #endif 1179 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1180 } 1181 1182 return csr; 1183 } 1184 1185 /* 1186 * Information Transfer *to* a Scsi Target. 1187 * 1188 * Note: Don't expect there to be an interrupt immediately after all 1189 * the data is transferred out. The WD spec sheet says that the Transfer- 1190 * Info command for non-MSG_IN phases only completes when the target 1191 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1192 * 1193 * This can have a nasty effect on commands which take a relatively long 1194 * time to complete, for example a START/STOP unit command may remain in 1195 * CMD phase until the disk has spun up. Only then will the target change 1196 * to STATUS phase. This is really only a problem for immediate commands 1197 * since we don't allow disconnection for them (yet). 1198 */ 1199 int 1200 sbicxfout(regs, len, bp) 1201 sbic_regmap_p regs; 1202 int len; 1203 void *bp; 1204 { 1205 int wait = sbic_data_wait; 1206 u_char asr, 1207 *buf = bp; 1208 1209 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1210 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1211 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1212 1213 /* 1214 * sigh.. WD-PROTO strikes again.. sending the command in one go 1215 * causes the chip to lock up if talking to certain (misbehaving?) 1216 * targets. Anyway, this procedure should work for all targets, but 1217 * it's slightly slower due to the overhead 1218 */ 1219 WAIT_CIP (regs); 1220 1221 SBIC_TC_PUT (regs, 0); 1222 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1223 SBIC_TC_PUT (regs, (unsigned)len); 1224 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1225 1226 /* 1227 * Loop for each byte transferred 1228 */ 1229 do { 1230 1231 GET_SBIC_asr (regs, asr); 1232 1233 if ( asr & SBIC_ASR_DBR ) { 1234 if ( len ) { 1235 SET_SBIC_data (regs, *buf); 1236 buf++; 1237 len--; 1238 } else { 1239 SET_SBIC_data (regs, 0); 1240 } 1241 wait = sbic_data_wait; 1242 } 1243 1244 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1245 1246 #ifdef DEBUG 1247 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1248 #endif 1249 1250 /* 1251 * Normally, an interrupt will be pending when this routing returns. 1252 */ 1253 return(len); 1254 } 1255 1256 /* 1257 * Information Transfer *from* a Scsi Target 1258 * returns # bytes left to read 1259 */ 1260 int 1261 sbicxfin(regs, len, bp) 1262 sbic_regmap_p regs; 1263 int len; 1264 void *bp; 1265 { 1266 int wait = sbic_data_wait; 1267 u_char *buf = bp; 1268 u_char asr; 1269 #ifdef DEBUG 1270 u_char *obp = bp; 1271 #endif 1272 1273 WAIT_CIP (regs); 1274 1275 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1276 SBIC_TC_PUT (regs, (unsigned)len); 1277 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1278 1279 /* 1280 * Loop for each byte transferred 1281 */ 1282 do { 1283 1284 GET_SBIC_asr (regs, asr); 1285 1286 if ( asr & SBIC_ASR_DBR ) { 1287 if ( len ) { 1288 GET_SBIC_data (regs, *buf); 1289 buf++; 1290 len--; 1291 } else { 1292 u_char foo; 1293 GET_SBIC_data (regs, foo); 1294 } 1295 wait = sbic_data_wait; 1296 } 1297 1298 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1299 1300 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1301 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1302 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1303 1304 SBIC_TC_PUT (regs, 0); 1305 1306 /* 1307 * this leaves with one csr to be read 1308 */ 1309 return len; 1310 } 1311 1312 /* 1313 * SCSI 'immediate' command: issue a command to some SCSI device 1314 * and get back an 'immediate' response (i.e., do programmed xfer 1315 * to get the response data). 'cbuf' is a buffer containing a scsi 1316 * command of length clen bytes. 'buf' is a buffer of length 'len' 1317 * bytes for data. The transfer direction is determined by the device 1318 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1319 * command must supply no data. 1320 * 1321 * Note that although this routine looks like it can handle disconnect/ 1322 * reselect, the fact is that it can't. There is still some work to be 1323 * done to clean this lot up. 1324 */ 1325 int 1326 sbicicmd(dev, cbuf, clen, buf, len) 1327 struct sbic_softc *dev; 1328 void *cbuf, 1329 *buf; 1330 int clen, 1331 len; 1332 { 1333 sbic_regmap_p regs = dev->sc_sbicp; 1334 struct sbic_acb *acb = dev->sc_nexus; 1335 u_char csr, 1336 asr; 1337 int still_busy = SBIC_STATE_RUNNING; 1338 #ifdef DEBUG 1339 int counter = 0; 1340 #endif 1341 1342 /* 1343 * Make sure pointers are OK 1344 */ 1345 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1346 dev->sc_tcnt = acb->sc_tcnt = 0; 1347 1348 acb->sc_dmacmd = 0; 1349 acb->sc_pa.dc_count = 0; /* No DMA */ 1350 acb->sc_kv.dc_addr = buf; 1351 acb->sc_kv.dc_count = len; 1352 1353 #ifdef DEBUG 1354 if ( data_pointer_debug > 1 ) 1355 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1356 #endif 1357 1358 /* 1359 * set the sbic into non-DMA mode 1360 */ 1361 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1362 1363 dev->sc_stat[0] = 0xff; 1364 dev->sc_msg[0] = 0xff; 1365 1366 /* 1367 * We're stealing the SCSI bus 1368 */ 1369 dev->sc_flags |= SBICF_ICMD; 1370 1371 do { 1372 GET_SBIC_asr (regs, asr); 1373 1374 /* 1375 * select the SCSI bus (it's an error if bus isn't free) 1376 */ 1377 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1378 still_busy != SBIC_STATE_DISCONNECT ) { 1379 if ( (csr = sbicselectbus(dev)) == 0 ) { 1380 dev->sc_flags &= ~SBICF_ICMD; 1381 return(-1); 1382 } 1383 } else 1384 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1385 GET_SBIC_csr(regs, csr); 1386 else 1387 csr = 0; 1388 1389 if ( csr ) { 1390 1391 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1392 1393 switch ( csr ) { 1394 1395 case SBIC_CSR_S_XFERRED: 1396 case SBIC_CSR_DISC: 1397 case SBIC_CSR_DISC_1: 1398 { 1399 u_char phase; 1400 1401 dev->sc_flags &= ~SBICF_SELECTED; 1402 GET_SBIC_cmd_phase (regs, phase); 1403 1404 if ( phase == 0x60 ) { 1405 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1406 still_busy = SBIC_STATE_DONE; /* done */ 1407 } else { 1408 #ifdef DEBUG 1409 if ( reselect_debug > 1 ) 1410 printf("sbicicmd: handling disconnect\n"); 1411 #endif 1412 still_busy = SBIC_STATE_DISCONNECT; 1413 } 1414 } 1415 break; 1416 1417 case SBIC_CSR_XFERRED | CMD_PHASE: 1418 case SBIC_CSR_MIS | CMD_PHASE: 1419 case SBIC_CSR_MIS_1 | CMD_PHASE: 1420 case SBIC_CSR_MIS_2 | CMD_PHASE: 1421 { 1422 if ( sbicxfout(regs, clen, cbuf) ) 1423 still_busy = sbicabort(dev, "icmd sending cmd"); 1424 } 1425 break; 1426 1427 case SBIC_CSR_XFERRED | STATUS_PHASE: 1428 case SBIC_CSR_MIS | STATUS_PHASE: 1429 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1430 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1431 { 1432 /* 1433 * The sbic does the status/cmd-complete reading ok, 1434 * so do this with its hi-level commands. 1435 */ 1436 #ifdef DEBUG 1437 if ( sbic_debug ) 1438 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1439 #endif 1440 SET_SBIC_cmd_phase(regs, 0x46); 1441 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1442 } 1443 break; 1444 1445 default: 1446 { 1447 still_busy = sbicnextstate(dev, csr, asr); 1448 } 1449 break; 1450 } 1451 1452 /* 1453 * make sure the last command was taken, 1454 * ie. we're not hunting after an ignored command.. 1455 */ 1456 GET_SBIC_asr(regs, asr); 1457 1458 /* 1459 * tapes may take a loooong time.. 1460 */ 1461 while (asr & SBIC_ASR_BSY ) { 1462 1463 if ( asr & SBIC_ASR_DBR ) { 1464 int i; 1465 1466 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1467 #ifdef DDB 1468 Debugger(); 1469 #endif 1470 /* 1471 * SBIC is jammed 1472 * DUNNO which direction 1473 * Try old direction 1474 */ 1475 GET_SBIC_data(regs, i); 1476 GET_SBIC_asr(regs, asr); 1477 1478 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1479 SET_SBIC_data(regs, i); 1480 } 1481 1482 GET_SBIC_asr(regs, asr); 1483 } 1484 } 1485 1486 /* 1487 * wait for last command to complete 1488 */ 1489 if ( asr & SBIC_ASR_LCI ) { 1490 printf("sbicicmd: last command ignored\n"); 1491 } 1492 else 1493 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1494 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1495 1496 /* 1497 * do it again 1498 */ 1499 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1500 1501 /* 1502 * Sometimes we need to do an extra read of the CSR 1503 */ 1504 GET_SBIC_csr(regs, csr); 1505 1506 #ifdef DEBUG 1507 if ( data_pointer_debug > 1 ) 1508 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1509 acb->sc_kv.dc_count, 1510 dev->sc_stat[0]); 1511 #endif 1512 1513 dev->sc_flags &= ~SBICF_ICMD; 1514 1515 return(dev->sc_stat[0]); 1516 } 1517 1518 /* 1519 * Finish SCSI xfer command: After the completion interrupt from 1520 * a read/write operation, sequence through the final phases in 1521 * programmed i/o. This routine is a lot like sbicicmd except we 1522 * skip (and don't allow) the select, cmd out and data in/out phases. 1523 */ 1524 void 1525 sbicxfdone(dev) 1526 struct sbic_softc *dev; 1527 { 1528 sbic_regmap_p regs = dev->sc_sbicp; 1529 u_char phase, 1530 csr; 1531 int s; 1532 1533 QPRINTF(("{")); 1534 s = splbio(); 1535 1536 /* 1537 * have the sbic complete on its own 1538 */ 1539 SBIC_TC_PUT(regs, 0); 1540 SET_SBIC_cmd_phase(regs, 0x46); 1541 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1542 1543 do { 1544 1545 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1546 GET_SBIC_csr (regs, csr); 1547 QPRINTF(("%02x:", csr)); 1548 1549 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1550 (csr != SBIC_CSR_S_XFERRED)); 1551 1552 dev->sc_flags &= ~SBICF_SELECTED; 1553 1554 GET_SBIC_cmd_phase (regs, phase); 1555 QPRINTF(("}%02x", phase)); 1556 1557 if ( phase == 0x60 ) 1558 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1559 else 1560 sbicerror(dev, csr); 1561 1562 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1563 1564 splx(s); 1565 } 1566 1567 /* 1568 * No DMA chains 1569 */ 1570 int 1571 sbicgo(dev, xs) 1572 struct sbic_softc *dev; 1573 struct scsi_xfer *xs; 1574 { 1575 struct sbic_acb *acb = dev->sc_nexus; 1576 sbic_regmap_p regs = dev->sc_sbicp; 1577 int i, 1578 dmaflags, 1579 count, 1580 usedma; 1581 u_char csr, 1582 asr, 1583 *addr; 1584 1585 dev->target = xs->sc_link->target; 1586 dev->lun = xs->sc_link->lun; 1587 1588 usedma = sbicdmaok(dev, xs); 1589 1590 #ifdef DEBUG 1591 if ( data_pointer_debug > 1 ) 1592 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1593 #endif 1594 1595 /* 1596 * select the SCSI bus (it's an error if bus isn't free) 1597 */ 1598 if ( (csr = sbicselectbus(dev)) == 0 ) 1599 return(0); /* Not done: needs to be rescheduled */ 1600 1601 dev->sc_stat[0] = 0xff; 1602 1603 /* 1604 * Calculate DMA chains now 1605 */ 1606 if ( acb->flags & ACB_DATAIN ) 1607 dmaflags = DMAGO_READ; 1608 else 1609 dmaflags = 0; 1610 1611 addr = acb->sc_kv.dc_addr; 1612 count = acb->sc_kv.dc_count; 1613 1614 if ( count && ((char *)kvtop(addr) != acb->sc_pa.dc_addr) ) { 1615 printf("sbic: DMA buffer mapping changed %x->%x\n", 1616 acb->sc_pa.dc_addr, kvtop(addr)); 1617 #ifdef DDB 1618 Debugger(); 1619 #endif 1620 } 1621 1622 #ifdef DEBUG 1623 ++sbicdma_ops; /* count total DMA operations */ 1624 #endif 1625 1626 /* 1627 * Allocate the DMA chain 1628 * Mark end of segment... 1629 */ 1630 acb->sc_tcnt = dev->sc_tcnt = 0; 1631 acb->sc_pa.dc_count = 0; 1632 1633 sbic_load_ptrs(dev); 1634 1635 /* 1636 * Enable interrupts but don't do any DMA 1637 * enintr() also enables interrupts for the sbic 1638 */ 1639 dev->sc_enintr(dev); 1640 1641 if ( usedma ) { 1642 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1643 acb->sc_pa.dc_count, dmaflags); 1644 #ifdef DEBUG 1645 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1646 #endif 1647 } else 1648 dev->sc_dmacmd = 0; /* Don't use DMA */ 1649 1650 acb->sc_dmacmd = dev->sc_dmacmd; 1651 1652 #ifdef DEBUG 1653 if ( data_pointer_debug > 1 ) { 1654 printf("sbicgo dmago:%d(%x:%x) dmacmd=0x%02x\n", dev->target, 1655 dev->sc_cur->dc_addr, 1656 dev->sc_tcnt, 1657 dev->sc_dmacmd); 1658 } 1659 #endif 1660 1661 /* 1662 * Lets cycle a while then let the interrupt handler take over. 1663 */ 1664 GET_SBIC_asr(regs, asr); 1665 1666 do { 1667 1668 QPRINTF(("go ")); 1669 1670 /* 1671 * Handle the new phase 1672 */ 1673 i = sbicnextstate(dev, csr, asr); 1674 #if 0 1675 WAIT_CIP(regs); 1676 #endif 1677 if ( i == SBIC_STATE_RUNNING ) { 1678 GET_SBIC_asr(regs, asr); 1679 1680 if ( asr & SBIC_ASR_LCI ) 1681 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1682 1683 if ( asr & SBIC_ASR_INT ) 1684 GET_SBIC_csr(regs, csr); 1685 } 1686 1687 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1688 1689 if ( i == SBIC_STATE_DONE ) { 1690 if ( dev->sc_stat[0] == 0xff ) 1691 #if 0 1692 printf("sbicgo: done & stat = 0xff\n"); 1693 #else 1694 ; 1695 #endif 1696 else 1697 return 1; /* Did we really finish that fast? */ 1698 } 1699 1700 return 0; 1701 } 1702 1703 1704 int 1705 sbicintr(dev) 1706 struct sbic_softc *dev; 1707 { 1708 sbic_regmap_p regs = dev->sc_sbicp; 1709 u_char asr, 1710 csr; 1711 int i; 1712 1713 /* 1714 * pending interrupt? 1715 */ 1716 GET_SBIC_asr (regs, asr); 1717 if ( (asr & SBIC_ASR_INT) == 0 ) 1718 return(0); 1719 1720 GET_SBIC_csr(regs, csr); 1721 1722 do { 1723 1724 QPRINTF(("intr[0x%x]", csr)); 1725 1726 i = sbicnextstate(dev, csr, asr); 1727 #if 0 1728 WAIT_CIP(regs); 1729 #endif 1730 if ( i == SBIC_STATE_RUNNING ) { 1731 GET_SBIC_asr(regs, asr); 1732 1733 if ( asr & SBIC_ASR_LCI ) 1734 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1735 1736 if ( asr & SBIC_ASR_INT ) 1737 GET_SBIC_csr(regs, csr); 1738 } 1739 1740 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1741 1742 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1743 1744 return(1); 1745 } 1746 1747 /* 1748 * Run commands and wait for disconnect. 1749 * This is only ever called when a command is in progress, when we 1750 * want to busy wait for it to finish. 1751 */ 1752 int 1753 sbicpoll(dev) 1754 struct sbic_softc *dev; 1755 { 1756 sbic_regmap_p regs = dev->sc_sbicp; 1757 u_char asr, 1758 csr; 1759 int i; 1760 1761 /* 1762 * Wait for the next interrupt 1763 */ 1764 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1765 1766 do { 1767 GET_SBIC_asr (regs, asr); 1768 1769 if ( asr & SBIC_ASR_INT ) 1770 GET_SBIC_csr(regs, csr); 1771 1772 QPRINTF(("poll[0x%x]", csr)); 1773 1774 /* 1775 * Handle it 1776 */ 1777 i = sbicnextstate(dev, csr, asr); 1778 1779 WAIT_CIP(regs); 1780 GET_SBIC_asr(regs, asr); 1781 1782 /* 1783 * tapes may take a loooong time.. 1784 */ 1785 while ( asr & SBIC_ASR_BSY ) { 1786 u_char z = 0; 1787 1788 if ( asr & SBIC_ASR_DBR ) { 1789 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1790 #ifdef DDB 1791 Debugger(); 1792 #endif 1793 /* 1794 * SBIC is jammed 1795 * DUNNO which direction 1796 * Try old direction 1797 */ 1798 GET_SBIC_data(regs, z); 1799 GET_SBIC_asr(regs, asr); 1800 1801 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1802 SET_SBIC_data(regs, z); 1803 } 1804 1805 GET_SBIC_asr(regs, asr); 1806 } 1807 1808 if ( asr & SBIC_ASR_LCI ) 1809 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1810 else 1811 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1812 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1813 1814 } while ( i == SBIC_STATE_RUNNING ); 1815 1816 return(1); 1817 } 1818 1819 /* 1820 * Handle a single msgin 1821 */ 1822 int 1823 sbicmsgin(dev) 1824 struct sbic_softc *dev; 1825 { 1826 sbic_regmap_p regs = dev->sc_sbicp; 1827 int recvlen = 1; 1828 u_char asr, 1829 csr, 1830 *tmpaddr, 1831 *msgaddr; 1832 1833 tmpaddr = msgaddr = dev->sc_msg; 1834 1835 tmpaddr[0] = 0xff; 1836 tmpaddr[1] = 0xff; 1837 1838 GET_SBIC_asr(regs, asr); 1839 1840 #ifdef DEBUG 1841 if ( reselect_debug > 1 ) 1842 printf("sbicmsgin asr=%02x\n", asr); 1843 #endif 1844 1845 GET_SBIC_selid (regs, csr); 1846 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1847 1848 SBIC_TC_PUT(regs, 0); 1849 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1850 1851 do { 1852 while( recvlen-- ) { 1853 1854 /* 1855 * Fetch the next byte of the message 1856 */ 1857 RECV_BYTE(regs, *tmpaddr); 1858 1859 /* 1860 * get the command completion interrupt, or we 1861 * can't send a new command (LCI) 1862 */ 1863 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1864 GET_SBIC_csr(regs, csr); 1865 1866 #ifdef DEBUG 1867 if ( reselect_debug > 1 ) 1868 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1869 #endif 1870 1871 tmpaddr++; 1872 1873 if ( recvlen ) { 1874 /* 1875 * Clear ACK, and wait for the interrupt for the next byte 1876 */ 1877 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1878 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1879 GET_SBIC_csr(regs, csr); 1880 } 1881 } 1882 1883 if ( msgaddr[0] == 0xff ) { 1884 printf("sbicmsgin: sbic swallowed our message\n"); 1885 break; 1886 } 1887 1888 #ifdef DEBUG 1889 if ( sync_debug ) { 1890 GET_SBIC_asr(regs, asr); 1891 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1892 } 1893 #endif 1894 /* 1895 * test whether this is a reply to our sync 1896 * request 1897 */ 1898 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1899 1900 /* 1901 * Got IFFY msg -- ack it 1902 */ 1903 QPRINTF(("IFFY")); 1904 1905 } else 1906 if ( msgaddr[0] == MSG_REJECT && 1907 dev->sc_sync[dev->target].state == SYNC_SENT) { 1908 1909 /* 1910 * Target probably rejected our Sync negotiation. 1911 */ 1912 QPRINTF(("REJECT of SYN")); 1913 1914 #ifdef DEBUG 1915 if ( sync_debug ) 1916 printf("target %d rejected sync, going async\n", dev->target); 1917 #endif 1918 1919 dev->sc_sync[dev->target].period = sbic_min_period; 1920 dev->sc_sync[dev->target].offset = 0; 1921 dev->sc_sync[dev->target].state = SYNC_DONE; 1922 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1923 dev->sc_sync[dev->target].period)); 1924 1925 } else 1926 if ( msgaddr[0] == MSG_REJECT ) { 1927 1928 /* 1929 * we'll never REJECt a REJECT message.. 1930 */ 1931 QPRINTF(("REJECT")); 1932 1933 } else 1934 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1935 1936 /* 1937 * don't reject this either. 1938 */ 1939 QPRINTF(("MSG_SAVE_DATA_PTR")); 1940 1941 } else 1942 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1943 1944 /* 1945 * don't reject this either. 1946 */ 1947 QPRINTF(("MSG_RESTORE_PTR")); 1948 1949 } else 1950 if ( msgaddr[0] == MSG_DISCONNECT ) { 1951 1952 /* 1953 * Target is disconnecting... 1954 */ 1955 QPRINTF(("DISCONNECT")); 1956 1957 #ifdef DEBUG 1958 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1959 printf("sbicmsgin: got disconnect msg %s\n", 1960 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1961 #endif 1962 1963 if ( dev->sc_flags & SBICF_ICMD ) { 1964 /* 1965 * We're in immediate mode. Prevent disconnects. 1966 * prepare to reject the message, NACK 1967 */ 1968 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1969 WAIT_CIP(regs); 1970 } 1971 1972 } else 1973 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1974 1975 /* 1976 * !! KLUDGE ALERT !! quite a few drives don't seem to 1977 * really like the current way of sending the 1978 * sync-handshake together with the ident-message, and 1979 * they react by sending command-complete and 1980 * disconnecting right after returning the valid sync 1981 * handshake. So, all I can do is reselect the drive, 1982 * and hope it won't disconnect again. I don't think 1983 * this is valid behavior, but I can't help fixing a 1984 * problem that apparently exists. 1985 * 1986 * Note: we should not get here on `normal' command 1987 * completion, as that condition is handled by the 1988 * high-level sel&xfer resume command used to walk 1989 * thru status/cc-phase. 1990 */ 1991 QPRINTF(("CMD_COMPLETE")); 1992 1993 #ifdef DEBUG 1994 if ( sync_debug ) 1995 printf ("GOT MSG %d! target %d acting weird.." 1996 " waiting for disconnect...\n", msgaddr[0], dev->target); 1997 #endif 1998 1999 /* 2000 * Check to see if sbic is handling this 2001 */ 2002 GET_SBIC_asr(regs, asr); 2003 2004 /* 2005 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 2006 */ 2007 if ( asr & SBIC_ASR_BSY ) 2008 return SBIC_STATE_RUNNING; 2009 2010 /* 2011 * Let's try this: Assume it works and set status to 00 2012 */ 2013 dev->sc_stat[0] = 0; 2014 2015 } else 2016 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 2017 2018 /* 2019 * Target is sending us an extended message. We'll assume it's 2020 * the response to our Sync. negotiation. 2021 */ 2022 QPRINTF(("ExtMSG\n")); 2023 2024 /* 2025 * Read in whole extended message. First, negate ACK to accept 2026 * the MSG_EXT_MESSAGE byte... 2027 */ 2028 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2029 2030 /* 2031 * Wait for the interrupt for the next byte (length) 2032 */ 2033 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2034 GET_SBIC_csr(regs, csr); 2035 2036 #ifdef DEBUG 2037 QPRINTF(("CLR ACK csr %02x\n", csr)); 2038 #endif 2039 2040 /* 2041 * Read the length byte 2042 */ 2043 RECV_BYTE(regs, *tmpaddr); 2044 2045 /* 2046 * Wait for command completion IRQ 2047 */ 2048 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2049 GET_SBIC_csr(regs, csr); 2050 2051 /* 2052 * Reload the loop counter 2053 */ 2054 recvlen = *tmpaddr++; 2055 2056 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2057 2058 } else 2059 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2060 msgaddr[2] == MSG_SYNC_REQ ) { 2061 2062 /* 2063 * We've received the complete Extended Message Sync. Request... 2064 */ 2065 QPRINTF(("SYN")); 2066 2067 /* 2068 * Compute the required Transfer Period for the WD chip... 2069 */ 2070 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2071 dev->sc_sync[dev->target].offset = msgaddr[4]; 2072 dev->sc_sync[dev->target].state = SYNC_DONE; 2073 2074 /* 2075 * Put the WD chip in synchronous mode 2076 */ 2077 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2078 dev->sc_sync[dev->target].period)); 2079 #ifdef DEBUG 2080 if ( sync_debug ) 2081 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2082 SBIC_SYN(dev->sc_sync[dev->target].offset, 2083 dev->sc_sync[dev->target].period)); 2084 #endif 2085 2086 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2087 dev->sc_dev.dv_xname, dev->target, 2088 msgaddr[3] * 4, msgaddr[4]); 2089 2090 } else { 2091 2092 /* 2093 * We don't support whatever this message is... 2094 */ 2095 #ifdef DEBUG 2096 if ( sbic_debug || sync_debug ) 2097 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2098 #endif 2099 2100 /* 2101 * prepare to reject the message, NACK 2102 */ 2103 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2104 WAIT_CIP(regs); 2105 } 2106 2107 /* 2108 * Negate ACK to complete the transfer 2109 */ 2110 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2111 2112 /* 2113 * Wait for the interrupt for the next byte, or phase change. 2114 * Only read the CSR if we have more data to transfer. 2115 * XXXSCW: We should really verify that we're still in MSG IN phase 2116 * before blindly going back around this loop, but that would mean 2117 * we read the CSR... <sigh> 2118 */ 2119 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2120 if ( recvlen > 0 ) 2121 GET_SBIC_csr(regs, csr); 2122 2123 } while ( recvlen > 0 ); 2124 2125 /* 2126 * Should still have one CSR to read 2127 */ 2128 return SBIC_STATE_RUNNING; 2129 } 2130 2131 2132 /* 2133 * sbicnextstate() 2134 * return: 2135 * SBIC_STATE_DONE == done 2136 * SBIC_STATE_RUNNING == working 2137 * SBIC_STATE_DISCONNECT == disconnected 2138 * SBIC_STATE_ERROR == error 2139 */ 2140 int 2141 sbicnextstate(dev, csr, asr) 2142 struct sbic_softc *dev; 2143 u_char csr, 2144 asr; 2145 { 2146 sbic_regmap_p regs = dev->sc_sbicp; 2147 struct sbic_acb *acb = dev->sc_nexus; 2148 2149 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2150 2151 switch (csr) { 2152 2153 case SBIC_CSR_XFERRED | CMD_PHASE: 2154 case SBIC_CSR_MIS | CMD_PHASE: 2155 case SBIC_CSR_MIS_1 | CMD_PHASE: 2156 case SBIC_CSR_MIS_2 | CMD_PHASE: 2157 { 2158 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2159 goto abort; 2160 } 2161 break; 2162 2163 case SBIC_CSR_XFERRED | STATUS_PHASE: 2164 case SBIC_CSR_MIS | STATUS_PHASE: 2165 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2166 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2167 { 2168 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2169 2170 /* 2171 * this should be the normal i/o completion case. 2172 * get the status & cmd complete msg then let the 2173 * device driver look at what happened. 2174 */ 2175 sbicxfdone(dev); 2176 2177 #ifdef DEBUG 2178 dev->sc_dmatimo = 0; 2179 if ( data_pointer_debug > 1 ) 2180 printf("next dmastop: %d(%x:%x)\n", dev->target, 2181 dev->sc_cur->dc_addr, 2182 dev->sc_tcnt); 2183 #endif 2184 /* 2185 * Stop the DMA chip 2186 */ 2187 dev->sc_dmastop(dev); 2188 2189 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2190 2191 /* 2192 * Indicate to the upper layers that the command is done 2193 */ 2194 sbic_scsidone(acb, dev->sc_stat[0]); 2195 2196 return SBIC_STATE_DONE; 2197 } 2198 2199 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2200 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2201 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2202 case SBIC_CSR_MIS | DATA_IN_PHASE: 2203 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2204 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2205 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2206 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2207 { 2208 /* 2209 * Verify that we expected to transfer data... 2210 */ 2211 if ( acb->sc_kv.dc_count <= 0 ) { 2212 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2213 acb->sc_kv.dc_count, asr, csr); 2214 goto abort; 2215 } 2216 2217 /* 2218 * Should we transfer using PIO or DMA ? 2219 */ 2220 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2221 acb->sc_dmacmd == 0 ) { 2222 2223 /* 2224 * Do PIO transfer 2225 */ 2226 int i; 2227 2228 #ifdef DEBUG 2229 if ( data_pointer_debug > 1 ) 2230 printf("next PIO: %d(%x:%x)\n", dev->target, 2231 acb->sc_kv.dc_addr, 2232 acb->sc_kv.dc_count); 2233 #endif 2234 2235 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2236 /* 2237 * data in 2238 */ 2239 i = sbicxfin(regs, acb->sc_kv.dc_count, 2240 acb->sc_kv.dc_addr); 2241 else 2242 /* 2243 * data out 2244 */ 2245 i = sbicxfout(regs, acb->sc_kv.dc_count, 2246 acb->sc_kv.dc_addr); 2247 2248 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2249 acb->sc_kv.dc_count = i; 2250 2251 /* 2252 * Update current count... 2253 */ 2254 acb->sc_tcnt = dev->sc_tcnt = i; 2255 2256 dev->sc_flags &= ~SBICF_INDMA; 2257 2258 } else { 2259 2260 /* 2261 * Do DMA transfer 2262 * set next dma addr and dec count 2263 */ 2264 sbic_save_ptrs(dev); 2265 sbic_load_ptrs(dev); 2266 2267 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2268 SBIC_MACHINE_DMA_MODE); 2269 2270 #ifdef DEBUG 2271 dev->sc_dmatimo = 1; 2272 if ( data_pointer_debug > 1 ) 2273 printf("next DMA: %d(%x:%x)\n", dev->target, 2274 dev->sc_cur->dc_addr, 2275 dev->sc_tcnt); 2276 #endif 2277 /* 2278 * Start the DMA chip going 2279 */ 2280 dev->sc_tcnt = dev->sc_dmanext(dev); 2281 2282 /* 2283 * Tell the WD chip how much to transfer this time around 2284 */ 2285 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2286 2287 /* 2288 * Start the transfer 2289 */ 2290 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2291 2292 /* 2293 * Indicate that we're in DMA mode 2294 */ 2295 dev->sc_flags |= SBICF_INDMA; 2296 } 2297 } 2298 break; 2299 2300 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2301 case SBIC_CSR_MIS | MESG_IN_PHASE: 2302 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2303 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2304 { 2305 sbic_save_ptrs(dev); 2306 2307 /* 2308 * Handle a single message in... 2309 */ 2310 return sbicmsgin(dev); 2311 } 2312 2313 case SBIC_CSR_MSGIN_W_ACK: 2314 { 2315 /* 2316 * We should never see this since it's handled in 'sbicmsgin()' 2317 * but just for the sake of paranoia... 2318 */ 2319 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2320 printf("Acking unknown msgin CSR:%02x",csr); 2321 } 2322 break; 2323 2324 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2325 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2326 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2327 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2328 { 2329 /* 2330 * We only ever handle a message out phase here for sending a 2331 * REJECT message. 2332 */ 2333 sbic_save_ptrs(dev); 2334 2335 #ifdef DEBUG 2336 if (sync_debug) 2337 printf ("sending REJECT msg to last msg.\n"); 2338 #endif 2339 2340 SEND_BYTE(regs, MSG_REJECT); 2341 WAIT_CIP(regs); 2342 } 2343 break; 2344 2345 case SBIC_CSR_DISC: 2346 case SBIC_CSR_DISC_1: 2347 { 2348 /* 2349 * Try to schedule another target 2350 */ 2351 sbic_save_ptrs(dev); 2352 2353 dev->sc_flags &= ~SBICF_SELECTED; 2354 2355 #ifdef DEBUG 2356 if ( reselect_debug > 1 ) 2357 printf("sbicnext target %d disconnected\n", dev->target); 2358 #endif 2359 2360 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2361 2362 ++dev->sc_tinfo[dev->target].dconns; 2363 2364 dev->sc_nexus = NULL; 2365 dev->sc_xs = NULL; 2366 2367 if ( acb->xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2368 !sbic_parallel_operations ) 2369 return SBIC_STATE_DISCONNECT; 2370 2371 QPRINTF(("sbicnext: calling sbic_sched\n")); 2372 2373 sbic_sched(dev); 2374 2375 QPRINTF(("sbicnext: sbic_sched returned\n")); 2376 2377 return SBIC_STATE_DISCONNECT; 2378 } 2379 2380 case SBIC_CSR_RSLT_NI: 2381 case SBIC_CSR_RSLT_IFY: 2382 { 2383 /* 2384 * A reselection. 2385 * Note that since we don't enable Advanced Features (assuming 2386 * the WD chip is at least the 'A' revision), we're only ever 2387 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2388 * hell of it, we'll handle it anyway, for all the extra code 2389 * it needs... 2390 */ 2391 u_char newtarget, 2392 newlun; 2393 2394 GET_SBIC_rselid(regs, newtarget); 2395 2396 /* 2397 * check SBIC_RID_SIV? 2398 */ 2399 newtarget &= SBIC_RID_MASK; 2400 2401 if ( csr == SBIC_CSR_RSLT_IFY ) { 2402 2403 /* 2404 * Read Identify msg to avoid lockup 2405 */ 2406 GET_SBIC_data(regs, newlun); 2407 WAIT_CIP(regs); 2408 newlun &= SBIC_TLUN_MASK; 2409 2410 } else { 2411 2412 /* 2413 * Need to read Identify message the hard way, assuming 2414 * the target even sends us one... 2415 */ 2416 for (newlun = 255; newlun; --newlun) { 2417 GET_SBIC_asr(regs, asr); 2418 if (asr & SBIC_ASR_INT) 2419 break; 2420 delay(10); 2421 } 2422 2423 /* 2424 * If we didn't get an interrupt, somethink's up 2425 */ 2426 if ( (asr & SBIC_ASR_INT) == 0 ) { 2427 printf("%s: Reselect without identify? asr %x\n", 2428 dev->sc_dev.dv_xname, asr); 2429 newlun = 0; /* XXXX */ 2430 } else { 2431 /* 2432 * We got an interrupt, verify that it's a change to 2433 * message in phase, and if so read the message. 2434 */ 2435 GET_SBIC_csr(regs,csr); 2436 2437 if ( csr == SBIC_CSR_MIS | MESG_IN_PHASE || 2438 csr == SBIC_CSR_MIS_1 | MESG_IN_PHASE || 2439 csr == SBIC_CSR_MIS_2 | MESG_IN_PHASE ) { 2440 /* 2441 * Yup, gone to message in. Fetch the target LUN 2442 */ 2443 sbicmsgin(dev); 2444 newlun = dev->sc_msg[0] & 0x07; 2445 2446 } else { 2447 /* 2448 * Whoops! Target didn't go to message in phase!! 2449 */ 2450 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2451 newlun = 0; /* XXXSCW */ 2452 } 2453 } 2454 } 2455 2456 /* 2457 * Ok, we have the identity of the reselecting target. 2458 */ 2459 #ifdef DEBUG 2460 if ( reselect_debug > 1 || 2461 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2462 printf("sbicnext: reselect %s from targ %d lun %d\n", 2463 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2464 } 2465 #endif 2466 2467 if ( dev->sc_nexus ) { 2468 /* 2469 * Whoops! We've been reselected with an command in progress! 2470 * The best we can do is to put the current command back on the 2471 * ready list and hope for the best. 2472 */ 2473 #ifdef DEBUG 2474 if ( reselect_debug > 1 ) { 2475 printf("%s: reselect %s with active command\n", 2476 dev->sc_dev.dv_xname, 2477 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2478 } 2479 #endif 2480 2481 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2482 2483 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2484 2485 dev->sc_nexus = NULL; 2486 dev->sc_xs = NULL; 2487 } 2488 2489 /* 2490 * Reload sync values for this target 2491 */ 2492 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2493 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2494 dev->sc_sync[newtarget].period)); 2495 else 2496 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2497 2498 /* 2499 * Loop through the nexus list until we find the saved entry 2500 * for the reselecting target... 2501 */ 2502 for (acb = dev->nexus_list.tqh_first; acb; 2503 acb = acb->chain.tqe_next) { 2504 2505 if ( acb->xs->sc_link->target == newtarget && 2506 acb->xs->sc_link->lun == newlun) { 2507 /* 2508 * We've found the saved entry. Dequeue it, and 2509 * make it current again. 2510 */ 2511 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2512 2513 dev->sc_nexus = acb; 2514 dev->sc_xs = acb->xs; 2515 dev->sc_flags |= SBICF_SELECTED; 2516 dev->target = newtarget; 2517 dev->lun = newlun; 2518 break; 2519 } 2520 } 2521 2522 if ( acb == NULL ) { 2523 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2524 dev->sc_dev.dv_xname, 2525 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2526 &dev->nexus_list.tqh_first); 2527 panic("bad reselect in sbic"); 2528 } 2529 2530 if ( csr == SBIC_CSR_RSLT_IFY ) 2531 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2532 } 2533 break; 2534 2535 default: 2536 abort: 2537 { 2538 /* 2539 * Something unexpected happened -- deal with it. 2540 */ 2541 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2542 2543 #ifdef DDB 2544 Debugger(); 2545 #endif 2546 2547 #ifdef DEBUG 2548 dev->sc_dmatimo = 0; 2549 if ( data_pointer_debug > 1 ) 2550 printf("next dmastop: %d(%x:%x)\n", dev->target, 2551 dev->sc_cur->dc_addr, 2552 dev->sc_tcnt); 2553 #endif 2554 2555 dev->sc_dmastop(dev); 2556 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2557 if ( dev->sc_xs ) sbicerror(dev, csr); 2558 sbicabort(dev, "next"); 2559 2560 if ( dev->sc_flags & SBICF_INDMA ) { 2561 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2562 2563 #ifdef DEBUG 2564 dev->sc_dmatimo = 0; 2565 if ( data_pointer_debug > 1 ) 2566 printf("next dmastop: %d(%x:%x)\n", dev->target, 2567 dev->sc_cur->dc_addr, 2568 dev->sc_tcnt); 2569 #endif 2570 sbic_scsidone(acb, -1); 2571 } 2572 2573 return SBIC_STATE_ERROR; 2574 } 2575 } 2576 2577 return(SBIC_STATE_RUNNING); 2578 } 2579 2580 2581 /* 2582 * Check if DMA can not be used with specified buffer 2583 */ 2584 int 2585 sbiccheckdmap(bp, len, mask) 2586 void *bp; 2587 u_long len, 2588 mask; 2589 { 2590 u_char *buffer; 2591 u_long phy_buf; 2592 u_long phy_len; 2593 2594 buffer = bp; 2595 2596 if ( len == 0 ) 2597 return(1); 2598 2599 while ( len ) { 2600 2601 phy_buf = kvtop(buffer); 2602 phy_len = NBPG - ((int) buffer & PGOFSET); 2603 2604 if ( len < phy_len ) 2605 phy_len = len; 2606 2607 if ( phy_buf & mask ) 2608 return(1); 2609 2610 buffer += phy_len; 2611 len -= phy_len; 2612 } 2613 2614 return(0); 2615 } 2616 2617 int 2618 sbictoscsiperiod(dev, a) 2619 struct sbic_softc *dev; 2620 int a; 2621 { 2622 unsigned int fs; 2623 2624 /* 2625 * cycle = DIV / (2 * CLK) 2626 * DIV = FS + 2 2627 * best we can do is 200ns at 20Mhz, 2 cycles 2628 */ 2629 2630 GET_SBIC_myid(dev->sc_sbicp, fs); 2631 2632 fs = (fs >> 6) + 2; /* DIV */ 2633 2634 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2635 2636 if ( a < 2 ) 2637 a = 8; /* map to Cycles */ 2638 2639 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2640 } 2641 2642 int 2643 sbicfromscsiperiod(dev, p) 2644 struct sbic_softc *dev; 2645 int p; 2646 { 2647 unsigned fs, 2648 ret; 2649 2650 /* 2651 * Just the inverse of the above 2652 */ 2653 GET_SBIC_myid(dev->sc_sbicp, fs); 2654 2655 fs = (fs >> 6) + 2; /* DIV */ 2656 2657 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2658 2659 ret = p << 2; /* in ns units */ 2660 ret = ret / fs; /* in Cycles */ 2661 2662 if ( ret < sbic_min_period ) 2663 return(sbic_min_period); 2664 2665 /* 2666 * verify rounding 2667 */ 2668 if ( sbictoscsiperiod(dev, ret) < p ) 2669 ret++; 2670 2671 return( (ret >= 8) ? 0 : ret ); 2672 } 2673 2674 #ifdef DEBUG 2675 void 2676 sbictimeout(dev) 2677 struct sbic_softc *dev; 2678 { 2679 int s, 2680 asr; 2681 2682 s = splbio(); 2683 2684 if ( dev->sc_dmatimo ) { 2685 2686 if ( dev->sc_dmatimo > 1 ) { 2687 2688 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2689 dev->sc_dmatimo - 1); 2690 2691 GET_SBIC_asr(dev->sc_sbicp, asr); 2692 2693 if ( asr & SBIC_ASR_INT ) { 2694 /* 2695 * We need to service a missed IRQ 2696 */ 2697 sbicintr(dev); 2698 } else { 2699 (void) sbicabort(dev, "timeout"); 2700 splx(s); 2701 return; 2702 } 2703 } 2704 2705 dev->sc_dmatimo++; 2706 } 2707 2708 splx(s); 2709 2710 timeout((void *)sbictimeout, dev, 30 * hz); 2711 } 2712 #endif 2713
Indexes created Mon Sep 29 13:09:55 GMT 2025