sbic.c revision 1.6
1 /* $NetBSD: sbic.c,v 1.6 1997/08/27 11:23:57 bouyer Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/kernel.h> /* For hz */ 60 #include <sys/disklabel.h> 61 #include <sys/dkstat.h> 62 #include <sys/buf.h> 63 #include <dev/scsipi/scsi_all.h> 64 #include <dev/scsipi/scsipi_all.h> 65 #include <dev/scsipi/scsiconf.h> 66 #include <vm/vm.h> 67 #include <vm/vm_kern.h> 68 #include <vm/vm_page.h> 69 #include <vm/pmap.h> 70 #include <machine/pmap.h> 71 #include <mvme68k/mvme68k/isr.h> 72 #include <mvme68k/dev/dmavar.h> 73 #include <mvme68k/dev/sbicreg.h> 74 #include <mvme68k/dev/sbicvar.h> 75 76 77 /* 78 * Since I can't find this in any other header files 79 */ 80 #define SCSI_PHASE(reg) (reg&0x07) 81 82 /* 83 * SCSI delays 84 * In u-seconds, primarily for state changes on the SPC. 85 */ 86 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 87 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 88 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 89 90 /* 91 * Convenience macro for waiting for a particular sbic event 92 */ 93 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 94 95 extern u_int kvtop(); 96 97 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 98 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 99 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 100 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 101 int sbiccheckdmap __P((void *, u_long, u_long)); 102 u_char sbicselectbus __P((struct sbic_softc *)); 103 int sbicxfout __P((sbic_regmap_p, int, void *)); 104 int sbicxfin __P((sbic_regmap_p, int, void *)); 105 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 106 int sbictoscsiperiod __P((struct sbic_softc *, int)); 107 int sbicintr __P((struct sbic_softc *)); 108 int sbicpoll __P((struct sbic_softc *)); 109 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 110 int sbicmsgin __P((struct sbic_softc *)); 111 int sbicabort __P((struct sbic_softc *, char *)); 112 void sbicxfdone __P((struct sbic_softc *)); 113 void sbicerror __P((struct sbic_softc *,u_char)); 114 void sbicreset __P((struct sbic_softc *)); 115 void sbic_scsidone __P((struct sbic_acb *, int)); 116 void sbic_sched __P((struct sbic_softc *)); 117 void sbic_save_ptrs __P((struct sbic_softc *)); 118 void sbic_load_ptrs __P((struct sbic_softc *)); 119 120 /* 121 * Synch xfer parameters, and timing conversions 122 */ 123 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 124 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 125 int sbic_cmd_wait = SBIC_CMD_WAIT; 126 int sbic_data_wait = SBIC_DATA_WAIT; 127 int sbic_init_wait = SBIC_INIT_WAIT; 128 129 /* 130 * was broken before.. now if you want this you get it for all drives 131 * on sbic controllers. 132 */ 133 u_char sbic_inhibit_sync[8]; 134 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 135 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 136 int sbic_parallel_operations = 1; /* Allow command queues */ 137 138 /* 139 * Some useful stuff for debugging purposes 140 */ 141 #ifdef DEBUG 142 int sbicdma_ops = 0; /* total DMA operations */ 143 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 144 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 145 int sbicdma_saves = 0; 146 147 #define QPRINTF(a) if (sbic_debug > 1) printf a 148 149 int sbic_debug = 0; /* Debug all chip related things */ 150 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 151 int reselect_debug = 0; /* Debug all reselection related things */ 152 int report_sense = 0; /* Always print Sense information */ 153 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 154 155 void sbictimeout __P((struct sbic_softc *dev)); 156 157 #else 158 #define QPRINTF(a) /* */ 159 #endif 160 161 162 /* 163 * default minphys routine for sbic based controllers 164 */ 165 void 166 sbic_minphys(bp) 167 struct buf *bp; 168 { 169 /* 170 * No max transfer at this level. 171 */ 172 minphys(bp); 173 } 174 175 176 /* 177 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 178 */ 179 void 180 sbic_save_ptrs(dev) 181 struct sbic_softc *dev; 182 { 183 sbic_regmap_p regs; 184 struct sbic_acb* acb; 185 int count, 186 asr, 187 s; 188 189 /* 190 * Only need to save pointers if DMA was active... 191 */ 192 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 193 return; 194 195 regs = dev->sc_sbicp; 196 197 s = splbio(); 198 199 /* 200 * Wait until WD chip is idle 201 */ 202 do { 203 GET_SBIC_asr(regs, asr); 204 if( asr & SBIC_ASR_DBR ) { 205 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 206 splx(s); 207 return; 208 } 209 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 210 211 212 /* 213 * Save important state. 214 * must be done before dmastop 215 */ 216 acb = dev->sc_nexus; 217 acb->sc_dmacmd = dev->sc_dmacmd; 218 219 /* 220 * Fetch the residual count 221 */ 222 SBIC_TC_GET(regs, count); 223 224 /* 225 * Shut down DMA 226 */ 227 dev->sc_dmastop(dev); 228 229 /* 230 * No longer in DMA 231 */ 232 dev->sc_flags &= ~SBICF_INDMA; 233 234 /* 235 * Ensure the WD chip is back in polled I/O mode, with nothing to 236 * transfer. 237 */ 238 SBIC_TC_PUT(regs, 0); 239 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 240 241 /* 242 * Update current count... 243 */ 244 acb->sc_tcnt = count; 245 246 /* 247 * Work out how many bytes were actually transferred 248 */ 249 count = dev->sc_tcnt - count; 250 dev->sc_tcnt = acb->sc_tcnt; 251 252 /* 253 * Fixup partial xfers 254 */ 255 acb->sc_kv.dc_addr += count; 256 acb->sc_kv.dc_count -= count; 257 acb->sc_pa.dc_addr += count; 258 acb->sc_pa.dc_count -= count >> 1; 259 260 #ifdef DEBUG 261 if ( data_pointer_debug ) 262 printf("save at (%x,%x):%x\n", 263 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 264 sbicdma_saves++; 265 #endif 266 267 splx(s); 268 } 269 270 271 /* 272 * DOES NOT RESTART DMA!!! 273 */ 274 void 275 sbic_load_ptrs(dev) 276 struct sbic_softc *dev; 277 { 278 struct sbic_acb *acb = dev->sc_nexus; 279 int s; 280 281 if ( acb->sc_kv.dc_count == 0 ) { 282 /* 283 * No data to xfer 284 */ 285 return; 286 } 287 288 s = splbio(); 289 290 /* 291 * Reset the Scatter-Gather chain 292 */ 293 dev->sc_last = dev->sc_cur = &acb->sc_pa; 294 295 /* 296 * Restore the Transfer Count and DMA specific data 297 */ 298 dev->sc_tcnt = acb->sc_tcnt; 299 dev->sc_dmacmd = acb->sc_dmacmd; 300 301 #ifdef DEBUG 302 sbicdma_ops++; 303 #endif 304 305 /* 306 * Need to fixup new segment? 307 */ 308 if ( dev->sc_tcnt == 0 ) { 309 /* 310 * sc_tcnt == 0 implies end of segment 311 */ 312 char *vaddr, *paddr; 313 int count; 314 315 /* 316 * do kvm to pa mappings 317 */ 318 vaddr = acb->sc_kv.dc_addr; 319 paddr = acb->sc_pa.dc_addr = (char *) kvtop(vaddr); 320 321 for (count = (NBPG - ((int)vaddr & PGOFSET)); 322 count < acb->sc_kv.dc_count && 323 (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 324 count += NBPG) 325 ; /* Do nothing */ 326 327 /* 328 * If it's all contiguous... 329 */ 330 if ( count > acb->sc_kv.dc_count ) { 331 count = acb->sc_kv.dc_count; 332 #ifdef DEBUG 333 sbicdma_hits++; 334 #endif 335 } 336 #ifdef DEBUG 337 else 338 sbicdma_misses++; 339 #endif 340 341 acb->sc_tcnt = count; 342 acb->sc_pa.dc_count = count >> 1; 343 344 #ifdef DEBUG 345 if ( data_pointer_debug ) 346 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", acb->sc_kv.dc_addr, 347 acb->sc_kv.dc_count, 348 acb->sc_pa.dc_addr, 349 acb->sc_tcnt); 350 #endif 351 352 } 353 354 splx(s); 355 } 356 357 /* 358 * used by specific sbic controller 359 * 360 * it appears that the higher level code does nothing with LUN's 361 * so I will too. I could plug it in, however so could they 362 * in scsi_scsipi_cmd(). 363 */ 364 int 365 sbic_scsicmd(xs) 366 struct scsipi_xfer *xs; 367 { 368 struct scsipi_link *slp = xs->sc_link; 369 struct sbic_softc *dev = slp->adapter_softc; 370 struct sbic_acb *acb; 371 int flags = xs->flags, 372 s; 373 374 if ( flags & SCSI_DATA_UIO ) 375 panic("sbic: scsi data uio requested"); 376 377 if ( dev->sc_nexus && (flags & SCSI_POLL) ) 378 panic("sbic_scsicmd: busy"); 379 380 if ( slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target ) 381 return ESCAPE_NOT_SUPPORTED; 382 383 s = splbio(); 384 385 if ( (acb = dev->free_list.tqh_first) != NULL ) 386 TAILQ_REMOVE(&dev->free_list, acb, chain); 387 388 splx(s); 389 390 if ( acb == NULL ) { 391 #ifdef DEBUG 392 printf("sbic_scsicmd: unable to queue request for target %d\n", 393 slp->scsipi_scsi.target); 394 #ifdef DDB 395 Debugger(); 396 #endif 397 #endif 398 xs->error = XS_DRIVER_STUFFUP; 399 400 return(TRY_AGAIN_LATER); 401 } 402 403 if ( flags & SCSI_DATA_IN ) 404 acb->flags = ACB_ACTIVE | ACB_DATAIN; 405 else 406 acb->flags = ACB_ACTIVE; 407 408 acb->xs = xs; 409 acb->clen = xs->cmdlen; 410 acb->sc_kv.dc_addr = xs->data; 411 acb->sc_kv.dc_count = xs->datalen; 412 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; 413 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 414 415 if ( flags & SCSI_POLL ) { 416 /* 417 * This has major side effects -- it locks up the machine 418 */ 419 int stat; 420 421 s = splbio(); 422 423 dev->sc_flags |= SBICF_ICMD; 424 425 do { 426 /* 427 * If we already had a nexus, while away the time until idle... 428 * This is likely only to happen if a reselection occurs between 429 * here and our earlier check for ICMD && sc_nexus (which would 430 * have resulted in a panic() had it been true). 431 */ 432 while ( dev->sc_nexus ) 433 sbicpoll(dev); 434 435 /* 436 * Fix up the new nexus 437 */ 438 dev->sc_nexus = acb; 439 dev->sc_xs = xs; 440 dev->target = slp->scsipi_scsi.target; 441 dev->lun = slp->scsipi_scsi.lun; 442 443 stat = sbicicmd(dev, &acb->cmd, acb->clen, 444 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 445 446 } while ( dev->sc_nexus != acb ); 447 448 sbic_scsidone(acb, stat); 449 450 splx(s); 451 452 return(COMPLETE); 453 } 454 455 s = splbio(); 456 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 457 458 /* 459 * If nothing is active, try to start it now. 460 */ 461 if ( dev->sc_nexus == NULL ) 462 sbic_sched(dev); 463 464 splx(s); 465 466 return(SUCCESSFULLY_QUEUED); 467 } 468 469 /* 470 * attempt to start the next available command 471 */ 472 void 473 sbic_sched(dev) 474 struct sbic_softc *dev; 475 { 476 struct scsipi_xfer *xs; 477 struct scsipi_link *slp = NULL; /* Gag the compiler */ 478 struct sbic_acb *acb; 479 int flags, 480 stat; 481 482 /* 483 * XXXSCW 484 * I'll keep this test here, even though I can't see any obvious way 485 * in which sbic_sched() could be called with sc_nexus non NULL 486 */ 487 if ( dev->sc_nexus ) 488 return; /* a command is current active */ 489 490 /* 491 * Loop through the ready list looking for work to do... 492 */ 493 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 494 int i, j; 495 496 slp = acb->xs->sc_link; 497 i = slp->scsipi_scsi.target; 498 j = 1 << slp->scsipi_scsi.lun; 499 500 /* 501 * We've found a potential command, but is the target/lun busy? 502 */ 503 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 504 /* 505 * Nope, it's not busy, so we can use it. 506 */ 507 dev->sc_tinfo[i].lubusy |= j; 508 TAILQ_REMOVE(&dev->ready_list, acb, chain); 509 dev->sc_nexus = acb; 510 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 511 break; 512 } 513 } 514 515 if ( acb == NULL ) { 516 QPRINTF(("sbicsched: no work\n")); 517 return; /* did not find an available command */ 518 } 519 520 #ifdef DEBUG 521 if ( data_pointer_debug > 1 ) 522 printf("sbic_sched(%d,%d)\n", slp->scsipi_scsi.target, 523 slp->scsipi_scsi.lun); 524 #endif 525 526 dev->sc_xs = xs = acb->xs; 527 flags = xs->flags; 528 529 if ( flags & SCSI_RESET ) 530 sbicreset(dev); 531 532 dev->sc_stat[0] = -1; 533 dev->target = slp->scsipi_scsi.target; 534 dev->lun = slp->scsipi_scsi.lun; 535 536 if ( flags & SCSI_POLL || (!sbic_parallel_operations && 537 (sbicdmaok(dev, xs) == 0)) ) 538 stat = sbicicmd(dev, &acb->cmd, acb->clen, 539 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 540 else 541 if ( sbicgo(dev, xs) == 0 ) 542 return; 543 else 544 stat = dev->sc_stat[0]; 545 546 sbic_scsidone(acb, stat); 547 } 548 549 void 550 sbic_scsidone(acb, stat) 551 struct sbic_acb *acb; 552 int stat; 553 { 554 struct scsipi_xfer *xs = acb->xs; 555 struct scsipi_link *slp = xs->sc_link; 556 struct sbic_softc *dev = slp->adapter_softc; 557 int dosched = 0; 558 559 #ifdef DIAGNOSTIC 560 if ( acb == NULL || xs == NULL ) { 561 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); 562 #ifdef DDB 563 Debugger(); 564 #endif 565 return; 566 } 567 #endif 568 569 /* 570 * is this right? 571 */ 572 xs->status = stat; 573 574 #ifdef DEBUG 575 if ( data_pointer_debug > 1 ) 576 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", slp->scsipi_scsi.target, 577 slp->scsipi_scsi.lun, 578 dev->target, dev->lun, stat); 579 580 if ( xs->sc_link->scsipi_scsi.target == 581 dev->sc_link.scsipi_scsi.adapter_target ) 582 panic("target == hostid"); 583 #endif 584 585 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) == 0 ) { 586 587 if ( stat == SCSI_CHECK ) { 588 /* 589 * Schedule a REQUEST SENSE 590 */ 591 struct scsipi_sense *ss = (void *)&acb->cmd; 592 593 #ifdef DEBUG 594 if ( report_sense ) 595 printf("sbic_scsidone: autosense %02x targ %d lun %d", 596 acb->cmd.opcode, slp->scsipi_scsi.target, 597 slp->scsipi_scsi.lun); 598 #endif 599 600 bzero(ss, sizeof(*ss)); 601 602 ss->opcode = REQUEST_SENSE; 603 ss->byte2 = slp->scsipi_scsi.lun << 5; 604 ss->length = sizeof(struct scsipi_sense_data); 605 606 acb->clen = sizeof(*ss); 607 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 608 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 609 acb->pa_addr = (char *)kvtop(&xs->sense.scsi_sense); /* XXX check */ 610 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 611 612 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 613 614 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 615 ~(1 << slp->scsipi_scsi.lun); 616 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 617 618 if ( dev->sc_nexus == acb ) { 619 dev->sc_nexus = NULL; 620 dev->sc_xs = NULL; 621 sbic_sched(dev); 622 } 623 return; 624 } 625 } 626 627 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) != 0 ) { 628 629 xs->error = XS_SENSE; 630 631 #ifdef DEBUG 632 if (report_sense) 633 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 634 xs->sense.scsi_sense.extra_bytes[3]); 635 #endif 636 637 } else { 638 xs->resid = 0; /* XXXX */ 639 } 640 641 xs->flags |= ITSDONE; 642 643 /* 644 * Remove the ACB from whatever queue it's on. We have to do a bit of 645 * a hack to figure out which queue it's on. Note that it is *not* 646 * necessary to cdr down the ready queue, but we must cdr down the 647 * nexus queue and see if it's there, so we can mark the unit as no 648 * longer busy. This code is sickening, but it works. 649 */ 650 if ( acb == dev->sc_nexus ) { 651 652 dev->sc_nexus = NULL; 653 dev->sc_xs = NULL; 654 655 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 656 ~(1 << slp->scsipi_scsi.lun); 657 658 if ( dev->ready_list.tqh_first ) 659 dosched = 1; /* start next command */ 660 661 } else 662 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 663 664 TAILQ_REMOVE(&dev->ready_list, acb, chain); 665 666 } else { 667 668 register struct sbic_acb *a; 669 670 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 671 if ( a == acb ) { 672 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 673 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 674 ~(1 << slp->scsipi_scsi.lun); 675 break; 676 } 677 } 678 679 if ( a ) 680 ; 681 else if ( acb->chain.tqe_next ) { 682 TAILQ_REMOVE(&dev->ready_list, acb, chain); 683 } else { 684 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 685 #ifdef DDB 686 Debugger(); 687 #endif 688 } 689 } 690 691 /* 692 * Put it on the free list. 693 */ 694 acb->flags = ACB_FREE; 695 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 696 697 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 698 699 scsipi_done(xs); 700 701 if ( dosched ) 702 sbic_sched(dev); 703 } 704 705 int 706 sbicdmaok(dev, xs) 707 struct sbic_softc *dev; 708 struct scsipi_xfer *xs; 709 { 710 if ( sbic_no_dma || xs->datalen & 0x03 || (int)xs->data & 0x03) 711 return(0); 712 713 /* 714 * controller supports dma to any addresses? 715 */ 716 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 717 return(1); 718 719 /* 720 * this address is ok for dma? 721 */ 722 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 723 return(1); 724 725 return(0); 726 } 727 728 int 729 sbicwait(regs, until, timeo, line) 730 sbic_regmap_p regs; 731 u_char until; 732 int timeo; 733 int line; 734 { 735 u_char val; 736 737 if ( timeo == 0 ) 738 timeo = 1000000; /* some large value.. */ 739 740 GET_SBIC_asr(regs, val); 741 742 while ( (val & until) == 0 ) { 743 744 if ( timeo-- == 0 ) { 745 int csr; 746 GET_SBIC_csr(regs, csr); 747 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 748 #if defined(DDB) && defined(DEBUG) 749 Debugger(); 750 #endif 751 return(val); /* Maybe I should abort */ 752 break; 753 } 754 755 DELAY(1); 756 GET_SBIC_asr(regs, val); 757 } 758 759 return(val); 760 } 761 762 int 763 sbicabort(dev, where) 764 struct sbic_softc *dev; 765 char *where; 766 { 767 sbic_regmap_p regs = dev->sc_sbicp; 768 u_char csr, 769 asr; 770 771 GET_SBIC_asr(regs, asr); 772 GET_SBIC_csr(regs, csr); 773 774 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 775 dev->sc_dev.dv_xname, where, csr, asr); 776 777 /* 778 * Clean up chip itself 779 */ 780 if ( dev->sc_flags & SBICF_SELECTED ) { 781 782 while ( asr & SBIC_ASR_DBR ) { 783 /* 784 * sbic is jammed w/data. need to clear it 785 * But we don't know what direction it needs to go 786 */ 787 GET_SBIC_data(regs, asr); 788 printf("%s: abort %s: clearing data buffer 0x%02x\n", 789 dev->sc_dev.dv_xname, where, asr); 790 GET_SBIC_asr(regs, asr); 791 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 792 SET_SBIC_data(regs, asr); 793 GET_SBIC_asr(regs, asr); 794 } 795 796 WAIT_CIP(regs); 797 798 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 799 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 800 WAIT_CIP(regs); 801 802 GET_SBIC_asr(regs, asr); 803 804 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 805 /* 806 * ok, get more drastic.. 807 */ 808 printf("%s: sbicabort - asr %x, trying to reset\n", 809 dev->sc_dev.dv_xname, asr); 810 sbicreset(dev); 811 dev->sc_flags &= ~SBICF_SELECTED; 812 return SBIC_STATE_ERROR; 813 } 814 815 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 816 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 817 818 do { 819 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 820 GET_SBIC_asr(regs, asr); 821 GET_SBIC_csr (regs, csr); 822 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 823 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 824 (csr != SBIC_CSR_CMD_INVALID) ); 825 826 /* 827 * lets just hope it worked.. 828 */ 829 dev->sc_flags &= ~SBICF_SELECTED; 830 } 831 832 return SBIC_STATE_ERROR; 833 } 834 835 836 /* 837 * Initialize driver-private structures 838 */ 839 void 840 sbicinit(dev) 841 struct sbic_softc *dev; 842 { 843 u_int i; 844 845 extern u_long scsi_nosync; 846 extern int shift_nosync; 847 848 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 849 850 struct sbic_acb *acb; 851 852 TAILQ_INIT(&dev->ready_list); 853 TAILQ_INIT(&dev->nexus_list); 854 TAILQ_INIT(&dev->free_list); 855 856 dev->sc_nexus = NULL; 857 dev->sc_xs = NULL; 858 859 acb = dev->sc_acb; 860 bzero(acb, sizeof(dev->sc_acb)); 861 862 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 863 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 864 acb++; 865 } 866 867 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 868 869 #ifdef DEBUG 870 /* 871 * make sure timeout is really not needed 872 */ 873 timeout((void *)sbictimeout, dev, 30 * hz); 874 #endif 875 876 } else 877 panic("sbic: reinitializing driver!"); 878 879 dev->sc_flags |= SBICF_ALIVE; 880 dev->sc_flags &= ~SBICF_SELECTED; 881 882 /* 883 * initialize inhibit array 884 */ 885 if ( scsi_nosync ) { 886 887 u_int inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 888 889 shift_nosync += 8; 890 891 #ifdef DEBUG 892 if ( inhibit_sync ) 893 printf("%s: Inhibiting synchronous transfer %02x\n", 894 dev->sc_dev.dv_xname, inhibit_sync); 895 #endif 896 for (i = 0; i < 8; ++i) { 897 if ( inhibit_sync & (1 << i) ) 898 sbic_inhibit_sync[i] = 1; 899 } 900 } 901 902 sbicreset(dev); 903 } 904 905 void 906 sbicreset(dev) 907 struct sbic_softc *dev; 908 { 909 sbic_regmap_p regs = dev->sc_sbicp; 910 u_int my_id, 911 s; 912 u_char csr; 913 914 s = splbio(); 915 916 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 917 918 if (dev->sc_clkfreq < 110) 919 my_id |= SBIC_ID_FS_8_10; 920 else if (dev->sc_clkfreq < 160) 921 my_id |= SBIC_ID_FS_12_15; 922 else if (dev->sc_clkfreq < 210) 923 my_id |= SBIC_ID_FS_16_20; 924 925 SET_SBIC_myid(regs, my_id); 926 927 /* 928 * Reset the chip 929 */ 930 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 931 DELAY(25); 932 933 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 934 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 935 936 /* 937 * Set up various chip parameters 938 */ 939 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 940 941 /* 942 * don't allow Selection (SBIC_RID_ES) 943 * until we can handle target mode!! 944 */ 945 SET_SBIC_rselid(regs, SBIC_RID_ER); 946 947 /* 948 * Asynchronous for now 949 */ 950 SET_SBIC_syn(regs, 0); 951 952 /* 953 * Anything else was zeroed by reset 954 */ 955 splx(s); 956 957 dev->sc_flags &= ~SBICF_SELECTED; 958 } 959 960 void 961 sbicerror(dev, csr) 962 struct sbic_softc *dev; 963 u_char csr; 964 { 965 struct scsipi_xfer *xs = dev->sc_xs; 966 967 #ifdef DIAGNOSTIC 968 if ( xs == NULL ) 969 panic("sbicerror: dev->sc_xs == NULL"); 970 #endif 971 972 if ( xs->flags & SCSI_SILENT ) 973 return; 974 975 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 976 } 977 978 /* 979 * select the bus, return when selected or error. 980 * 981 * Returns the current CSR following selection and optionally MSG out phase. 982 * i.e. the returned CSR *should* indicate CMD phase... 983 * If the return value is 0, some error happened. 984 */ 985 u_char 986 sbicselectbus(dev) 987 struct sbic_softc *dev; 988 { 989 sbic_regmap_p regs = dev->sc_sbicp; 990 u_char target = dev->target, 991 lun = dev->lun, 992 asr, 993 csr, 994 id; 995 996 /* 997 * if we're already selected, return (XXXX panic maybe?) 998 */ 999 if ( dev->sc_flags & SBICF_SELECTED ) 1000 return(0); 1001 1002 QPRINTF(("sbicselectbus %d: ", target)); 1003 1004 /* 1005 * issue select 1006 */ 1007 SET_SBIC_selid(regs, target); 1008 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 1009 1010 GET_SBIC_asr(regs, asr); 1011 1012 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1013 /* 1014 * This means we got ourselves reselected upon 1015 */ 1016 QPRINTF(("WD busy (reselect?)\n")); 1017 return 0; 1018 } 1019 1020 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1021 1022 /* 1023 * wait for select (merged from seperate function may need 1024 * cleanup) 1025 */ 1026 WAIT_CIP(regs); 1027 1028 do { 1029 1030 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1031 1032 if ( asr & SBIC_ASR_LCI ) { 1033 QPRINTF(("late LCI: asr %02x\n", asr)); 1034 return 0; 1035 } 1036 1037 /* 1038 * Clear interrupt 1039 */ 1040 GET_SBIC_csr (regs, csr); 1041 1042 QPRINTF(("%02x ", csr)); 1043 1044 /* 1045 * Reselected from under our feet? 1046 */ 1047 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 1048 QPRINTF(("got reselected, asr %02x\n", asr)); 1049 /* 1050 * We need to handle this now so we don't lock up later 1051 */ 1052 sbicnextstate(dev, csr, asr); 1053 1054 return 0; 1055 } 1056 1057 /* 1058 * Whoops! 1059 */ 1060 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1061 panic("sbicselectbus: target issued select!"); 1062 return 0; 1063 } 1064 1065 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1066 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1067 csr != SBIC_CSR_SEL_TIMEO); 1068 1069 /* 1070 * Anyone at home? 1071 */ 1072 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1073 dev->sc_xs->error = XS_SELTIMEOUT; 1074 QPRINTF(("Selection Timeout\n")); 1075 return 0; 1076 } 1077 1078 QPRINTF(("Selection Complete\n")); 1079 1080 /* 1081 * Assume we're now selected 1082 */ 1083 GET_SBIC_selid(regs, id); 1084 dev->target = id; 1085 dev->lun = lun; 1086 dev->sc_flags |= SBICF_SELECTED; 1087 1088 /* 1089 * Enable (or not) reselection 1090 * XXXSCW This is probably not necessary since we don't use use the 1091 * Select-and-Xfer-with-ATN command to initiate a selection... 1092 */ 1093 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1094 SET_SBIC_rselid (regs, 0); 1095 else 1096 SET_SBIC_rselid (regs, SBIC_RID_ER); 1097 1098 /* 1099 * We only really need to do anything when the target goes to MSG out 1100 * If the device ignored ATN, it's probably old and brain-dead, 1101 * but we'll try to support it anyhow. 1102 * If it doesn't support message out, it definately doesn't 1103 * support synchronous transfers, so no point in even asking... 1104 */ 1105 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1106 /* 1107 * Send identify message (SCSI-2 requires an identify msg) 1108 */ 1109 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1110 /* 1111 * Handle drives that don't want to be asked 1112 * whether to go sync at all. 1113 */ 1114 dev->sc_sync[id].offset = 0; 1115 dev->sc_sync[id].period = sbic_min_period; 1116 dev->sc_sync[id].state = SYNC_DONE; 1117 } 1118 1119 /* 1120 * Do we need to negotiate Synchronous Xfers for this target? 1121 */ 1122 if ( dev->sc_sync[id].state != SYNC_START ) { 1123 /* 1124 * Nope, we've already negotiated. 1125 * Now see if we should allow the target to disconnect/reselect... 1126 */ 1127 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 1128 !sbic_enable_reselect ) 1129 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1130 else 1131 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1132 1133 } else { 1134 /* 1135 * try to initiate a sync transfer. 1136 * So compose the sync message we're going 1137 * to send to the target 1138 */ 1139 #ifdef DEBUG 1140 if ( sync_debug ) 1141 printf("\nSending sync request to target %d ... ", id); 1142 #endif 1143 /* 1144 * setup scsi message sync message request 1145 */ 1146 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1147 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1148 dev->sc_msg[2] = 3; 1149 dev->sc_msg[3] = MSG_SYNC_REQ; 1150 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1151 dev->sc_msg[5] = sbic_max_offset; 1152 1153 sbicxfout(regs, 6, dev->sc_msg); 1154 1155 dev->sc_sync[id].state = SYNC_SENT; 1156 #ifdef DEBUG 1157 if ( sync_debug ) 1158 printf ("sent\n"); 1159 #endif 1160 } 1161 1162 /* 1163 * There's one interrupt still to come: the change to CMD phase... 1164 */ 1165 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1166 GET_SBIC_csr(regs, csr); 1167 } 1168 1169 /* 1170 * set sync or async 1171 */ 1172 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1173 #ifdef DEBUG 1174 if ( sync_debug ) 1175 printf("select(%d): sync reg = 0x%02x\n", target, 1176 SBIC_SYN(dev->sc_sync[target].offset, 1177 dev->sc_sync[target].period)); 1178 #endif 1179 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1180 dev->sc_sync[target].period)); 1181 } else { 1182 #ifdef DEBUG 1183 if ( sync_debug ) 1184 printf("select(%d): sync reg = 0x%02x\n", target, 1185 SBIC_SYN(0,sbic_min_period)); 1186 #endif 1187 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1188 } 1189 1190 return csr; 1191 } 1192 1193 /* 1194 * Information Transfer *to* a Scsi Target. 1195 * 1196 * Note: Don't expect there to be an interrupt immediately after all 1197 * the data is transferred out. The WD spec sheet says that the Transfer- 1198 * Info command for non-MSG_IN phases only completes when the target 1199 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1200 * 1201 * This can have a nasty effect on commands which take a relatively long 1202 * time to complete, for example a START/STOP unit command may remain in 1203 * CMD phase until the disk has spun up. Only then will the target change 1204 * to STATUS phase. This is really only a problem for immediate commands 1205 * since we don't allow disconnection for them (yet). 1206 */ 1207 int 1208 sbicxfout(regs, len, bp) 1209 sbic_regmap_p regs; 1210 int len; 1211 void *bp; 1212 { 1213 int wait = sbic_data_wait; 1214 u_char asr, 1215 *buf = bp; 1216 1217 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1218 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1219 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1220 1221 /* 1222 * sigh.. WD-PROTO strikes again.. sending the command in one go 1223 * causes the chip to lock up if talking to certain (misbehaving?) 1224 * targets. Anyway, this procedure should work for all targets, but 1225 * it's slightly slower due to the overhead 1226 */ 1227 WAIT_CIP (regs); 1228 1229 SBIC_TC_PUT (regs, 0); 1230 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1231 SBIC_TC_PUT (regs, (unsigned)len); 1232 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1233 1234 /* 1235 * Loop for each byte transferred 1236 */ 1237 do { 1238 1239 GET_SBIC_asr (regs, asr); 1240 1241 if ( asr & SBIC_ASR_DBR ) { 1242 if ( len ) { 1243 SET_SBIC_data (regs, *buf); 1244 buf++; 1245 len--; 1246 } else { 1247 SET_SBIC_data (regs, 0); 1248 } 1249 wait = sbic_data_wait; 1250 } 1251 1252 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1253 1254 #ifdef DEBUG 1255 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1256 #endif 1257 1258 /* 1259 * Normally, an interrupt will be pending when this routing returns. 1260 */ 1261 return(len); 1262 } 1263 1264 /* 1265 * Information Transfer *from* a Scsi Target 1266 * returns # bytes left to read 1267 */ 1268 int 1269 sbicxfin(regs, len, bp) 1270 sbic_regmap_p regs; 1271 int len; 1272 void *bp; 1273 { 1274 int wait = sbic_data_wait; 1275 u_char *buf = bp; 1276 u_char asr; 1277 #ifdef DEBUG 1278 u_char *obp = bp; 1279 #endif 1280 1281 WAIT_CIP (regs); 1282 1283 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1284 SBIC_TC_PUT (regs, (unsigned)len); 1285 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1286 1287 /* 1288 * Loop for each byte transferred 1289 */ 1290 do { 1291 1292 GET_SBIC_asr (regs, asr); 1293 1294 if ( asr & SBIC_ASR_DBR ) { 1295 if ( len ) { 1296 GET_SBIC_data (regs, *buf); 1297 buf++; 1298 len--; 1299 } else { 1300 u_char foo; 1301 GET_SBIC_data (regs, foo); 1302 } 1303 wait = sbic_data_wait; 1304 } 1305 1306 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1307 1308 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1309 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1310 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1311 1312 SBIC_TC_PUT (regs, 0); 1313 1314 /* 1315 * this leaves with one csr to be read 1316 */ 1317 return len; 1318 } 1319 1320 /* 1321 * SCSI 'immediate' command: issue a command to some SCSI device 1322 * and get back an 'immediate' response (i.e., do programmed xfer 1323 * to get the response data). 'cbuf' is a buffer containing a scsi 1324 * command of length clen bytes. 'buf' is a buffer of length 'len' 1325 * bytes for data. The transfer direction is determined by the device 1326 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1327 * command must supply no data. 1328 * 1329 * Note that although this routine looks like it can handle disconnect/ 1330 * reselect, the fact is that it can't. There is still some work to be 1331 * done to clean this lot up. 1332 */ 1333 int 1334 sbicicmd(dev, cbuf, clen, buf, len) 1335 struct sbic_softc *dev; 1336 void *cbuf, 1337 *buf; 1338 int clen, 1339 len; 1340 { 1341 sbic_regmap_p regs = dev->sc_sbicp; 1342 struct sbic_acb *acb = dev->sc_nexus; 1343 u_char csr, 1344 asr; 1345 int still_busy = SBIC_STATE_RUNNING; 1346 #ifdef DEBUG 1347 int counter = 0; 1348 #endif 1349 1350 /* 1351 * Make sure pointers are OK 1352 */ 1353 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1354 dev->sc_tcnt = acb->sc_tcnt = 0; 1355 1356 acb->sc_dmacmd = 0; 1357 acb->sc_pa.dc_count = 0; /* No DMA */ 1358 acb->sc_kv.dc_addr = buf; 1359 acb->sc_kv.dc_count = len; 1360 1361 #ifdef DEBUG 1362 if ( data_pointer_debug > 1 ) 1363 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1364 #endif 1365 1366 /* 1367 * set the sbic into non-DMA mode 1368 */ 1369 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1370 1371 dev->sc_stat[0] = 0xff; 1372 dev->sc_msg[0] = 0xff; 1373 1374 /* 1375 * We're stealing the SCSI bus 1376 */ 1377 dev->sc_flags |= SBICF_ICMD; 1378 1379 do { 1380 GET_SBIC_asr (regs, asr); 1381 1382 /* 1383 * select the SCSI bus (it's an error if bus isn't free) 1384 */ 1385 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1386 still_busy != SBIC_STATE_DISCONNECT ) { 1387 if ( (csr = sbicselectbus(dev)) == 0 ) { 1388 dev->sc_flags &= ~SBICF_ICMD; 1389 return(-1); 1390 } 1391 } else 1392 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1393 GET_SBIC_csr(regs, csr); 1394 else 1395 csr = 0; 1396 1397 if ( csr ) { 1398 1399 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1400 1401 switch ( csr ) { 1402 1403 case SBIC_CSR_S_XFERRED: 1404 case SBIC_CSR_DISC: 1405 case SBIC_CSR_DISC_1: 1406 { 1407 u_char phase; 1408 1409 dev->sc_flags &= ~SBICF_SELECTED; 1410 GET_SBIC_cmd_phase (regs, phase); 1411 1412 if ( phase == 0x60 ) { 1413 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1414 still_busy = SBIC_STATE_DONE; /* done */ 1415 } else { 1416 #ifdef DEBUG 1417 if ( reselect_debug > 1 ) 1418 printf("sbicicmd: handling disconnect\n"); 1419 #endif 1420 still_busy = SBIC_STATE_DISCONNECT; 1421 } 1422 } 1423 break; 1424 1425 case SBIC_CSR_XFERRED | CMD_PHASE: 1426 case SBIC_CSR_MIS | CMD_PHASE: 1427 case SBIC_CSR_MIS_1 | CMD_PHASE: 1428 case SBIC_CSR_MIS_2 | CMD_PHASE: 1429 { 1430 if ( sbicxfout(regs, clen, cbuf) ) 1431 still_busy = sbicabort(dev, "icmd sending cmd"); 1432 } 1433 break; 1434 1435 case SBIC_CSR_XFERRED | STATUS_PHASE: 1436 case SBIC_CSR_MIS | STATUS_PHASE: 1437 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1438 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1439 { 1440 /* 1441 * The sbic does the status/cmd-complete reading ok, 1442 * so do this with its hi-level commands. 1443 */ 1444 #ifdef DEBUG 1445 if ( sbic_debug ) 1446 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1447 #endif 1448 SET_SBIC_cmd_phase(regs, 0x46); 1449 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1450 } 1451 break; 1452 1453 default: 1454 { 1455 still_busy = sbicnextstate(dev, csr, asr); 1456 } 1457 break; 1458 } 1459 1460 /* 1461 * make sure the last command was taken, 1462 * ie. we're not hunting after an ignored command.. 1463 */ 1464 GET_SBIC_asr(regs, asr); 1465 1466 /* 1467 * tapes may take a loooong time.. 1468 */ 1469 while (asr & SBIC_ASR_BSY ) { 1470 1471 if ( asr & SBIC_ASR_DBR ) { 1472 int i; 1473 1474 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1475 #ifdef DDB 1476 Debugger(); 1477 #endif 1478 /* 1479 * SBIC is jammed 1480 * DUNNO which direction 1481 * Try old direction 1482 */ 1483 GET_SBIC_data(regs, i); 1484 GET_SBIC_asr(regs, asr); 1485 1486 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1487 SET_SBIC_data(regs, i); 1488 } 1489 1490 GET_SBIC_asr(regs, asr); 1491 } 1492 } 1493 1494 /* 1495 * wait for last command to complete 1496 */ 1497 if ( asr & SBIC_ASR_LCI ) { 1498 printf("sbicicmd: last command ignored\n"); 1499 } 1500 else 1501 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1502 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1503 1504 /* 1505 * do it again 1506 */ 1507 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1508 1509 /* 1510 * Sometimes we need to do an extra read of the CSR 1511 */ 1512 GET_SBIC_csr(regs, csr); 1513 1514 #ifdef DEBUG 1515 if ( data_pointer_debug > 1 ) 1516 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1517 acb->sc_kv.dc_count, 1518 dev->sc_stat[0]); 1519 #endif 1520 1521 dev->sc_flags &= ~SBICF_ICMD; 1522 1523 return(dev->sc_stat[0]); 1524 } 1525 1526 /* 1527 * Finish SCSI xfer command: After the completion interrupt from 1528 * a read/write operation, sequence through the final phases in 1529 * programmed i/o. This routine is a lot like sbicicmd except we 1530 * skip (and don't allow) the select, cmd out and data in/out phases. 1531 */ 1532 void 1533 sbicxfdone(dev) 1534 struct sbic_softc *dev; 1535 { 1536 sbic_regmap_p regs = dev->sc_sbicp; 1537 u_char phase, 1538 csr; 1539 int s; 1540 1541 QPRINTF(("{")); 1542 s = splbio(); 1543 1544 /* 1545 * have the sbic complete on its own 1546 */ 1547 SBIC_TC_PUT(regs, 0); 1548 SET_SBIC_cmd_phase(regs, 0x46); 1549 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1550 1551 do { 1552 1553 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1554 GET_SBIC_csr (regs, csr); 1555 QPRINTF(("%02x:", csr)); 1556 1557 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1558 (csr != SBIC_CSR_S_XFERRED)); 1559 1560 dev->sc_flags &= ~SBICF_SELECTED; 1561 1562 GET_SBIC_cmd_phase (regs, phase); 1563 QPRINTF(("}%02x", phase)); 1564 1565 if ( phase == 0x60 ) 1566 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1567 else 1568 sbicerror(dev, csr); 1569 1570 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1571 1572 splx(s); 1573 } 1574 1575 /* 1576 * No DMA chains 1577 */ 1578 int 1579 sbicgo(dev, xs) 1580 struct sbic_softc *dev; 1581 struct scsipi_xfer *xs; 1582 { 1583 struct sbic_acb *acb = dev->sc_nexus; 1584 sbic_regmap_p regs = dev->sc_sbicp; 1585 int i, 1586 dmaflags, 1587 count, 1588 usedma; 1589 u_char csr, 1590 asr, 1591 *addr; 1592 1593 dev->target = xs->sc_link->scsipi_scsi.target; 1594 dev->lun = xs->sc_link->scsipi_scsi.lun; 1595 1596 usedma = sbicdmaok(dev, xs); 1597 1598 #ifdef DEBUG 1599 if ( data_pointer_debug > 1 ) 1600 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1601 #endif 1602 1603 /* 1604 * select the SCSI bus (it's an error if bus isn't free) 1605 */ 1606 if ( (csr = sbicselectbus(dev)) == 0 ) 1607 return(0); /* Not done: needs to be rescheduled */ 1608 1609 dev->sc_stat[0] = 0xff; 1610 1611 /* 1612 * Calculate DMA chains now 1613 */ 1614 if ( acb->flags & ACB_DATAIN ) 1615 dmaflags = DMAGO_READ; 1616 else 1617 dmaflags = 0; 1618 1619 addr = acb->sc_kv.dc_addr; 1620 count = acb->sc_kv.dc_count; 1621 1622 if ( count && ((char *)kvtop(addr) != acb->sc_pa.dc_addr) ) { 1623 printf("sbic: DMA buffer mapping changed %x->%x\n", 1624 acb->sc_pa.dc_addr, kvtop(addr)); 1625 #ifdef DDB 1626 Debugger(); 1627 #endif 1628 } 1629 1630 #ifdef DEBUG 1631 ++sbicdma_ops; /* count total DMA operations */ 1632 #endif 1633 1634 /* 1635 * Allocate the DMA chain 1636 * Mark end of segment... 1637 */ 1638 acb->sc_tcnt = dev->sc_tcnt = 0; 1639 acb->sc_pa.dc_count = 0; 1640 1641 sbic_load_ptrs(dev); 1642 1643 /* 1644 * Enable interrupts but don't do any DMA 1645 * enintr() also enables interrupts for the sbic 1646 */ 1647 dev->sc_enintr(dev); 1648 1649 if ( usedma ) { 1650 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1651 acb->sc_pa.dc_count, dmaflags); 1652 #ifdef DEBUG 1653 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1654 #endif 1655 } else 1656 dev->sc_dmacmd = 0; /* Don't use DMA */ 1657 1658 acb->sc_dmacmd = dev->sc_dmacmd; 1659 1660 #ifdef DEBUG 1661 if ( data_pointer_debug > 1 ) { 1662 printf("sbicgo dmago:%d(%x:%x) dmacmd=0x%02x\n", dev->target, 1663 dev->sc_cur->dc_addr, 1664 dev->sc_tcnt, 1665 dev->sc_dmacmd); 1666 } 1667 #endif 1668 1669 /* 1670 * Lets cycle a while then let the interrupt handler take over. 1671 */ 1672 GET_SBIC_asr(regs, asr); 1673 1674 do { 1675 1676 QPRINTF(("go ")); 1677 1678 /* 1679 * Handle the new phase 1680 */ 1681 i = sbicnextstate(dev, csr, asr); 1682 #if 0 1683 WAIT_CIP(regs); 1684 #endif 1685 if ( i == SBIC_STATE_RUNNING ) { 1686 GET_SBIC_asr(regs, asr); 1687 1688 if ( asr & SBIC_ASR_LCI ) 1689 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1690 1691 if ( asr & SBIC_ASR_INT ) 1692 GET_SBIC_csr(regs, csr); 1693 } 1694 1695 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1696 1697 if ( i == SBIC_STATE_DONE ) { 1698 if ( dev->sc_stat[0] == 0xff ) 1699 #if 0 1700 printf("sbicgo: done & stat = 0xff\n"); 1701 #else 1702 ; 1703 #endif 1704 else 1705 return 1; /* Did we really finish that fast? */ 1706 } 1707 1708 return 0; 1709 } 1710 1711 1712 int 1713 sbicintr(dev) 1714 struct sbic_softc *dev; 1715 { 1716 sbic_regmap_p regs = dev->sc_sbicp; 1717 u_char asr, 1718 csr; 1719 int i; 1720 1721 /* 1722 * pending interrupt? 1723 */ 1724 GET_SBIC_asr (regs, asr); 1725 if ( (asr & SBIC_ASR_INT) == 0 ) 1726 return(0); 1727 1728 GET_SBIC_csr(regs, csr); 1729 1730 do { 1731 1732 QPRINTF(("intr[0x%x]", csr)); 1733 1734 i = sbicnextstate(dev, csr, asr); 1735 #if 0 1736 WAIT_CIP(regs); 1737 #endif 1738 if ( i == SBIC_STATE_RUNNING ) { 1739 GET_SBIC_asr(regs, asr); 1740 1741 if ( asr & SBIC_ASR_LCI ) 1742 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1743 1744 if ( asr & SBIC_ASR_INT ) 1745 GET_SBIC_csr(regs, csr); 1746 } 1747 1748 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1749 1750 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1751 1752 return(1); 1753 } 1754 1755 /* 1756 * Run commands and wait for disconnect. 1757 * This is only ever called when a command is in progress, when we 1758 * want to busy wait for it to finish. 1759 */ 1760 int 1761 sbicpoll(dev) 1762 struct sbic_softc *dev; 1763 { 1764 sbic_regmap_p regs = dev->sc_sbicp; 1765 u_char asr, 1766 csr; 1767 int i; 1768 1769 /* 1770 * Wait for the next interrupt 1771 */ 1772 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1773 1774 do { 1775 GET_SBIC_asr (regs, asr); 1776 1777 if ( asr & SBIC_ASR_INT ) 1778 GET_SBIC_csr(regs, csr); 1779 1780 QPRINTF(("poll[0x%x]", csr)); 1781 1782 /* 1783 * Handle it 1784 */ 1785 i = sbicnextstate(dev, csr, asr); 1786 1787 WAIT_CIP(regs); 1788 GET_SBIC_asr(regs, asr); 1789 1790 /* 1791 * tapes may take a loooong time.. 1792 */ 1793 while ( asr & SBIC_ASR_BSY ) { 1794 u_char z = 0; 1795 1796 if ( asr & SBIC_ASR_DBR ) { 1797 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1798 #ifdef DDB 1799 Debugger(); 1800 #endif 1801 /* 1802 * SBIC is jammed 1803 * DUNNO which direction 1804 * Try old direction 1805 */ 1806 GET_SBIC_data(regs, z); 1807 GET_SBIC_asr(regs, asr); 1808 1809 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1810 SET_SBIC_data(regs, z); 1811 } 1812 1813 GET_SBIC_asr(regs, asr); 1814 } 1815 1816 if ( asr & SBIC_ASR_LCI ) 1817 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1818 else 1819 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1820 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1821 1822 } while ( i == SBIC_STATE_RUNNING ); 1823 1824 return(1); 1825 } 1826 1827 /* 1828 * Handle a single msgin 1829 */ 1830 int 1831 sbicmsgin(dev) 1832 struct sbic_softc *dev; 1833 { 1834 sbic_regmap_p regs = dev->sc_sbicp; 1835 int recvlen = 1; 1836 u_char asr, 1837 csr, 1838 *tmpaddr, 1839 *msgaddr; 1840 1841 tmpaddr = msgaddr = dev->sc_msg; 1842 1843 tmpaddr[0] = 0xff; 1844 tmpaddr[1] = 0xff; 1845 1846 GET_SBIC_asr(regs, asr); 1847 1848 #ifdef DEBUG 1849 if ( reselect_debug > 1 ) 1850 printf("sbicmsgin asr=%02x\n", asr); 1851 #endif 1852 1853 GET_SBIC_selid (regs, csr); 1854 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1855 1856 SBIC_TC_PUT(regs, 0); 1857 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1858 1859 do { 1860 while( recvlen-- ) { 1861 1862 /* 1863 * Fetch the next byte of the message 1864 */ 1865 RECV_BYTE(regs, *tmpaddr); 1866 1867 /* 1868 * get the command completion interrupt, or we 1869 * can't send a new command (LCI) 1870 */ 1871 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1872 GET_SBIC_csr(regs, csr); 1873 1874 #ifdef DEBUG 1875 if ( reselect_debug > 1 ) 1876 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1877 #endif 1878 1879 tmpaddr++; 1880 1881 if ( recvlen ) { 1882 /* 1883 * Clear ACK, and wait for the interrupt for the next byte 1884 */ 1885 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1886 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1887 GET_SBIC_csr(regs, csr); 1888 } 1889 } 1890 1891 if ( msgaddr[0] == 0xff ) { 1892 printf("sbicmsgin: sbic swallowed our message\n"); 1893 break; 1894 } 1895 1896 #ifdef DEBUG 1897 if ( sync_debug ) { 1898 GET_SBIC_asr(regs, asr); 1899 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1900 } 1901 #endif 1902 /* 1903 * test whether this is a reply to our sync 1904 * request 1905 */ 1906 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1907 1908 /* 1909 * Got IFFY msg -- ack it 1910 */ 1911 QPRINTF(("IFFY")); 1912 1913 } else 1914 if ( msgaddr[0] == MSG_REJECT && 1915 dev->sc_sync[dev->target].state == SYNC_SENT) { 1916 1917 /* 1918 * Target probably rejected our Sync negotiation. 1919 */ 1920 QPRINTF(("REJECT of SYN")); 1921 1922 #ifdef DEBUG 1923 if ( sync_debug ) 1924 printf("target %d rejected sync, going async\n", dev->target); 1925 #endif 1926 1927 dev->sc_sync[dev->target].period = sbic_min_period; 1928 dev->sc_sync[dev->target].offset = 0; 1929 dev->sc_sync[dev->target].state = SYNC_DONE; 1930 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1931 dev->sc_sync[dev->target].period)); 1932 1933 } else 1934 if ( msgaddr[0] == MSG_REJECT ) { 1935 1936 /* 1937 * we'll never REJECt a REJECT message.. 1938 */ 1939 QPRINTF(("REJECT")); 1940 1941 } else 1942 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1943 1944 /* 1945 * don't reject this either. 1946 */ 1947 QPRINTF(("MSG_SAVE_DATA_PTR")); 1948 1949 } else 1950 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1951 1952 /* 1953 * don't reject this either. 1954 */ 1955 QPRINTF(("MSG_RESTORE_PTR")); 1956 1957 } else 1958 if ( msgaddr[0] == MSG_DISCONNECT ) { 1959 1960 /* 1961 * Target is disconnecting... 1962 */ 1963 QPRINTF(("DISCONNECT")); 1964 1965 #ifdef DEBUG 1966 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1967 printf("sbicmsgin: got disconnect msg %s\n", 1968 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1969 #endif 1970 1971 if ( dev->sc_flags & SBICF_ICMD ) { 1972 /* 1973 * We're in immediate mode. Prevent disconnects. 1974 * prepare to reject the message, NACK 1975 */ 1976 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1977 WAIT_CIP(regs); 1978 } 1979 1980 } else 1981 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1982 1983 /* 1984 * !! KLUDGE ALERT !! quite a few drives don't seem to 1985 * really like the current way of sending the 1986 * sync-handshake together with the ident-message, and 1987 * they react by sending command-complete and 1988 * disconnecting right after returning the valid sync 1989 * handshake. So, all I can do is reselect the drive, 1990 * and hope it won't disconnect again. I don't think 1991 * this is valid behavior, but I can't help fixing a 1992 * problem that apparently exists. 1993 * 1994 * Note: we should not get here on `normal' command 1995 * completion, as that condition is handled by the 1996 * high-level sel&xfer resume command used to walk 1997 * thru status/cc-phase. 1998 */ 1999 QPRINTF(("CMD_COMPLETE")); 2000 2001 #ifdef DEBUG 2002 if ( sync_debug ) 2003 printf ("GOT MSG %d! target %d acting weird.." 2004 " waiting for disconnect...\n", msgaddr[0], dev->target); 2005 #endif 2006 2007 /* 2008 * Check to see if sbic is handling this 2009 */ 2010 GET_SBIC_asr(regs, asr); 2011 2012 /* 2013 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 2014 */ 2015 if ( asr & SBIC_ASR_BSY ) 2016 return SBIC_STATE_RUNNING; 2017 2018 /* 2019 * Let's try this: Assume it works and set status to 00 2020 */ 2021 dev->sc_stat[0] = 0; 2022 2023 } else 2024 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 2025 2026 /* 2027 * Target is sending us an extended message. We'll assume it's 2028 * the response to our Sync. negotiation. 2029 */ 2030 QPRINTF(("ExtMSG\n")); 2031 2032 /* 2033 * Read in whole extended message. First, negate ACK to accept 2034 * the MSG_EXT_MESSAGE byte... 2035 */ 2036 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2037 2038 /* 2039 * Wait for the interrupt for the next byte (length) 2040 */ 2041 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2042 GET_SBIC_csr(regs, csr); 2043 2044 #ifdef DEBUG 2045 QPRINTF(("CLR ACK csr %02x\n", csr)); 2046 #endif 2047 2048 /* 2049 * Read the length byte 2050 */ 2051 RECV_BYTE(regs, *tmpaddr); 2052 2053 /* 2054 * Wait for command completion IRQ 2055 */ 2056 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2057 GET_SBIC_csr(regs, csr); 2058 2059 /* 2060 * Reload the loop counter 2061 */ 2062 recvlen = *tmpaddr++; 2063 2064 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2065 2066 } else 2067 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2068 msgaddr[2] == MSG_SYNC_REQ ) { 2069 2070 /* 2071 * We've received the complete Extended Message Sync. Request... 2072 */ 2073 QPRINTF(("SYN")); 2074 2075 /* 2076 * Compute the required Transfer Period for the WD chip... 2077 */ 2078 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2079 dev->sc_sync[dev->target].offset = msgaddr[4]; 2080 dev->sc_sync[dev->target].state = SYNC_DONE; 2081 2082 /* 2083 * Put the WD chip in synchronous mode 2084 */ 2085 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2086 dev->sc_sync[dev->target].period)); 2087 #ifdef DEBUG 2088 if ( sync_debug ) 2089 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2090 SBIC_SYN(dev->sc_sync[dev->target].offset, 2091 dev->sc_sync[dev->target].period)); 2092 #endif 2093 2094 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2095 dev->sc_dev.dv_xname, dev->target, 2096 msgaddr[3] * 4, msgaddr[4]); 2097 2098 } else { 2099 2100 /* 2101 * We don't support whatever this message is... 2102 */ 2103 #ifdef DEBUG 2104 if ( sbic_debug || sync_debug ) 2105 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2106 #endif 2107 2108 /* 2109 * prepare to reject the message, NACK 2110 */ 2111 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2112 WAIT_CIP(regs); 2113 } 2114 2115 /* 2116 * Negate ACK to complete the transfer 2117 */ 2118 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2119 2120 /* 2121 * Wait for the interrupt for the next byte, or phase change. 2122 * Only read the CSR if we have more data to transfer. 2123 * XXXSCW: We should really verify that we're still in MSG IN phase 2124 * before blindly going back around this loop, but that would mean 2125 * we read the CSR... <sigh> 2126 */ 2127 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2128 if ( recvlen > 0 ) 2129 GET_SBIC_csr(regs, csr); 2130 2131 } while ( recvlen > 0 ); 2132 2133 /* 2134 * Should still have one CSR to read 2135 */ 2136 return SBIC_STATE_RUNNING; 2137 } 2138 2139 2140 /* 2141 * sbicnextstate() 2142 * return: 2143 * SBIC_STATE_DONE == done 2144 * SBIC_STATE_RUNNING == working 2145 * SBIC_STATE_DISCONNECT == disconnected 2146 * SBIC_STATE_ERROR == error 2147 */ 2148 int 2149 sbicnextstate(dev, csr, asr) 2150 struct sbic_softc *dev; 2151 u_char csr, 2152 asr; 2153 { 2154 sbic_regmap_p regs = dev->sc_sbicp; 2155 struct sbic_acb *acb = dev->sc_nexus; 2156 2157 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2158 2159 switch (csr) { 2160 2161 case SBIC_CSR_XFERRED | CMD_PHASE: 2162 case SBIC_CSR_MIS | CMD_PHASE: 2163 case SBIC_CSR_MIS_1 | CMD_PHASE: 2164 case SBIC_CSR_MIS_2 | CMD_PHASE: 2165 { 2166 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2167 goto abort; 2168 } 2169 break; 2170 2171 case SBIC_CSR_XFERRED | STATUS_PHASE: 2172 case SBIC_CSR_MIS | STATUS_PHASE: 2173 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2174 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2175 { 2176 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2177 2178 /* 2179 * this should be the normal i/o completion case. 2180 * get the status & cmd complete msg then let the 2181 * device driver look at what happened. 2182 */ 2183 sbicxfdone(dev); 2184 2185 #ifdef DEBUG 2186 dev->sc_dmatimo = 0; 2187 if ( data_pointer_debug > 1 ) 2188 printf("next dmastop: %d(%x:%x)\n", dev->target, 2189 dev->sc_cur->dc_addr, 2190 dev->sc_tcnt); 2191 #endif 2192 /* 2193 * Stop the DMA chip 2194 */ 2195 dev->sc_dmastop(dev); 2196 2197 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2198 2199 /* 2200 * Indicate to the upper layers that the command is done 2201 */ 2202 sbic_scsidone(acb, dev->sc_stat[0]); 2203 2204 return SBIC_STATE_DONE; 2205 } 2206 2207 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2208 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2209 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2210 case SBIC_CSR_MIS | DATA_IN_PHASE: 2211 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2212 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2213 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2214 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2215 { 2216 /* 2217 * Verify that we expected to transfer data... 2218 */ 2219 if ( acb->sc_kv.dc_count <= 0 ) { 2220 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2221 acb->sc_kv.dc_count, asr, csr); 2222 goto abort; 2223 } 2224 2225 /* 2226 * Should we transfer using PIO or DMA ? 2227 */ 2228 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2229 acb->sc_dmacmd == 0 ) { 2230 2231 /* 2232 * Do PIO transfer 2233 */ 2234 int i; 2235 2236 #ifdef DEBUG 2237 if ( data_pointer_debug > 1 ) 2238 printf("next PIO: %d(%x:%x)\n", dev->target, 2239 acb->sc_kv.dc_addr, 2240 acb->sc_kv.dc_count); 2241 #endif 2242 2243 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2244 /* 2245 * data in 2246 */ 2247 i = sbicxfin(regs, acb->sc_kv.dc_count, 2248 acb->sc_kv.dc_addr); 2249 else 2250 /* 2251 * data out 2252 */ 2253 i = sbicxfout(regs, acb->sc_kv.dc_count, 2254 acb->sc_kv.dc_addr); 2255 2256 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2257 acb->sc_kv.dc_count = i; 2258 2259 /* 2260 * Update current count... 2261 */ 2262 acb->sc_tcnt = dev->sc_tcnt = i; 2263 2264 dev->sc_flags &= ~SBICF_INDMA; 2265 2266 } else { 2267 2268 /* 2269 * Do DMA transfer 2270 * set next dma addr and dec count 2271 */ 2272 sbic_save_ptrs(dev); 2273 sbic_load_ptrs(dev); 2274 2275 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2276 SBIC_MACHINE_DMA_MODE); 2277 2278 #ifdef DEBUG 2279 dev->sc_dmatimo = 1; 2280 if ( data_pointer_debug > 1 ) 2281 printf("next DMA: %d(%x:%x)\n", dev->target, 2282 dev->sc_cur->dc_addr, 2283 dev->sc_tcnt); 2284 #endif 2285 /* 2286 * Start the DMA chip going 2287 */ 2288 dev->sc_tcnt = dev->sc_dmanext(dev); 2289 2290 /* 2291 * Tell the WD chip how much to transfer this time around 2292 */ 2293 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2294 2295 /* 2296 * Start the transfer 2297 */ 2298 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2299 2300 /* 2301 * Indicate that we're in DMA mode 2302 */ 2303 dev->sc_flags |= SBICF_INDMA; 2304 } 2305 } 2306 break; 2307 2308 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2309 case SBIC_CSR_MIS | MESG_IN_PHASE: 2310 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2311 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2312 { 2313 sbic_save_ptrs(dev); 2314 2315 /* 2316 * Handle a single message in... 2317 */ 2318 return sbicmsgin(dev); 2319 } 2320 2321 case SBIC_CSR_MSGIN_W_ACK: 2322 { 2323 /* 2324 * We should never see this since it's handled in 'sbicmsgin()' 2325 * but just for the sake of paranoia... 2326 */ 2327 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2328 printf("Acking unknown msgin CSR:%02x",csr); 2329 } 2330 break; 2331 2332 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2333 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2334 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2335 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2336 { 2337 /* 2338 * We only ever handle a message out phase here for sending a 2339 * REJECT message. 2340 */ 2341 sbic_save_ptrs(dev); 2342 2343 #ifdef DEBUG 2344 if (sync_debug) 2345 printf ("sending REJECT msg to last msg.\n"); 2346 #endif 2347 2348 SEND_BYTE(regs, MSG_REJECT); 2349 WAIT_CIP(regs); 2350 } 2351 break; 2352 2353 case SBIC_CSR_DISC: 2354 case SBIC_CSR_DISC_1: 2355 { 2356 /* 2357 * Try to schedule another target 2358 */ 2359 sbic_save_ptrs(dev); 2360 2361 dev->sc_flags &= ~SBICF_SELECTED; 2362 2363 #ifdef DEBUG 2364 if ( reselect_debug > 1 ) 2365 printf("sbicnext target %d disconnected\n", dev->target); 2366 #endif 2367 2368 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2369 2370 ++dev->sc_tinfo[dev->target].dconns; 2371 2372 dev->sc_nexus = NULL; 2373 dev->sc_xs = NULL; 2374 2375 if ( acb->xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2376 !sbic_parallel_operations ) 2377 return SBIC_STATE_DISCONNECT; 2378 2379 QPRINTF(("sbicnext: calling sbic_sched\n")); 2380 2381 sbic_sched(dev); 2382 2383 QPRINTF(("sbicnext: sbic_sched returned\n")); 2384 2385 return SBIC_STATE_DISCONNECT; 2386 } 2387 2388 case SBIC_CSR_RSLT_NI: 2389 case SBIC_CSR_RSLT_IFY: 2390 { 2391 /* 2392 * A reselection. 2393 * Note that since we don't enable Advanced Features (assuming 2394 * the WD chip is at least the 'A' revision), we're only ever 2395 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2396 * hell of it, we'll handle it anyway, for all the extra code 2397 * it needs... 2398 */ 2399 u_char newtarget, 2400 newlun; 2401 2402 GET_SBIC_rselid(regs, newtarget); 2403 2404 /* 2405 * check SBIC_RID_SIV? 2406 */ 2407 newtarget &= SBIC_RID_MASK; 2408 2409 if ( csr == SBIC_CSR_RSLT_IFY ) { 2410 2411 /* 2412 * Read Identify msg to avoid lockup 2413 */ 2414 GET_SBIC_data(regs, newlun); 2415 WAIT_CIP(regs); 2416 newlun &= SBIC_TLUN_MASK; 2417 2418 } else { 2419 2420 /* 2421 * Need to read Identify message the hard way, assuming 2422 * the target even sends us one... 2423 */ 2424 for (newlun = 255; newlun; --newlun) { 2425 GET_SBIC_asr(regs, asr); 2426 if (asr & SBIC_ASR_INT) 2427 break; 2428 delay(10); 2429 } 2430 2431 /* 2432 * If we didn't get an interrupt, somethink's up 2433 */ 2434 if ( (asr & SBIC_ASR_INT) == 0 ) { 2435 printf("%s: Reselect without identify? asr %x\n", 2436 dev->sc_dev.dv_xname, asr); 2437 newlun = 0; /* XXXX */ 2438 } else { 2439 /* 2440 * We got an interrupt, verify that it's a change to 2441 * message in phase, and if so read the message. 2442 */ 2443 GET_SBIC_csr(regs,csr); 2444 2445 if ( csr == SBIC_CSR_MIS | MESG_IN_PHASE || 2446 csr == SBIC_CSR_MIS_1 | MESG_IN_PHASE || 2447 csr == SBIC_CSR_MIS_2 | MESG_IN_PHASE ) { 2448 /* 2449 * Yup, gone to message in. Fetch the target LUN 2450 */ 2451 sbicmsgin(dev); 2452 newlun = dev->sc_msg[0] & 0x07; 2453 2454 } else { 2455 /* 2456 * Whoops! Target didn't go to message in phase!! 2457 */ 2458 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2459 newlun = 0; /* XXXSCW */ 2460 } 2461 } 2462 } 2463 2464 /* 2465 * Ok, we have the identity of the reselecting target. 2466 */ 2467 #ifdef DEBUG 2468 if ( reselect_debug > 1 || 2469 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2470 printf("sbicnext: reselect %s from targ %d lun %d\n", 2471 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2472 } 2473 #endif 2474 2475 if ( dev->sc_nexus ) { 2476 /* 2477 * Whoops! We've been reselected with an command in progress! 2478 * The best we can do is to put the current command back on the 2479 * ready list and hope for the best. 2480 */ 2481 #ifdef DEBUG 2482 if ( reselect_debug > 1 ) { 2483 printf("%s: reselect %s with active command\n", 2484 dev->sc_dev.dv_xname, 2485 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2486 } 2487 #endif 2488 2489 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2490 2491 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2492 2493 dev->sc_nexus = NULL; 2494 dev->sc_xs = NULL; 2495 } 2496 2497 /* 2498 * Reload sync values for this target 2499 */ 2500 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2501 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2502 dev->sc_sync[newtarget].period)); 2503 else 2504 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2505 2506 /* 2507 * Loop through the nexus list until we find the saved entry 2508 * for the reselecting target... 2509 */ 2510 for (acb = dev->nexus_list.tqh_first; acb; 2511 acb = acb->chain.tqe_next) { 2512 2513 if ( acb->xs->sc_link->scsipi_scsi.target == newtarget && 2514 acb->xs->sc_link->scsipi_scsi.lun == newlun) { 2515 /* 2516 * We've found the saved entry. Dequeue it, and 2517 * make it current again. 2518 */ 2519 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2520 2521 dev->sc_nexus = acb; 2522 dev->sc_xs = acb->xs; 2523 dev->sc_flags |= SBICF_SELECTED; 2524 dev->target = newtarget; 2525 dev->lun = newlun; 2526 break; 2527 } 2528 } 2529 2530 if ( acb == NULL ) { 2531 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2532 dev->sc_dev.dv_xname, 2533 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2534 &dev->nexus_list.tqh_first); 2535 panic("bad reselect in sbic"); 2536 } 2537 2538 if ( csr == SBIC_CSR_RSLT_IFY ) 2539 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2540 } 2541 break; 2542 2543 default: 2544 abort: 2545 { 2546 /* 2547 * Something unexpected happened -- deal with it. 2548 */ 2549 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2550 2551 #ifdef DDB 2552 Debugger(); 2553 #endif 2554 2555 #ifdef DEBUG 2556 dev->sc_dmatimo = 0; 2557 if ( data_pointer_debug > 1 ) 2558 printf("next dmastop: %d(%x:%x)\n", dev->target, 2559 dev->sc_cur->dc_addr, 2560 dev->sc_tcnt); 2561 #endif 2562 2563 dev->sc_dmastop(dev); 2564 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2565 if ( dev->sc_xs ) sbicerror(dev, csr); 2566 sbicabort(dev, "next"); 2567 2568 if ( dev->sc_flags & SBICF_INDMA ) { 2569 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2570 2571 #ifdef DEBUG 2572 dev->sc_dmatimo = 0; 2573 if ( data_pointer_debug > 1 ) 2574 printf("next dmastop: %d(%x:%x)\n", dev->target, 2575 dev->sc_cur->dc_addr, 2576 dev->sc_tcnt); 2577 #endif 2578 sbic_scsidone(acb, -1); 2579 } 2580 2581 return SBIC_STATE_ERROR; 2582 } 2583 } 2584 2585 return(SBIC_STATE_RUNNING); 2586 } 2587 2588 2589 /* 2590 * Check if DMA can not be used with specified buffer 2591 */ 2592 int 2593 sbiccheckdmap(bp, len, mask) 2594 void *bp; 2595 u_long len, 2596 mask; 2597 { 2598 u_char *buffer; 2599 u_long phy_buf; 2600 u_long phy_len; 2601 2602 buffer = bp; 2603 2604 if ( len == 0 ) 2605 return(1); 2606 2607 while ( len ) { 2608 2609 phy_buf = kvtop(buffer); 2610 phy_len = NBPG - ((int) buffer & PGOFSET); 2611 2612 if ( len < phy_len ) 2613 phy_len = len; 2614 2615 if ( phy_buf & mask ) 2616 return(1); 2617 2618 buffer += phy_len; 2619 len -= phy_len; 2620 } 2621 2622 return(0); 2623 } 2624 2625 int 2626 sbictoscsiperiod(dev, a) 2627 struct sbic_softc *dev; 2628 int a; 2629 { 2630 unsigned int fs; 2631 2632 /* 2633 * cycle = DIV / (2 * CLK) 2634 * DIV = FS + 2 2635 * best we can do is 200ns at 20Mhz, 2 cycles 2636 */ 2637 2638 GET_SBIC_myid(dev->sc_sbicp, fs); 2639 2640 fs = (fs >> 6) + 2; /* DIV */ 2641 2642 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2643 2644 if ( a < 2 ) 2645 a = 8; /* map to Cycles */ 2646 2647 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2648 } 2649 2650 int 2651 sbicfromscsiperiod(dev, p) 2652 struct sbic_softc *dev; 2653 int p; 2654 { 2655 unsigned fs, 2656 ret; 2657 2658 /* 2659 * Just the inverse of the above 2660 */ 2661 GET_SBIC_myid(dev->sc_sbicp, fs); 2662 2663 fs = (fs >> 6) + 2; /* DIV */ 2664 2665 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2666 2667 ret = p << 2; /* in ns units */ 2668 ret = ret / fs; /* in Cycles */ 2669 2670 if ( ret < sbic_min_period ) 2671 return(sbic_min_period); 2672 2673 /* 2674 * verify rounding 2675 */ 2676 if ( sbictoscsiperiod(dev, ret) < p ) 2677 ret++; 2678 2679 return( (ret >= 8) ? 0 : ret ); 2680 } 2681 2682 #ifdef DEBUG 2683 void 2684 sbictimeout(dev) 2685 struct sbic_softc *dev; 2686 { 2687 int s, 2688 asr; 2689 2690 s = splbio(); 2691 2692 if ( dev->sc_dmatimo ) { 2693 2694 if ( dev->sc_dmatimo > 1 ) { 2695 2696 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2697 dev->sc_dmatimo - 1); 2698 2699 GET_SBIC_asr(dev->sc_sbicp, asr); 2700 2701 if ( asr & SBIC_ASR_INT ) { 2702 /* 2703 * We need to service a missed IRQ 2704 */ 2705 sbicintr(dev); 2706 } else { 2707 (void) sbicabort(dev, "timeout"); 2708 splx(s); 2709 return; 2710 } 2711 } 2712 2713 dev->sc_dmatimo++; 2714 } 2715 2716 splx(s); 2717 2718 timeout((void *)sbictimeout, dev, 30 * hz); 2719 } 2720 #endif 2721
Indexes created Sun Sep 28 16:09:52 GMT 2025