sbic.c revision 1.7
1 /* $NetBSD: sbic.c,v 1.7 1998/07/04 22:18:32 jonathan Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 #include "opt_ddb.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/kernel.h> /* For hz */ 61 #include <sys/disklabel.h> 62 #include <sys/dkstat.h> 63 #include <sys/buf.h> 64 #include <dev/scsipi/scsi_all.h> 65 #include <dev/scsipi/scsipi_all.h> 66 #include <dev/scsipi/scsiconf.h> 67 #include <vm/vm.h> 68 #include <vm/vm_kern.h> 69 #include <vm/vm_page.h> 70 #include <vm/pmap.h> 71 #include <machine/pmap.h> 72 #include <mvme68k/mvme68k/isr.h> 73 #include <mvme68k/dev/dmavar.h> 74 #include <mvme68k/dev/sbicreg.h> 75 #include <mvme68k/dev/sbicvar.h> 76 77 78 /* 79 * Since I can't find this in any other header files 80 */ 81 #define SCSI_PHASE(reg) (reg&0x07) 82 83 /* 84 * SCSI delays 85 * In u-seconds, primarily for state changes on the SPC. 86 */ 87 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 88 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 89 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 90 91 /* 92 * Convenience macro for waiting for a particular sbic event 93 */ 94 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 95 96 extern u_int kvtop(); 97 98 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 99 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 100 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 101 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 102 int sbiccheckdmap __P((void *, u_long, u_long)); 103 u_char sbicselectbus __P((struct sbic_softc *)); 104 int sbicxfout __P((sbic_regmap_p, int, void *)); 105 int sbicxfin __P((sbic_regmap_p, int, void *)); 106 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 107 int sbictoscsiperiod __P((struct sbic_softc *, int)); 108 int sbicintr __P((struct sbic_softc *)); 109 int sbicpoll __P((struct sbic_softc *)); 110 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 111 int sbicmsgin __P((struct sbic_softc *)); 112 int sbicabort __P((struct sbic_softc *, char *)); 113 void sbicxfdone __P((struct sbic_softc *)); 114 void sbicerror __P((struct sbic_softc *,u_char)); 115 void sbicreset __P((struct sbic_softc *)); 116 void sbic_scsidone __P((struct sbic_acb *, int)); 117 void sbic_sched __P((struct sbic_softc *)); 118 void sbic_save_ptrs __P((struct sbic_softc *)); 119 void sbic_load_ptrs __P((struct sbic_softc *)); 120 121 /* 122 * Synch xfer parameters, and timing conversions 123 */ 124 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 125 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 126 int sbic_cmd_wait = SBIC_CMD_WAIT; 127 int sbic_data_wait = SBIC_DATA_WAIT; 128 int sbic_init_wait = SBIC_INIT_WAIT; 129 130 /* 131 * was broken before.. now if you want this you get it for all drives 132 * on sbic controllers. 133 */ 134 u_char sbic_inhibit_sync[8]; 135 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 136 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 137 int sbic_parallel_operations = 1; /* Allow command queues */ 138 139 /* 140 * Some useful stuff for debugging purposes 141 */ 142 #ifdef DEBUG 143 int sbicdma_ops = 0; /* total DMA operations */ 144 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 145 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 146 int sbicdma_saves = 0; 147 148 #define QPRINTF(a) if (sbic_debug > 1) printf a 149 150 int sbic_debug = 0; /* Debug all chip related things */ 151 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 152 int reselect_debug = 0; /* Debug all reselection related things */ 153 int report_sense = 0; /* Always print Sense information */ 154 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 155 156 void sbictimeout __P((struct sbic_softc *dev)); 157 158 #else 159 #define QPRINTF(a) /* */ 160 #endif 161 162 163 /* 164 * default minphys routine for sbic based controllers 165 */ 166 void 167 sbic_minphys(bp) 168 struct buf *bp; 169 { 170 /* 171 * No max transfer at this level. 172 */ 173 minphys(bp); 174 } 175 176 177 /* 178 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 179 */ 180 void 181 sbic_save_ptrs(dev) 182 struct sbic_softc *dev; 183 { 184 sbic_regmap_p regs; 185 struct sbic_acb* acb; 186 int count, 187 asr, 188 s; 189 190 /* 191 * Only need to save pointers if DMA was active... 192 */ 193 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 194 return; 195 196 regs = dev->sc_sbicp; 197 198 s = splbio(); 199 200 /* 201 * Wait until WD chip is idle 202 */ 203 do { 204 GET_SBIC_asr(regs, asr); 205 if( asr & SBIC_ASR_DBR ) { 206 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 207 splx(s); 208 return; 209 } 210 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 211 212 213 /* 214 * Save important state. 215 * must be done before dmastop 216 */ 217 acb = dev->sc_nexus; 218 acb->sc_dmacmd = dev->sc_dmacmd; 219 220 /* 221 * Fetch the residual count 222 */ 223 SBIC_TC_GET(regs, count); 224 225 /* 226 * Shut down DMA 227 */ 228 dev->sc_dmastop(dev); 229 230 /* 231 * No longer in DMA 232 */ 233 dev->sc_flags &= ~SBICF_INDMA; 234 235 /* 236 * Ensure the WD chip is back in polled I/O mode, with nothing to 237 * transfer. 238 */ 239 SBIC_TC_PUT(regs, 0); 240 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 241 242 /* 243 * Update current count... 244 */ 245 acb->sc_tcnt = count; 246 247 /* 248 * Work out how many bytes were actually transferred 249 */ 250 count = dev->sc_tcnt - count; 251 dev->sc_tcnt = acb->sc_tcnt; 252 253 /* 254 * Fixup partial xfers 255 */ 256 acb->sc_kv.dc_addr += count; 257 acb->sc_kv.dc_count -= count; 258 acb->sc_pa.dc_addr += count; 259 acb->sc_pa.dc_count -= count >> 1; 260 261 #ifdef DEBUG 262 if ( data_pointer_debug ) 263 printf("save at (%x,%x):%x\n", 264 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 265 sbicdma_saves++; 266 #endif 267 268 splx(s); 269 } 270 271 272 /* 273 * DOES NOT RESTART DMA!!! 274 */ 275 void 276 sbic_load_ptrs(dev) 277 struct sbic_softc *dev; 278 { 279 struct sbic_acb *acb = dev->sc_nexus; 280 int s; 281 282 if ( acb->sc_kv.dc_count == 0 ) { 283 /* 284 * No data to xfer 285 */ 286 return; 287 } 288 289 s = splbio(); 290 291 /* 292 * Reset the Scatter-Gather chain 293 */ 294 dev->sc_last = dev->sc_cur = &acb->sc_pa; 295 296 /* 297 * Restore the Transfer Count and DMA specific data 298 */ 299 dev->sc_tcnt = acb->sc_tcnt; 300 dev->sc_dmacmd = acb->sc_dmacmd; 301 302 #ifdef DEBUG 303 sbicdma_ops++; 304 #endif 305 306 /* 307 * Need to fixup new segment? 308 */ 309 if ( dev->sc_tcnt == 0 ) { 310 /* 311 * sc_tcnt == 0 implies end of segment 312 */ 313 char *vaddr, *paddr; 314 int count; 315 316 /* 317 * do kvm to pa mappings 318 */ 319 vaddr = acb->sc_kv.dc_addr; 320 paddr = acb->sc_pa.dc_addr = (char *) kvtop(vaddr); 321 322 for (count = (NBPG - ((int)vaddr & PGOFSET)); 323 count < acb->sc_kv.dc_count && 324 (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 325 count += NBPG) 326 ; /* Do nothing */ 327 328 /* 329 * If it's all contiguous... 330 */ 331 if ( count > acb->sc_kv.dc_count ) { 332 count = acb->sc_kv.dc_count; 333 #ifdef DEBUG 334 sbicdma_hits++; 335 #endif 336 } 337 #ifdef DEBUG 338 else 339 sbicdma_misses++; 340 #endif 341 342 acb->sc_tcnt = count; 343 acb->sc_pa.dc_count = count >> 1; 344 345 #ifdef DEBUG 346 if ( data_pointer_debug ) 347 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", acb->sc_kv.dc_addr, 348 acb->sc_kv.dc_count, 349 acb->sc_pa.dc_addr, 350 acb->sc_tcnt); 351 #endif 352 353 } 354 355 splx(s); 356 } 357 358 /* 359 * used by specific sbic controller 360 * 361 * it appears that the higher level code does nothing with LUN's 362 * so I will too. I could plug it in, however so could they 363 * in scsi_scsipi_cmd(). 364 */ 365 int 366 sbic_scsicmd(xs) 367 struct scsipi_xfer *xs; 368 { 369 struct scsipi_link *slp = xs->sc_link; 370 struct sbic_softc *dev = slp->adapter_softc; 371 struct sbic_acb *acb; 372 int flags = xs->flags, 373 s; 374 375 if ( flags & SCSI_DATA_UIO ) 376 panic("sbic: scsi data uio requested"); 377 378 if ( dev->sc_nexus && (flags & SCSI_POLL) ) 379 panic("sbic_scsicmd: busy"); 380 381 if ( slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target ) 382 return ESCAPE_NOT_SUPPORTED; 383 384 s = splbio(); 385 386 if ( (acb = dev->free_list.tqh_first) != NULL ) 387 TAILQ_REMOVE(&dev->free_list, acb, chain); 388 389 splx(s); 390 391 if ( acb == NULL ) { 392 #ifdef DEBUG 393 printf("sbic_scsicmd: unable to queue request for target %d\n", 394 slp->scsipi_scsi.target); 395 #ifdef DDB 396 Debugger(); 397 #endif 398 #endif 399 xs->error = XS_DRIVER_STUFFUP; 400 401 return(TRY_AGAIN_LATER); 402 } 403 404 if ( flags & SCSI_DATA_IN ) 405 acb->flags = ACB_ACTIVE | ACB_DATAIN; 406 else 407 acb->flags = ACB_ACTIVE; 408 409 acb->xs = xs; 410 acb->clen = xs->cmdlen; 411 acb->sc_kv.dc_addr = xs->data; 412 acb->sc_kv.dc_count = xs->datalen; 413 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; 414 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 415 416 if ( flags & SCSI_POLL ) { 417 /* 418 * This has major side effects -- it locks up the machine 419 */ 420 int stat; 421 422 s = splbio(); 423 424 dev->sc_flags |= SBICF_ICMD; 425 426 do { 427 /* 428 * If we already had a nexus, while away the time until idle... 429 * This is likely only to happen if a reselection occurs between 430 * here and our earlier check for ICMD && sc_nexus (which would 431 * have resulted in a panic() had it been true). 432 */ 433 while ( dev->sc_nexus ) 434 sbicpoll(dev); 435 436 /* 437 * Fix up the new nexus 438 */ 439 dev->sc_nexus = acb; 440 dev->sc_xs = xs; 441 dev->target = slp->scsipi_scsi.target; 442 dev->lun = slp->scsipi_scsi.lun; 443 444 stat = sbicicmd(dev, &acb->cmd, acb->clen, 445 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 446 447 } while ( dev->sc_nexus != acb ); 448 449 sbic_scsidone(acb, stat); 450 451 splx(s); 452 453 return(COMPLETE); 454 } 455 456 s = splbio(); 457 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 458 459 /* 460 * If nothing is active, try to start it now. 461 */ 462 if ( dev->sc_nexus == NULL ) 463 sbic_sched(dev); 464 465 splx(s); 466 467 return(SUCCESSFULLY_QUEUED); 468 } 469 470 /* 471 * attempt to start the next available command 472 */ 473 void 474 sbic_sched(dev) 475 struct sbic_softc *dev; 476 { 477 struct scsipi_xfer *xs; 478 struct scsipi_link *slp = NULL; /* Gag the compiler */ 479 struct sbic_acb *acb; 480 int flags, 481 stat; 482 483 /* 484 * XXXSCW 485 * I'll keep this test here, even though I can't see any obvious way 486 * in which sbic_sched() could be called with sc_nexus non NULL 487 */ 488 if ( dev->sc_nexus ) 489 return; /* a command is current active */ 490 491 /* 492 * Loop through the ready list looking for work to do... 493 */ 494 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 495 int i, j; 496 497 slp = acb->xs->sc_link; 498 i = slp->scsipi_scsi.target; 499 j = 1 << slp->scsipi_scsi.lun; 500 501 /* 502 * We've found a potential command, but is the target/lun busy? 503 */ 504 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 505 /* 506 * Nope, it's not busy, so we can use it. 507 */ 508 dev->sc_tinfo[i].lubusy |= j; 509 TAILQ_REMOVE(&dev->ready_list, acb, chain); 510 dev->sc_nexus = acb; 511 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 512 break; 513 } 514 } 515 516 if ( acb == NULL ) { 517 QPRINTF(("sbicsched: no work\n")); 518 return; /* did not find an available command */ 519 } 520 521 #ifdef DEBUG 522 if ( data_pointer_debug > 1 ) 523 printf("sbic_sched(%d,%d)\n", slp->scsipi_scsi.target, 524 slp->scsipi_scsi.lun); 525 #endif 526 527 dev->sc_xs = xs = acb->xs; 528 flags = xs->flags; 529 530 if ( flags & SCSI_RESET ) 531 sbicreset(dev); 532 533 dev->sc_stat[0] = -1; 534 dev->target = slp->scsipi_scsi.target; 535 dev->lun = slp->scsipi_scsi.lun; 536 537 if ( flags & SCSI_POLL || (!sbic_parallel_operations && 538 (sbicdmaok(dev, xs) == 0)) ) 539 stat = sbicicmd(dev, &acb->cmd, acb->clen, 540 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 541 else 542 if ( sbicgo(dev, xs) == 0 ) 543 return; 544 else 545 stat = dev->sc_stat[0]; 546 547 sbic_scsidone(acb, stat); 548 } 549 550 void 551 sbic_scsidone(acb, stat) 552 struct sbic_acb *acb; 553 int stat; 554 { 555 struct scsipi_xfer *xs = acb->xs; 556 struct scsipi_link *slp = xs->sc_link; 557 struct sbic_softc *dev = slp->adapter_softc; 558 int dosched = 0; 559 560 #ifdef DIAGNOSTIC 561 if ( acb == NULL || xs == NULL ) { 562 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); 563 #ifdef DDB 564 Debugger(); 565 #endif 566 return; 567 } 568 #endif 569 570 /* 571 * is this right? 572 */ 573 xs->status = stat; 574 575 #ifdef DEBUG 576 if ( data_pointer_debug > 1 ) 577 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", slp->scsipi_scsi.target, 578 slp->scsipi_scsi.lun, 579 dev->target, dev->lun, stat); 580 581 if ( xs->sc_link->scsipi_scsi.target == 582 dev->sc_link.scsipi_scsi.adapter_target ) 583 panic("target == hostid"); 584 #endif 585 586 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) == 0 ) { 587 588 if ( stat == SCSI_CHECK ) { 589 /* 590 * Schedule a REQUEST SENSE 591 */ 592 struct scsipi_sense *ss = (void *)&acb->cmd; 593 594 #ifdef DEBUG 595 if ( report_sense ) 596 printf("sbic_scsidone: autosense %02x targ %d lun %d", 597 acb->cmd.opcode, slp->scsipi_scsi.target, 598 slp->scsipi_scsi.lun); 599 #endif 600 601 bzero(ss, sizeof(*ss)); 602 603 ss->opcode = REQUEST_SENSE; 604 ss->byte2 = slp->scsipi_scsi.lun << 5; 605 ss->length = sizeof(struct scsipi_sense_data); 606 607 acb->clen = sizeof(*ss); 608 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 609 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 610 acb->pa_addr = (char *)kvtop(&xs->sense.scsi_sense); /* XXX check */ 611 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 612 613 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 614 615 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 616 ~(1 << slp->scsipi_scsi.lun); 617 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 618 619 if ( dev->sc_nexus == acb ) { 620 dev->sc_nexus = NULL; 621 dev->sc_xs = NULL; 622 sbic_sched(dev); 623 } 624 return; 625 } 626 } 627 628 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) != 0 ) { 629 630 xs->error = XS_SENSE; 631 632 #ifdef DEBUG 633 if (report_sense) 634 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 635 xs->sense.scsi_sense.extra_bytes[3]); 636 #endif 637 638 } else { 639 xs->resid = 0; /* XXXX */ 640 } 641 642 xs->flags |= ITSDONE; 643 644 /* 645 * Remove the ACB from whatever queue it's on. We have to do a bit of 646 * a hack to figure out which queue it's on. Note that it is *not* 647 * necessary to cdr down the ready queue, but we must cdr down the 648 * nexus queue and see if it's there, so we can mark the unit as no 649 * longer busy. This code is sickening, but it works. 650 */ 651 if ( acb == dev->sc_nexus ) { 652 653 dev->sc_nexus = NULL; 654 dev->sc_xs = NULL; 655 656 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 657 ~(1 << slp->scsipi_scsi.lun); 658 659 if ( dev->ready_list.tqh_first ) 660 dosched = 1; /* start next command */ 661 662 } else 663 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 664 665 TAILQ_REMOVE(&dev->ready_list, acb, chain); 666 667 } else { 668 669 register struct sbic_acb *a; 670 671 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 672 if ( a == acb ) { 673 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 674 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 675 ~(1 << slp->scsipi_scsi.lun); 676 break; 677 } 678 } 679 680 if ( a ) 681 ; 682 else if ( acb->chain.tqe_next ) { 683 TAILQ_REMOVE(&dev->ready_list, acb, chain); 684 } else { 685 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 686 #ifdef DDB 687 Debugger(); 688 #endif 689 } 690 } 691 692 /* 693 * Put it on the free list. 694 */ 695 acb->flags = ACB_FREE; 696 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 697 698 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 699 700 scsipi_done(xs); 701 702 if ( dosched ) 703 sbic_sched(dev); 704 } 705 706 int 707 sbicdmaok(dev, xs) 708 struct sbic_softc *dev; 709 struct scsipi_xfer *xs; 710 { 711 if ( sbic_no_dma || xs->datalen & 0x03 || (int)xs->data & 0x03) 712 return(0); 713 714 /* 715 * controller supports dma to any addresses? 716 */ 717 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 718 return(1); 719 720 /* 721 * this address is ok for dma? 722 */ 723 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 724 return(1); 725 726 return(0); 727 } 728 729 int 730 sbicwait(regs, until, timeo, line) 731 sbic_regmap_p regs; 732 u_char until; 733 int timeo; 734 int line; 735 { 736 u_char val; 737 738 if ( timeo == 0 ) 739 timeo = 1000000; /* some large value.. */ 740 741 GET_SBIC_asr(regs, val); 742 743 while ( (val & until) == 0 ) { 744 745 if ( timeo-- == 0 ) { 746 int csr; 747 GET_SBIC_csr(regs, csr); 748 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 749 #if defined(DDB) && defined(DEBUG) 750 Debugger(); 751 #endif 752 return(val); /* Maybe I should abort */ 753 break; 754 } 755 756 DELAY(1); 757 GET_SBIC_asr(regs, val); 758 } 759 760 return(val); 761 } 762 763 int 764 sbicabort(dev, where) 765 struct sbic_softc *dev; 766 char *where; 767 { 768 sbic_regmap_p regs = dev->sc_sbicp; 769 u_char csr, 770 asr; 771 772 GET_SBIC_asr(regs, asr); 773 GET_SBIC_csr(regs, csr); 774 775 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 776 dev->sc_dev.dv_xname, where, csr, asr); 777 778 /* 779 * Clean up chip itself 780 */ 781 if ( dev->sc_flags & SBICF_SELECTED ) { 782 783 while ( asr & SBIC_ASR_DBR ) { 784 /* 785 * sbic is jammed w/data. need to clear it 786 * But we don't know what direction it needs to go 787 */ 788 GET_SBIC_data(regs, asr); 789 printf("%s: abort %s: clearing data buffer 0x%02x\n", 790 dev->sc_dev.dv_xname, where, asr); 791 GET_SBIC_asr(regs, asr); 792 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 793 SET_SBIC_data(regs, asr); 794 GET_SBIC_asr(regs, asr); 795 } 796 797 WAIT_CIP(regs); 798 799 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 800 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 801 WAIT_CIP(regs); 802 803 GET_SBIC_asr(regs, asr); 804 805 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 806 /* 807 * ok, get more drastic.. 808 */ 809 printf("%s: sbicabort - asr %x, trying to reset\n", 810 dev->sc_dev.dv_xname, asr); 811 sbicreset(dev); 812 dev->sc_flags &= ~SBICF_SELECTED; 813 return SBIC_STATE_ERROR; 814 } 815 816 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 817 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 818 819 do { 820 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 821 GET_SBIC_asr(regs, asr); 822 GET_SBIC_csr (regs, csr); 823 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 824 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 825 (csr != SBIC_CSR_CMD_INVALID) ); 826 827 /* 828 * lets just hope it worked.. 829 */ 830 dev->sc_flags &= ~SBICF_SELECTED; 831 } 832 833 return SBIC_STATE_ERROR; 834 } 835 836 837 /* 838 * Initialize driver-private structures 839 */ 840 void 841 sbicinit(dev) 842 struct sbic_softc *dev; 843 { 844 u_int i; 845 846 extern u_long scsi_nosync; 847 extern int shift_nosync; 848 849 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 850 851 struct sbic_acb *acb; 852 853 TAILQ_INIT(&dev->ready_list); 854 TAILQ_INIT(&dev->nexus_list); 855 TAILQ_INIT(&dev->free_list); 856 857 dev->sc_nexus = NULL; 858 dev->sc_xs = NULL; 859 860 acb = dev->sc_acb; 861 bzero(acb, sizeof(dev->sc_acb)); 862 863 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 864 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 865 acb++; 866 } 867 868 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 869 870 #ifdef DEBUG 871 /* 872 * make sure timeout is really not needed 873 */ 874 timeout((void *)sbictimeout, dev, 30 * hz); 875 #endif 876 877 } else 878 panic("sbic: reinitializing driver!"); 879 880 dev->sc_flags |= SBICF_ALIVE; 881 dev->sc_flags &= ~SBICF_SELECTED; 882 883 /* 884 * initialize inhibit array 885 */ 886 if ( scsi_nosync ) { 887 888 u_int inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 889 890 shift_nosync += 8; 891 892 #ifdef DEBUG 893 if ( inhibit_sync ) 894 printf("%s: Inhibiting synchronous transfer %02x\n", 895 dev->sc_dev.dv_xname, inhibit_sync); 896 #endif 897 for (i = 0; i < 8; ++i) { 898 if ( inhibit_sync & (1 << i) ) 899 sbic_inhibit_sync[i] = 1; 900 } 901 } 902 903 sbicreset(dev); 904 } 905 906 void 907 sbicreset(dev) 908 struct sbic_softc *dev; 909 { 910 sbic_regmap_p regs = dev->sc_sbicp; 911 u_int my_id, 912 s; 913 u_char csr; 914 915 s = splbio(); 916 917 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 918 919 if (dev->sc_clkfreq < 110) 920 my_id |= SBIC_ID_FS_8_10; 921 else if (dev->sc_clkfreq < 160) 922 my_id |= SBIC_ID_FS_12_15; 923 else if (dev->sc_clkfreq < 210) 924 my_id |= SBIC_ID_FS_16_20; 925 926 SET_SBIC_myid(regs, my_id); 927 928 /* 929 * Reset the chip 930 */ 931 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 932 DELAY(25); 933 934 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 935 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 936 937 /* 938 * Set up various chip parameters 939 */ 940 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 941 942 /* 943 * don't allow Selection (SBIC_RID_ES) 944 * until we can handle target mode!! 945 */ 946 SET_SBIC_rselid(regs, SBIC_RID_ER); 947 948 /* 949 * Asynchronous for now 950 */ 951 SET_SBIC_syn(regs, 0); 952 953 /* 954 * Anything else was zeroed by reset 955 */ 956 splx(s); 957 958 dev->sc_flags &= ~SBICF_SELECTED; 959 } 960 961 void 962 sbicerror(dev, csr) 963 struct sbic_softc *dev; 964 u_char csr; 965 { 966 struct scsipi_xfer *xs = dev->sc_xs; 967 968 #ifdef DIAGNOSTIC 969 if ( xs == NULL ) 970 panic("sbicerror: dev->sc_xs == NULL"); 971 #endif 972 973 if ( xs->flags & SCSI_SILENT ) 974 return; 975 976 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 977 } 978 979 /* 980 * select the bus, return when selected or error. 981 * 982 * Returns the current CSR following selection and optionally MSG out phase. 983 * i.e. the returned CSR *should* indicate CMD phase... 984 * If the return value is 0, some error happened. 985 */ 986 u_char 987 sbicselectbus(dev) 988 struct sbic_softc *dev; 989 { 990 sbic_regmap_p regs = dev->sc_sbicp; 991 u_char target = dev->target, 992 lun = dev->lun, 993 asr, 994 csr, 995 id; 996 997 /* 998 * if we're already selected, return (XXXX panic maybe?) 999 */ 1000 if ( dev->sc_flags & SBICF_SELECTED ) 1001 return(0); 1002 1003 QPRINTF(("sbicselectbus %d: ", target)); 1004 1005 /* 1006 * issue select 1007 */ 1008 SET_SBIC_selid(regs, target); 1009 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 1010 1011 GET_SBIC_asr(regs, asr); 1012 1013 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1014 /* 1015 * This means we got ourselves reselected upon 1016 */ 1017 QPRINTF(("WD busy (reselect?)\n")); 1018 return 0; 1019 } 1020 1021 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1022 1023 /* 1024 * wait for select (merged from seperate function may need 1025 * cleanup) 1026 */ 1027 WAIT_CIP(regs); 1028 1029 do { 1030 1031 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1032 1033 if ( asr & SBIC_ASR_LCI ) { 1034 QPRINTF(("late LCI: asr %02x\n", asr)); 1035 return 0; 1036 } 1037 1038 /* 1039 * Clear interrupt 1040 */ 1041 GET_SBIC_csr (regs, csr); 1042 1043 QPRINTF(("%02x ", csr)); 1044 1045 /* 1046 * Reselected from under our feet? 1047 */ 1048 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 1049 QPRINTF(("got reselected, asr %02x\n", asr)); 1050 /* 1051 * We need to handle this now so we don't lock up later 1052 */ 1053 sbicnextstate(dev, csr, asr); 1054 1055 return 0; 1056 } 1057 1058 /* 1059 * Whoops! 1060 */ 1061 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1062 panic("sbicselectbus: target issued select!"); 1063 return 0; 1064 } 1065 1066 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1067 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1068 csr != SBIC_CSR_SEL_TIMEO); 1069 1070 /* 1071 * Anyone at home? 1072 */ 1073 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1074 dev->sc_xs->error = XS_SELTIMEOUT; 1075 QPRINTF(("Selection Timeout\n")); 1076 return 0; 1077 } 1078 1079 QPRINTF(("Selection Complete\n")); 1080 1081 /* 1082 * Assume we're now selected 1083 */ 1084 GET_SBIC_selid(regs, id); 1085 dev->target = id; 1086 dev->lun = lun; 1087 dev->sc_flags |= SBICF_SELECTED; 1088 1089 /* 1090 * Enable (or not) reselection 1091 * XXXSCW This is probably not necessary since we don't use use the 1092 * Select-and-Xfer-with-ATN command to initiate a selection... 1093 */ 1094 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1095 SET_SBIC_rselid (regs, 0); 1096 else 1097 SET_SBIC_rselid (regs, SBIC_RID_ER); 1098 1099 /* 1100 * We only really need to do anything when the target goes to MSG out 1101 * If the device ignored ATN, it's probably old and brain-dead, 1102 * but we'll try to support it anyhow. 1103 * If it doesn't support message out, it definately doesn't 1104 * support synchronous transfers, so no point in even asking... 1105 */ 1106 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1107 /* 1108 * Send identify message (SCSI-2 requires an identify msg) 1109 */ 1110 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1111 /* 1112 * Handle drives that don't want to be asked 1113 * whether to go sync at all. 1114 */ 1115 dev->sc_sync[id].offset = 0; 1116 dev->sc_sync[id].period = sbic_min_period; 1117 dev->sc_sync[id].state = SYNC_DONE; 1118 } 1119 1120 /* 1121 * Do we need to negotiate Synchronous Xfers for this target? 1122 */ 1123 if ( dev->sc_sync[id].state != SYNC_START ) { 1124 /* 1125 * Nope, we've already negotiated. 1126 * Now see if we should allow the target to disconnect/reselect... 1127 */ 1128 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 1129 !sbic_enable_reselect ) 1130 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1131 else 1132 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1133 1134 } else { 1135 /* 1136 * try to initiate a sync transfer. 1137 * So compose the sync message we're going 1138 * to send to the target 1139 */ 1140 #ifdef DEBUG 1141 if ( sync_debug ) 1142 printf("\nSending sync request to target %d ... ", id); 1143 #endif 1144 /* 1145 * setup scsi message sync message request 1146 */ 1147 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1148 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1149 dev->sc_msg[2] = 3; 1150 dev->sc_msg[3] = MSG_SYNC_REQ; 1151 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1152 dev->sc_msg[5] = sbic_max_offset; 1153 1154 sbicxfout(regs, 6, dev->sc_msg); 1155 1156 dev->sc_sync[id].state = SYNC_SENT; 1157 #ifdef DEBUG 1158 if ( sync_debug ) 1159 printf ("sent\n"); 1160 #endif 1161 } 1162 1163 /* 1164 * There's one interrupt still to come: the change to CMD phase... 1165 */ 1166 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1167 GET_SBIC_csr(regs, csr); 1168 } 1169 1170 /* 1171 * set sync or async 1172 */ 1173 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1174 #ifdef DEBUG 1175 if ( sync_debug ) 1176 printf("select(%d): sync reg = 0x%02x\n", target, 1177 SBIC_SYN(dev->sc_sync[target].offset, 1178 dev->sc_sync[target].period)); 1179 #endif 1180 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1181 dev->sc_sync[target].period)); 1182 } else { 1183 #ifdef DEBUG 1184 if ( sync_debug ) 1185 printf("select(%d): sync reg = 0x%02x\n", target, 1186 SBIC_SYN(0,sbic_min_period)); 1187 #endif 1188 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1189 } 1190 1191 return csr; 1192 } 1193 1194 /* 1195 * Information Transfer *to* a Scsi Target. 1196 * 1197 * Note: Don't expect there to be an interrupt immediately after all 1198 * the data is transferred out. The WD spec sheet says that the Transfer- 1199 * Info command for non-MSG_IN phases only completes when the target 1200 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1201 * 1202 * This can have a nasty effect on commands which take a relatively long 1203 * time to complete, for example a START/STOP unit command may remain in 1204 * CMD phase until the disk has spun up. Only then will the target change 1205 * to STATUS phase. This is really only a problem for immediate commands 1206 * since we don't allow disconnection for them (yet). 1207 */ 1208 int 1209 sbicxfout(regs, len, bp) 1210 sbic_regmap_p regs; 1211 int len; 1212 void *bp; 1213 { 1214 int wait = sbic_data_wait; 1215 u_char asr, 1216 *buf = bp; 1217 1218 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1219 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1220 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1221 1222 /* 1223 * sigh.. WD-PROTO strikes again.. sending the command in one go 1224 * causes the chip to lock up if talking to certain (misbehaving?) 1225 * targets. Anyway, this procedure should work for all targets, but 1226 * it's slightly slower due to the overhead 1227 */ 1228 WAIT_CIP (regs); 1229 1230 SBIC_TC_PUT (regs, 0); 1231 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1232 SBIC_TC_PUT (regs, (unsigned)len); 1233 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1234 1235 /* 1236 * Loop for each byte transferred 1237 */ 1238 do { 1239 1240 GET_SBIC_asr (regs, asr); 1241 1242 if ( asr & SBIC_ASR_DBR ) { 1243 if ( len ) { 1244 SET_SBIC_data (regs, *buf); 1245 buf++; 1246 len--; 1247 } else { 1248 SET_SBIC_data (regs, 0); 1249 } 1250 wait = sbic_data_wait; 1251 } 1252 1253 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1254 1255 #ifdef DEBUG 1256 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1257 #endif 1258 1259 /* 1260 * Normally, an interrupt will be pending when this routing returns. 1261 */ 1262 return(len); 1263 } 1264 1265 /* 1266 * Information Transfer *from* a Scsi Target 1267 * returns # bytes left to read 1268 */ 1269 int 1270 sbicxfin(regs, len, bp) 1271 sbic_regmap_p regs; 1272 int len; 1273 void *bp; 1274 { 1275 int wait = sbic_data_wait; 1276 u_char *buf = bp; 1277 u_char asr; 1278 #ifdef DEBUG 1279 u_char *obp = bp; 1280 #endif 1281 1282 WAIT_CIP (regs); 1283 1284 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1285 SBIC_TC_PUT (regs, (unsigned)len); 1286 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1287 1288 /* 1289 * Loop for each byte transferred 1290 */ 1291 do { 1292 1293 GET_SBIC_asr (regs, asr); 1294 1295 if ( asr & SBIC_ASR_DBR ) { 1296 if ( len ) { 1297 GET_SBIC_data (regs, *buf); 1298 buf++; 1299 len--; 1300 } else { 1301 u_char foo; 1302 GET_SBIC_data (regs, foo); 1303 } 1304 wait = sbic_data_wait; 1305 } 1306 1307 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1308 1309 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1310 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1311 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1312 1313 SBIC_TC_PUT (regs, 0); 1314 1315 /* 1316 * this leaves with one csr to be read 1317 */ 1318 return len; 1319 } 1320 1321 /* 1322 * SCSI 'immediate' command: issue a command to some SCSI device 1323 * and get back an 'immediate' response (i.e., do programmed xfer 1324 * to get the response data). 'cbuf' is a buffer containing a scsi 1325 * command of length clen bytes. 'buf' is a buffer of length 'len' 1326 * bytes for data. The transfer direction is determined by the device 1327 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1328 * command must supply no data. 1329 * 1330 * Note that although this routine looks like it can handle disconnect/ 1331 * reselect, the fact is that it can't. There is still some work to be 1332 * done to clean this lot up. 1333 */ 1334 int 1335 sbicicmd(dev, cbuf, clen, buf, len) 1336 struct sbic_softc *dev; 1337 void *cbuf, 1338 *buf; 1339 int clen, 1340 len; 1341 { 1342 sbic_regmap_p regs = dev->sc_sbicp; 1343 struct sbic_acb *acb = dev->sc_nexus; 1344 u_char csr, 1345 asr; 1346 int still_busy = SBIC_STATE_RUNNING; 1347 #ifdef DEBUG 1348 int counter = 0; 1349 #endif 1350 1351 /* 1352 * Make sure pointers are OK 1353 */ 1354 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1355 dev->sc_tcnt = acb->sc_tcnt = 0; 1356 1357 acb->sc_dmacmd = 0; 1358 acb->sc_pa.dc_count = 0; /* No DMA */ 1359 acb->sc_kv.dc_addr = buf; 1360 acb->sc_kv.dc_count = len; 1361 1362 #ifdef DEBUG 1363 if ( data_pointer_debug > 1 ) 1364 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1365 #endif 1366 1367 /* 1368 * set the sbic into non-DMA mode 1369 */ 1370 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1371 1372 dev->sc_stat[0] = 0xff; 1373 dev->sc_msg[0] = 0xff; 1374 1375 /* 1376 * We're stealing the SCSI bus 1377 */ 1378 dev->sc_flags |= SBICF_ICMD; 1379 1380 do { 1381 GET_SBIC_asr (regs, asr); 1382 1383 /* 1384 * select the SCSI bus (it's an error if bus isn't free) 1385 */ 1386 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1387 still_busy != SBIC_STATE_DISCONNECT ) { 1388 if ( (csr = sbicselectbus(dev)) == 0 ) { 1389 dev->sc_flags &= ~SBICF_ICMD; 1390 return(-1); 1391 } 1392 } else 1393 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1394 GET_SBIC_csr(regs, csr); 1395 else 1396 csr = 0; 1397 1398 if ( csr ) { 1399 1400 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1401 1402 switch ( csr ) { 1403 1404 case SBIC_CSR_S_XFERRED: 1405 case SBIC_CSR_DISC: 1406 case SBIC_CSR_DISC_1: 1407 { 1408 u_char phase; 1409 1410 dev->sc_flags &= ~SBICF_SELECTED; 1411 GET_SBIC_cmd_phase (regs, phase); 1412 1413 if ( phase == 0x60 ) { 1414 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1415 still_busy = SBIC_STATE_DONE; /* done */ 1416 } else { 1417 #ifdef DEBUG 1418 if ( reselect_debug > 1 ) 1419 printf("sbicicmd: handling disconnect\n"); 1420 #endif 1421 still_busy = SBIC_STATE_DISCONNECT; 1422 } 1423 } 1424 break; 1425 1426 case SBIC_CSR_XFERRED | CMD_PHASE: 1427 case SBIC_CSR_MIS | CMD_PHASE: 1428 case SBIC_CSR_MIS_1 | CMD_PHASE: 1429 case SBIC_CSR_MIS_2 | CMD_PHASE: 1430 { 1431 if ( sbicxfout(regs, clen, cbuf) ) 1432 still_busy = sbicabort(dev, "icmd sending cmd"); 1433 } 1434 break; 1435 1436 case SBIC_CSR_XFERRED | STATUS_PHASE: 1437 case SBIC_CSR_MIS | STATUS_PHASE: 1438 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1439 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1440 { 1441 /* 1442 * The sbic does the status/cmd-complete reading ok, 1443 * so do this with its hi-level commands. 1444 */ 1445 #ifdef DEBUG 1446 if ( sbic_debug ) 1447 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1448 #endif 1449 SET_SBIC_cmd_phase(regs, 0x46); 1450 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1451 } 1452 break; 1453 1454 default: 1455 { 1456 still_busy = sbicnextstate(dev, csr, asr); 1457 } 1458 break; 1459 } 1460 1461 /* 1462 * make sure the last command was taken, 1463 * ie. we're not hunting after an ignored command.. 1464 */ 1465 GET_SBIC_asr(regs, asr); 1466 1467 /* 1468 * tapes may take a loooong time.. 1469 */ 1470 while (asr & SBIC_ASR_BSY ) { 1471 1472 if ( asr & SBIC_ASR_DBR ) { 1473 int i; 1474 1475 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1476 #ifdef DDB 1477 Debugger(); 1478 #endif 1479 /* 1480 * SBIC is jammed 1481 * DUNNO which direction 1482 * Try old direction 1483 */ 1484 GET_SBIC_data(regs, i); 1485 GET_SBIC_asr(regs, asr); 1486 1487 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1488 SET_SBIC_data(regs, i); 1489 } 1490 1491 GET_SBIC_asr(regs, asr); 1492 } 1493 } 1494 1495 /* 1496 * wait for last command to complete 1497 */ 1498 if ( asr & SBIC_ASR_LCI ) { 1499 printf("sbicicmd: last command ignored\n"); 1500 } 1501 else 1502 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1503 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1504 1505 /* 1506 * do it again 1507 */ 1508 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1509 1510 /* 1511 * Sometimes we need to do an extra read of the CSR 1512 */ 1513 GET_SBIC_csr(regs, csr); 1514 1515 #ifdef DEBUG 1516 if ( data_pointer_debug > 1 ) 1517 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1518 acb->sc_kv.dc_count, 1519 dev->sc_stat[0]); 1520 #endif 1521 1522 dev->sc_flags &= ~SBICF_ICMD; 1523 1524 return(dev->sc_stat[0]); 1525 } 1526 1527 /* 1528 * Finish SCSI xfer command: After the completion interrupt from 1529 * a read/write operation, sequence through the final phases in 1530 * programmed i/o. This routine is a lot like sbicicmd except we 1531 * skip (and don't allow) the select, cmd out and data in/out phases. 1532 */ 1533 void 1534 sbicxfdone(dev) 1535 struct sbic_softc *dev; 1536 { 1537 sbic_regmap_p regs = dev->sc_sbicp; 1538 u_char phase, 1539 csr; 1540 int s; 1541 1542 QPRINTF(("{")); 1543 s = splbio(); 1544 1545 /* 1546 * have the sbic complete on its own 1547 */ 1548 SBIC_TC_PUT(regs, 0); 1549 SET_SBIC_cmd_phase(regs, 0x46); 1550 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1551 1552 do { 1553 1554 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1555 GET_SBIC_csr (regs, csr); 1556 QPRINTF(("%02x:", csr)); 1557 1558 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1559 (csr != SBIC_CSR_S_XFERRED)); 1560 1561 dev->sc_flags &= ~SBICF_SELECTED; 1562 1563 GET_SBIC_cmd_phase (regs, phase); 1564 QPRINTF(("}%02x", phase)); 1565 1566 if ( phase == 0x60 ) 1567 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1568 else 1569 sbicerror(dev, csr); 1570 1571 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1572 1573 splx(s); 1574 } 1575 1576 /* 1577 * No DMA chains 1578 */ 1579 int 1580 sbicgo(dev, xs) 1581 struct sbic_softc *dev; 1582 struct scsipi_xfer *xs; 1583 { 1584 struct sbic_acb *acb = dev->sc_nexus; 1585 sbic_regmap_p regs = dev->sc_sbicp; 1586 int i, 1587 dmaflags, 1588 count, 1589 usedma; 1590 u_char csr, 1591 asr, 1592 *addr; 1593 1594 dev->target = xs->sc_link->scsipi_scsi.target; 1595 dev->lun = xs->sc_link->scsipi_scsi.lun; 1596 1597 usedma = sbicdmaok(dev, xs); 1598 1599 #ifdef DEBUG 1600 if ( data_pointer_debug > 1 ) 1601 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1602 #endif 1603 1604 /* 1605 * select the SCSI bus (it's an error if bus isn't free) 1606 */ 1607 if ( (csr = sbicselectbus(dev)) == 0 ) 1608 return(0); /* Not done: needs to be rescheduled */ 1609 1610 dev->sc_stat[0] = 0xff; 1611 1612 /* 1613 * Calculate DMA chains now 1614 */ 1615 if ( acb->flags & ACB_DATAIN ) 1616 dmaflags = DMAGO_READ; 1617 else 1618 dmaflags = 0; 1619 1620 addr = acb->sc_kv.dc_addr; 1621 count = acb->sc_kv.dc_count; 1622 1623 if ( count && ((char *)kvtop(addr) != acb->sc_pa.dc_addr) ) { 1624 printf("sbic: DMA buffer mapping changed %x->%x\n", 1625 acb->sc_pa.dc_addr, kvtop(addr)); 1626 #ifdef DDB 1627 Debugger(); 1628 #endif 1629 } 1630 1631 #ifdef DEBUG 1632 ++sbicdma_ops; /* count total DMA operations */ 1633 #endif 1634 1635 /* 1636 * Allocate the DMA chain 1637 * Mark end of segment... 1638 */ 1639 acb->sc_tcnt = dev->sc_tcnt = 0; 1640 acb->sc_pa.dc_count = 0; 1641 1642 sbic_load_ptrs(dev); 1643 1644 /* 1645 * Enable interrupts but don't do any DMA 1646 * enintr() also enables interrupts for the sbic 1647 */ 1648 dev->sc_enintr(dev); 1649 1650 if ( usedma ) { 1651 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1652 acb->sc_pa.dc_count, dmaflags); 1653 #ifdef DEBUG 1654 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1655 #endif 1656 } else 1657 dev->sc_dmacmd = 0; /* Don't use DMA */ 1658 1659 acb->sc_dmacmd = dev->sc_dmacmd; 1660 1661 #ifdef DEBUG 1662 if ( data_pointer_debug > 1 ) { 1663 printf("sbicgo dmago:%d(%x:%x) dmacmd=0x%02x\n", dev->target, 1664 dev->sc_cur->dc_addr, 1665 dev->sc_tcnt, 1666 dev->sc_dmacmd); 1667 } 1668 #endif 1669 1670 /* 1671 * Lets cycle a while then let the interrupt handler take over. 1672 */ 1673 GET_SBIC_asr(regs, asr); 1674 1675 do { 1676 1677 QPRINTF(("go ")); 1678 1679 /* 1680 * Handle the new phase 1681 */ 1682 i = sbicnextstate(dev, csr, asr); 1683 #if 0 1684 WAIT_CIP(regs); 1685 #endif 1686 if ( i == SBIC_STATE_RUNNING ) { 1687 GET_SBIC_asr(regs, asr); 1688 1689 if ( asr & SBIC_ASR_LCI ) 1690 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1691 1692 if ( asr & SBIC_ASR_INT ) 1693 GET_SBIC_csr(regs, csr); 1694 } 1695 1696 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1697 1698 if ( i == SBIC_STATE_DONE ) { 1699 if ( dev->sc_stat[0] == 0xff ) 1700 #if 0 1701 printf("sbicgo: done & stat = 0xff\n"); 1702 #else 1703 ; 1704 #endif 1705 else 1706 return 1; /* Did we really finish that fast? */ 1707 } 1708 1709 return 0; 1710 } 1711 1712 1713 int 1714 sbicintr(dev) 1715 struct sbic_softc *dev; 1716 { 1717 sbic_regmap_p regs = dev->sc_sbicp; 1718 u_char asr, 1719 csr; 1720 int i; 1721 1722 /* 1723 * pending interrupt? 1724 */ 1725 GET_SBIC_asr (regs, asr); 1726 if ( (asr & SBIC_ASR_INT) == 0 ) 1727 return(0); 1728 1729 GET_SBIC_csr(regs, csr); 1730 1731 do { 1732 1733 QPRINTF(("intr[0x%x]", csr)); 1734 1735 i = sbicnextstate(dev, csr, asr); 1736 #if 0 1737 WAIT_CIP(regs); 1738 #endif 1739 if ( i == SBIC_STATE_RUNNING ) { 1740 GET_SBIC_asr(regs, asr); 1741 1742 if ( asr & SBIC_ASR_LCI ) 1743 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1744 1745 if ( asr & SBIC_ASR_INT ) 1746 GET_SBIC_csr(regs, csr); 1747 } 1748 1749 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1750 1751 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1752 1753 return(1); 1754 } 1755 1756 /* 1757 * Run commands and wait for disconnect. 1758 * This is only ever called when a command is in progress, when we 1759 * want to busy wait for it to finish. 1760 */ 1761 int 1762 sbicpoll(dev) 1763 struct sbic_softc *dev; 1764 { 1765 sbic_regmap_p regs = dev->sc_sbicp; 1766 u_char asr, 1767 csr; 1768 int i; 1769 1770 /* 1771 * Wait for the next interrupt 1772 */ 1773 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1774 1775 do { 1776 GET_SBIC_asr (regs, asr); 1777 1778 if ( asr & SBIC_ASR_INT ) 1779 GET_SBIC_csr(regs, csr); 1780 1781 QPRINTF(("poll[0x%x]", csr)); 1782 1783 /* 1784 * Handle it 1785 */ 1786 i = sbicnextstate(dev, csr, asr); 1787 1788 WAIT_CIP(regs); 1789 GET_SBIC_asr(regs, asr); 1790 1791 /* 1792 * tapes may take a loooong time.. 1793 */ 1794 while ( asr & SBIC_ASR_BSY ) { 1795 u_char z = 0; 1796 1797 if ( asr & SBIC_ASR_DBR ) { 1798 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1799 #ifdef DDB 1800 Debugger(); 1801 #endif 1802 /* 1803 * SBIC is jammed 1804 * DUNNO which direction 1805 * Try old direction 1806 */ 1807 GET_SBIC_data(regs, z); 1808 GET_SBIC_asr(regs, asr); 1809 1810 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1811 SET_SBIC_data(regs, z); 1812 } 1813 1814 GET_SBIC_asr(regs, asr); 1815 } 1816 1817 if ( asr & SBIC_ASR_LCI ) 1818 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1819 else 1820 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1821 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1822 1823 } while ( i == SBIC_STATE_RUNNING ); 1824 1825 return(1); 1826 } 1827 1828 /* 1829 * Handle a single msgin 1830 */ 1831 int 1832 sbicmsgin(dev) 1833 struct sbic_softc *dev; 1834 { 1835 sbic_regmap_p regs = dev->sc_sbicp; 1836 int recvlen = 1; 1837 u_char asr, 1838 csr, 1839 *tmpaddr, 1840 *msgaddr; 1841 1842 tmpaddr = msgaddr = dev->sc_msg; 1843 1844 tmpaddr[0] = 0xff; 1845 tmpaddr[1] = 0xff; 1846 1847 GET_SBIC_asr(regs, asr); 1848 1849 #ifdef DEBUG 1850 if ( reselect_debug > 1 ) 1851 printf("sbicmsgin asr=%02x\n", asr); 1852 #endif 1853 1854 GET_SBIC_selid (regs, csr); 1855 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1856 1857 SBIC_TC_PUT(regs, 0); 1858 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1859 1860 do { 1861 while( recvlen-- ) { 1862 1863 /* 1864 * Fetch the next byte of the message 1865 */ 1866 RECV_BYTE(regs, *tmpaddr); 1867 1868 /* 1869 * get the command completion interrupt, or we 1870 * can't send a new command (LCI) 1871 */ 1872 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1873 GET_SBIC_csr(regs, csr); 1874 1875 #ifdef DEBUG 1876 if ( reselect_debug > 1 ) 1877 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1878 #endif 1879 1880 tmpaddr++; 1881 1882 if ( recvlen ) { 1883 /* 1884 * Clear ACK, and wait for the interrupt for the next byte 1885 */ 1886 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1887 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1888 GET_SBIC_csr(regs, csr); 1889 } 1890 } 1891 1892 if ( msgaddr[0] == 0xff ) { 1893 printf("sbicmsgin: sbic swallowed our message\n"); 1894 break; 1895 } 1896 1897 #ifdef DEBUG 1898 if ( sync_debug ) { 1899 GET_SBIC_asr(regs, asr); 1900 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1901 } 1902 #endif 1903 /* 1904 * test whether this is a reply to our sync 1905 * request 1906 */ 1907 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1908 1909 /* 1910 * Got IFFY msg -- ack it 1911 */ 1912 QPRINTF(("IFFY")); 1913 1914 } else 1915 if ( msgaddr[0] == MSG_REJECT && 1916 dev->sc_sync[dev->target].state == SYNC_SENT) { 1917 1918 /* 1919 * Target probably rejected our Sync negotiation. 1920 */ 1921 QPRINTF(("REJECT of SYN")); 1922 1923 #ifdef DEBUG 1924 if ( sync_debug ) 1925 printf("target %d rejected sync, going async\n", dev->target); 1926 #endif 1927 1928 dev->sc_sync[dev->target].period = sbic_min_period; 1929 dev->sc_sync[dev->target].offset = 0; 1930 dev->sc_sync[dev->target].state = SYNC_DONE; 1931 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1932 dev->sc_sync[dev->target].period)); 1933 1934 } else 1935 if ( msgaddr[0] == MSG_REJECT ) { 1936 1937 /* 1938 * we'll never REJECt a REJECT message.. 1939 */ 1940 QPRINTF(("REJECT")); 1941 1942 } else 1943 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1944 1945 /* 1946 * don't reject this either. 1947 */ 1948 QPRINTF(("MSG_SAVE_DATA_PTR")); 1949 1950 } else 1951 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1952 1953 /* 1954 * don't reject this either. 1955 */ 1956 QPRINTF(("MSG_RESTORE_PTR")); 1957 1958 } else 1959 if ( msgaddr[0] == MSG_DISCONNECT ) { 1960 1961 /* 1962 * Target is disconnecting... 1963 */ 1964 QPRINTF(("DISCONNECT")); 1965 1966 #ifdef DEBUG 1967 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1968 printf("sbicmsgin: got disconnect msg %s\n", 1969 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1970 #endif 1971 1972 if ( dev->sc_flags & SBICF_ICMD ) { 1973 /* 1974 * We're in immediate mode. Prevent disconnects. 1975 * prepare to reject the message, NACK 1976 */ 1977 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1978 WAIT_CIP(regs); 1979 } 1980 1981 } else 1982 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1983 1984 /* 1985 * !! KLUDGE ALERT !! quite a few drives don't seem to 1986 * really like the current way of sending the 1987 * sync-handshake together with the ident-message, and 1988 * they react by sending command-complete and 1989 * disconnecting right after returning the valid sync 1990 * handshake. So, all I can do is reselect the drive, 1991 * and hope it won't disconnect again. I don't think 1992 * this is valid behavior, but I can't help fixing a 1993 * problem that apparently exists. 1994 * 1995 * Note: we should not get here on `normal' command 1996 * completion, as that condition is handled by the 1997 * high-level sel&xfer resume command used to walk 1998 * thru status/cc-phase. 1999 */ 2000 QPRINTF(("CMD_COMPLETE")); 2001 2002 #ifdef DEBUG 2003 if ( sync_debug ) 2004 printf ("GOT MSG %d! target %d acting weird.." 2005 " waiting for disconnect...\n", msgaddr[0], dev->target); 2006 #endif 2007 2008 /* 2009 * Check to see if sbic is handling this 2010 */ 2011 GET_SBIC_asr(regs, asr); 2012 2013 /* 2014 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 2015 */ 2016 if ( asr & SBIC_ASR_BSY ) 2017 return SBIC_STATE_RUNNING; 2018 2019 /* 2020 * Let's try this: Assume it works and set status to 00 2021 */ 2022 dev->sc_stat[0] = 0; 2023 2024 } else 2025 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 2026 2027 /* 2028 * Target is sending us an extended message. We'll assume it's 2029 * the response to our Sync. negotiation. 2030 */ 2031 QPRINTF(("ExtMSG\n")); 2032 2033 /* 2034 * Read in whole extended message. First, negate ACK to accept 2035 * the MSG_EXT_MESSAGE byte... 2036 */ 2037 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2038 2039 /* 2040 * Wait for the interrupt for the next byte (length) 2041 */ 2042 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2043 GET_SBIC_csr(regs, csr); 2044 2045 #ifdef DEBUG 2046 QPRINTF(("CLR ACK csr %02x\n", csr)); 2047 #endif 2048 2049 /* 2050 * Read the length byte 2051 */ 2052 RECV_BYTE(regs, *tmpaddr); 2053 2054 /* 2055 * Wait for command completion IRQ 2056 */ 2057 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2058 GET_SBIC_csr(regs, csr); 2059 2060 /* 2061 * Reload the loop counter 2062 */ 2063 recvlen = *tmpaddr++; 2064 2065 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2066 2067 } else 2068 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2069 msgaddr[2] == MSG_SYNC_REQ ) { 2070 2071 /* 2072 * We've received the complete Extended Message Sync. Request... 2073 */ 2074 QPRINTF(("SYN")); 2075 2076 /* 2077 * Compute the required Transfer Period for the WD chip... 2078 */ 2079 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2080 dev->sc_sync[dev->target].offset = msgaddr[4]; 2081 dev->sc_sync[dev->target].state = SYNC_DONE; 2082 2083 /* 2084 * Put the WD chip in synchronous mode 2085 */ 2086 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2087 dev->sc_sync[dev->target].period)); 2088 #ifdef DEBUG 2089 if ( sync_debug ) 2090 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2091 SBIC_SYN(dev->sc_sync[dev->target].offset, 2092 dev->sc_sync[dev->target].period)); 2093 #endif 2094 2095 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2096 dev->sc_dev.dv_xname, dev->target, 2097 msgaddr[3] * 4, msgaddr[4]); 2098 2099 } else { 2100 2101 /* 2102 * We don't support whatever this message is... 2103 */ 2104 #ifdef DEBUG 2105 if ( sbic_debug || sync_debug ) 2106 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2107 #endif 2108 2109 /* 2110 * prepare to reject the message, NACK 2111 */ 2112 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2113 WAIT_CIP(regs); 2114 } 2115 2116 /* 2117 * Negate ACK to complete the transfer 2118 */ 2119 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2120 2121 /* 2122 * Wait for the interrupt for the next byte, or phase change. 2123 * Only read the CSR if we have more data to transfer. 2124 * XXXSCW: We should really verify that we're still in MSG IN phase 2125 * before blindly going back around this loop, but that would mean 2126 * we read the CSR... <sigh> 2127 */ 2128 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2129 if ( recvlen > 0 ) 2130 GET_SBIC_csr(regs, csr); 2131 2132 } while ( recvlen > 0 ); 2133 2134 /* 2135 * Should still have one CSR to read 2136 */ 2137 return SBIC_STATE_RUNNING; 2138 } 2139 2140 2141 /* 2142 * sbicnextstate() 2143 * return: 2144 * SBIC_STATE_DONE == done 2145 * SBIC_STATE_RUNNING == working 2146 * SBIC_STATE_DISCONNECT == disconnected 2147 * SBIC_STATE_ERROR == error 2148 */ 2149 int 2150 sbicnextstate(dev, csr, asr) 2151 struct sbic_softc *dev; 2152 u_char csr, 2153 asr; 2154 { 2155 sbic_regmap_p regs = dev->sc_sbicp; 2156 struct sbic_acb *acb = dev->sc_nexus; 2157 2158 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2159 2160 switch (csr) { 2161 2162 case SBIC_CSR_XFERRED | CMD_PHASE: 2163 case SBIC_CSR_MIS | CMD_PHASE: 2164 case SBIC_CSR_MIS_1 | CMD_PHASE: 2165 case SBIC_CSR_MIS_2 | CMD_PHASE: 2166 { 2167 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2168 goto abort; 2169 } 2170 break; 2171 2172 case SBIC_CSR_XFERRED | STATUS_PHASE: 2173 case SBIC_CSR_MIS | STATUS_PHASE: 2174 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2175 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2176 { 2177 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2178 2179 /* 2180 * this should be the normal i/o completion case. 2181 * get the status & cmd complete msg then let the 2182 * device driver look at what happened. 2183 */ 2184 sbicxfdone(dev); 2185 2186 #ifdef DEBUG 2187 dev->sc_dmatimo = 0; 2188 if ( data_pointer_debug > 1 ) 2189 printf("next dmastop: %d(%x:%x)\n", dev->target, 2190 dev->sc_cur->dc_addr, 2191 dev->sc_tcnt); 2192 #endif 2193 /* 2194 * Stop the DMA chip 2195 */ 2196 dev->sc_dmastop(dev); 2197 2198 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2199 2200 /* 2201 * Indicate to the upper layers that the command is done 2202 */ 2203 sbic_scsidone(acb, dev->sc_stat[0]); 2204 2205 return SBIC_STATE_DONE; 2206 } 2207 2208 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2209 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2210 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2211 case SBIC_CSR_MIS | DATA_IN_PHASE: 2212 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2213 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2214 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2215 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2216 { 2217 /* 2218 * Verify that we expected to transfer data... 2219 */ 2220 if ( acb->sc_kv.dc_count <= 0 ) { 2221 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2222 acb->sc_kv.dc_count, asr, csr); 2223 goto abort; 2224 } 2225 2226 /* 2227 * Should we transfer using PIO or DMA ? 2228 */ 2229 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2230 acb->sc_dmacmd == 0 ) { 2231 2232 /* 2233 * Do PIO transfer 2234 */ 2235 int i; 2236 2237 #ifdef DEBUG 2238 if ( data_pointer_debug > 1 ) 2239 printf("next PIO: %d(%x:%x)\n", dev->target, 2240 acb->sc_kv.dc_addr, 2241 acb->sc_kv.dc_count); 2242 #endif 2243 2244 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2245 /* 2246 * data in 2247 */ 2248 i = sbicxfin(regs, acb->sc_kv.dc_count, 2249 acb->sc_kv.dc_addr); 2250 else 2251 /* 2252 * data out 2253 */ 2254 i = sbicxfout(regs, acb->sc_kv.dc_count, 2255 acb->sc_kv.dc_addr); 2256 2257 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2258 acb->sc_kv.dc_count = i; 2259 2260 /* 2261 * Update current count... 2262 */ 2263 acb->sc_tcnt = dev->sc_tcnt = i; 2264 2265 dev->sc_flags &= ~SBICF_INDMA; 2266 2267 } else { 2268 2269 /* 2270 * Do DMA transfer 2271 * set next dma addr and dec count 2272 */ 2273 sbic_save_ptrs(dev); 2274 sbic_load_ptrs(dev); 2275 2276 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2277 SBIC_MACHINE_DMA_MODE); 2278 2279 #ifdef DEBUG 2280 dev->sc_dmatimo = 1; 2281 if ( data_pointer_debug > 1 ) 2282 printf("next DMA: %d(%x:%x)\n", dev->target, 2283 dev->sc_cur->dc_addr, 2284 dev->sc_tcnt); 2285 #endif 2286 /* 2287 * Start the DMA chip going 2288 */ 2289 dev->sc_tcnt = dev->sc_dmanext(dev); 2290 2291 /* 2292 * Tell the WD chip how much to transfer this time around 2293 */ 2294 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2295 2296 /* 2297 * Start the transfer 2298 */ 2299 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2300 2301 /* 2302 * Indicate that we're in DMA mode 2303 */ 2304 dev->sc_flags |= SBICF_INDMA; 2305 } 2306 } 2307 break; 2308 2309 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2310 case SBIC_CSR_MIS | MESG_IN_PHASE: 2311 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2312 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2313 { 2314 sbic_save_ptrs(dev); 2315 2316 /* 2317 * Handle a single message in... 2318 */ 2319 return sbicmsgin(dev); 2320 } 2321 2322 case SBIC_CSR_MSGIN_W_ACK: 2323 { 2324 /* 2325 * We should never see this since it's handled in 'sbicmsgin()' 2326 * but just for the sake of paranoia... 2327 */ 2328 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2329 printf("Acking unknown msgin CSR:%02x",csr); 2330 } 2331 break; 2332 2333 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2334 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2335 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2336 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2337 { 2338 /* 2339 * We only ever handle a message out phase here for sending a 2340 * REJECT message. 2341 */ 2342 sbic_save_ptrs(dev); 2343 2344 #ifdef DEBUG 2345 if (sync_debug) 2346 printf ("sending REJECT msg to last msg.\n"); 2347 #endif 2348 2349 SEND_BYTE(regs, MSG_REJECT); 2350 WAIT_CIP(regs); 2351 } 2352 break; 2353 2354 case SBIC_CSR_DISC: 2355 case SBIC_CSR_DISC_1: 2356 { 2357 /* 2358 * Try to schedule another target 2359 */ 2360 sbic_save_ptrs(dev); 2361 2362 dev->sc_flags &= ~SBICF_SELECTED; 2363 2364 #ifdef DEBUG 2365 if ( reselect_debug > 1 ) 2366 printf("sbicnext target %d disconnected\n", dev->target); 2367 #endif 2368 2369 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2370 2371 ++dev->sc_tinfo[dev->target].dconns; 2372 2373 dev->sc_nexus = NULL; 2374 dev->sc_xs = NULL; 2375 2376 if ( acb->xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2377 !sbic_parallel_operations ) 2378 return SBIC_STATE_DISCONNECT; 2379 2380 QPRINTF(("sbicnext: calling sbic_sched\n")); 2381 2382 sbic_sched(dev); 2383 2384 QPRINTF(("sbicnext: sbic_sched returned\n")); 2385 2386 return SBIC_STATE_DISCONNECT; 2387 } 2388 2389 case SBIC_CSR_RSLT_NI: 2390 case SBIC_CSR_RSLT_IFY: 2391 { 2392 /* 2393 * A reselection. 2394 * Note that since we don't enable Advanced Features (assuming 2395 * the WD chip is at least the 'A' revision), we're only ever 2396 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2397 * hell of it, we'll handle it anyway, for all the extra code 2398 * it needs... 2399 */ 2400 u_char newtarget, 2401 newlun; 2402 2403 GET_SBIC_rselid(regs, newtarget); 2404 2405 /* 2406 * check SBIC_RID_SIV? 2407 */ 2408 newtarget &= SBIC_RID_MASK; 2409 2410 if ( csr == SBIC_CSR_RSLT_IFY ) { 2411 2412 /* 2413 * Read Identify msg to avoid lockup 2414 */ 2415 GET_SBIC_data(regs, newlun); 2416 WAIT_CIP(regs); 2417 newlun &= SBIC_TLUN_MASK; 2418 2419 } else { 2420 2421 /* 2422 * Need to read Identify message the hard way, assuming 2423 * the target even sends us one... 2424 */ 2425 for (newlun = 255; newlun; --newlun) { 2426 GET_SBIC_asr(regs, asr); 2427 if (asr & SBIC_ASR_INT) 2428 break; 2429 delay(10); 2430 } 2431 2432 /* 2433 * If we didn't get an interrupt, somethink's up 2434 */ 2435 if ( (asr & SBIC_ASR_INT) == 0 ) { 2436 printf("%s: Reselect without identify? asr %x\n", 2437 dev->sc_dev.dv_xname, asr); 2438 newlun = 0; /* XXXX */ 2439 } else { 2440 /* 2441 * We got an interrupt, verify that it's a change to 2442 * message in phase, and if so read the message. 2443 */ 2444 GET_SBIC_csr(regs,csr); 2445 2446 if ( csr == SBIC_CSR_MIS | MESG_IN_PHASE || 2447 csr == SBIC_CSR_MIS_1 | MESG_IN_PHASE || 2448 csr == SBIC_CSR_MIS_2 | MESG_IN_PHASE ) { 2449 /* 2450 * Yup, gone to message in. Fetch the target LUN 2451 */ 2452 sbicmsgin(dev); 2453 newlun = dev->sc_msg[0] & 0x07; 2454 2455 } else { 2456 /* 2457 * Whoops! Target didn't go to message in phase!! 2458 */ 2459 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2460 newlun = 0; /* XXXSCW */ 2461 } 2462 } 2463 } 2464 2465 /* 2466 * Ok, we have the identity of the reselecting target. 2467 */ 2468 #ifdef DEBUG 2469 if ( reselect_debug > 1 || 2470 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2471 printf("sbicnext: reselect %s from targ %d lun %d\n", 2472 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2473 } 2474 #endif 2475 2476 if ( dev->sc_nexus ) { 2477 /* 2478 * Whoops! We've been reselected with an command in progress! 2479 * The best we can do is to put the current command back on the 2480 * ready list and hope for the best. 2481 */ 2482 #ifdef DEBUG 2483 if ( reselect_debug > 1 ) { 2484 printf("%s: reselect %s with active command\n", 2485 dev->sc_dev.dv_xname, 2486 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2487 } 2488 #endif 2489 2490 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2491 2492 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2493 2494 dev->sc_nexus = NULL; 2495 dev->sc_xs = NULL; 2496 } 2497 2498 /* 2499 * Reload sync values for this target 2500 */ 2501 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2502 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2503 dev->sc_sync[newtarget].period)); 2504 else 2505 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2506 2507 /* 2508 * Loop through the nexus list until we find the saved entry 2509 * for the reselecting target... 2510 */ 2511 for (acb = dev->nexus_list.tqh_first; acb; 2512 acb = acb->chain.tqe_next) { 2513 2514 if ( acb->xs->sc_link->scsipi_scsi.target == newtarget && 2515 acb->xs->sc_link->scsipi_scsi.lun == newlun) { 2516 /* 2517 * We've found the saved entry. Dequeue it, and 2518 * make it current again. 2519 */ 2520 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2521 2522 dev->sc_nexus = acb; 2523 dev->sc_xs = acb->xs; 2524 dev->sc_flags |= SBICF_SELECTED; 2525 dev->target = newtarget; 2526 dev->lun = newlun; 2527 break; 2528 } 2529 } 2530 2531 if ( acb == NULL ) { 2532 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2533 dev->sc_dev.dv_xname, 2534 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2535 &dev->nexus_list.tqh_first); 2536 panic("bad reselect in sbic"); 2537 } 2538 2539 if ( csr == SBIC_CSR_RSLT_IFY ) 2540 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2541 } 2542 break; 2543 2544 default: 2545 abort: 2546 { 2547 /* 2548 * Something unexpected happened -- deal with it. 2549 */ 2550 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2551 2552 #ifdef DDB 2553 Debugger(); 2554 #endif 2555 2556 #ifdef DEBUG 2557 dev->sc_dmatimo = 0; 2558 if ( data_pointer_debug > 1 ) 2559 printf("next dmastop: %d(%x:%x)\n", dev->target, 2560 dev->sc_cur->dc_addr, 2561 dev->sc_tcnt); 2562 #endif 2563 2564 dev->sc_dmastop(dev); 2565 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2566 if ( dev->sc_xs ) sbicerror(dev, csr); 2567 sbicabort(dev, "next"); 2568 2569 if ( dev->sc_flags & SBICF_INDMA ) { 2570 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2571 2572 #ifdef DEBUG 2573 dev->sc_dmatimo = 0; 2574 if ( data_pointer_debug > 1 ) 2575 printf("next dmastop: %d(%x:%x)\n", dev->target, 2576 dev->sc_cur->dc_addr, 2577 dev->sc_tcnt); 2578 #endif 2579 sbic_scsidone(acb, -1); 2580 } 2581 2582 return SBIC_STATE_ERROR; 2583 } 2584 } 2585 2586 return(SBIC_STATE_RUNNING); 2587 } 2588 2589 2590 /* 2591 * Check if DMA can not be used with specified buffer 2592 */ 2593 int 2594 sbiccheckdmap(bp, len, mask) 2595 void *bp; 2596 u_long len, 2597 mask; 2598 { 2599 u_char *buffer; 2600 u_long phy_buf; 2601 u_long phy_len; 2602 2603 buffer = bp; 2604 2605 if ( len == 0 ) 2606 return(1); 2607 2608 while ( len ) { 2609 2610 phy_buf = kvtop(buffer); 2611 phy_len = NBPG - ((int) buffer & PGOFSET); 2612 2613 if ( len < phy_len ) 2614 phy_len = len; 2615 2616 if ( phy_buf & mask ) 2617 return(1); 2618 2619 buffer += phy_len; 2620 len -= phy_len; 2621 } 2622 2623 return(0); 2624 } 2625 2626 int 2627 sbictoscsiperiod(dev, a) 2628 struct sbic_softc *dev; 2629 int a; 2630 { 2631 unsigned int fs; 2632 2633 /* 2634 * cycle = DIV / (2 * CLK) 2635 * DIV = FS + 2 2636 * best we can do is 200ns at 20Mhz, 2 cycles 2637 */ 2638 2639 GET_SBIC_myid(dev->sc_sbicp, fs); 2640 2641 fs = (fs >> 6) + 2; /* DIV */ 2642 2643 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2644 2645 if ( a < 2 ) 2646 a = 8; /* map to Cycles */ 2647 2648 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2649 } 2650 2651 int 2652 sbicfromscsiperiod(dev, p) 2653 struct sbic_softc *dev; 2654 int p; 2655 { 2656 unsigned fs, 2657 ret; 2658 2659 /* 2660 * Just the inverse of the above 2661 */ 2662 GET_SBIC_myid(dev->sc_sbicp, fs); 2663 2664 fs = (fs >> 6) + 2; /* DIV */ 2665 2666 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2667 2668 ret = p << 2; /* in ns units */ 2669 ret = ret / fs; /* in Cycles */ 2670 2671 if ( ret < sbic_min_period ) 2672 return(sbic_min_period); 2673 2674 /* 2675 * verify rounding 2676 */ 2677 if ( sbictoscsiperiod(dev, ret) < p ) 2678 ret++; 2679 2680 return( (ret >= 8) ? 0 : ret ); 2681 } 2682 2683 #ifdef DEBUG 2684 void 2685 sbictimeout(dev) 2686 struct sbic_softc *dev; 2687 { 2688 int s, 2689 asr; 2690 2691 s = splbio(); 2692 2693 if ( dev->sc_dmatimo ) { 2694 2695 if ( dev->sc_dmatimo > 1 ) { 2696 2697 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2698 dev->sc_dmatimo - 1); 2699 2700 GET_SBIC_asr(dev->sc_sbicp, asr); 2701 2702 if ( asr & SBIC_ASR_INT ) { 2703 /* 2704 * We need to service a missed IRQ 2705 */ 2706 sbicintr(dev); 2707 } else { 2708 (void) sbicabort(dev, "timeout"); 2709 splx(s); 2710 return; 2711 } 2712 } 2713 2714 dev->sc_dmatimo++; 2715 } 2716 2717 splx(s); 2718 2719 timeout((void *)sbictimeout, dev, 30 * hz); 2720 } 2721 #endif 2722
Indexes created Sun Sep 28 16:09:52 GMT 2025