vme_pccreg.h revision 1.2
1 /* $NetBSD: vme_pccreg.h,v 1.2 1997/10/09 08:42:46 jtc Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Based IN PART on a 147 VME driver by Theo de Raadt. 41 */ 42 43 /* 44 * Register map of the Type 1 VMEchip found on the MVME-147 45 * Peripheral Channel Controller. 46 */ 47 48 struct vme_pcc { 49 50 /* 51 * Local VME control registers. 52 */ 53 54 int8_t pad0; 55 volatile u_int8_t vme_scon; 56 57 #define VME1_SCON_SWITCH 0x01 /* SCON jumper is set */ 58 #define VME1_SCON_SRESET 0x02 /* assert SRESET on bus */ 59 #define VME1_SCON_SYSFAIL 0x04 /* assert SYSFAIL on bus */ 60 #define VME1_SCON_ROBIN 0x08 /* round robin bus requests */ 61 62 int8_t pad1; 63 volatile u_int8_t vme_reqconf; 64 65 #define VME1_REQ_IPLMASK 0x03 /* interrupt level for requester */ 66 #define VME1_REQ_RNEVER 0x08 67 #define VME1_REQ_RWD 0x10 68 #define VME1_REQ_DHB 0x40 69 #define VME1_REQ_DWB 0x80 70 71 int8_t pad2; 72 volatile u_int8_t vme_masconf; 73 74 #define VME1_MAS_D16 0x01 /* force d8/16 accesses only */ 75 #define VME1_MAS_MASA24 0x02 /* send address mod for A24 access */ 76 #define VME1_MAS_MASA16 0x04 /* send address mod for A16 access */ 77 #define VME1_MAS_MASUAT 0x08 /* handle unaligned VME cycles */ 78 #define VME1_MAS_CFILL 0x10 /* DO NOT USE */ 79 #define VME1_MAS_MASWP 0x20 /* VME fast mode (DO NOT USE) */ 80 81 int8_t pad3; 82 volatile u_int8_t vme_slconf; 83 84 #define VME1_SLAVE_SLVD16 0x01 /* DO NOT USE */ 85 #define VME1_SLAVE_SLVWP 0x20 /* DO NOT USE */ 86 #define VME1_SLAVE_SLVEN 0x80 /* allow access to onboard DRAM */ 87 88 int8_t pad4; 89 volatile u_int8_t vme_timerconf; 90 91 #define VME1_TIMER_LOCAL_MASK 0x03 92 #define VME1_TIMER_LOCAL_T0 0x00 /* local timeout 102 microsec */ 93 #define VME1_TIMER_LOCAL_T1 0x01 /* local timeout 205 microsec */ 94 #define VME1_TIMER_LOCAL_T2 0x02 /* local timeout 410 microsec */ 95 #define VME1_TIMER_LOCAL_T3 0x03 /* local timeout disabled */ 96 #define VME1_TIMER_VMEACC_MASK 0x0c 97 #define VME1_TIMER_VMEACC_T0 0x00 /* VME access timeout 102 microsec */ 98 #define VME1_TIMER_VMEACC_T1 0x04 /* VME access timeout 1.6 millisec */ 99 #define VME1_TIMER_VMEACC_T2 0x08 /* VME access timeout 51 millisec */ 100 #define VME1_TIMER_VMEACC_T3 0x0c /* VME access timeout disabled */ 101 #define VME1_TIMER_VMEGLO_MASK 0x30 102 #define VME1_TIMER_VMEGLO_T0 0x00 /* VME glob timeout 102 microsec */ 103 #define VME1_TIMER_VMEGLO_T1 0x10 /* VME glob timeout 205 microsec */ 104 #define VME1_TIMER_VMEGLO_T2 0x20 /* VME glob timeout 410 microsec */ 105 #define VME1_TIMER_VMEGLO_T3 0x30 /* VME glob timeout disabled */ 106 #define VME1_TIMER_ARBTO 0x40 /* enable VME arbitration timer */ 107 108 int8_t pad5; 109 volatile u_int8_t vme_sladdrmod; 110 111 #define VME1_SLMOD_DATA 0x01 112 #define VME1_SLMOD_PRGRM 0x02 113 #define VME1_SLMOD_BLOCK 0x04 114 #define VME1_SLMOD_SHORT 0x08 115 #define VME1_SLMOD_STND 0x10 116 #define VME1_SLMOD_EXTED 0x20 117 #define VME1_SLMOD_USER 0x40 118 #define VME1_SLMOD_SUPER 0x80 119 120 int8_t pad6; 121 volatile u_int8_t vme_msaddrmod; 122 123 #define VME1_MSMOD_AM_MASK 0x3f 124 #define VME1_MSMOD_AMSEL 0x80 125 126 int8_t pad7; 127 volatile u_int8_t vme_irqen; 128 129 #define VME1_IRQ_VME(x) (1 << (x)) 130 131 int8_t pad8; 132 volatile u_int8_t vme_uireqen; 133 134 int8_t pad9; 135 volatile u_int8_t vme_uirq; 136 137 int8_t pad10; 138 volatile u_int8_t vme_irq; 139 140 int8_t pad11; 141 volatile u_int8_t vme_vmeid; 142 143 int8_t pad12; 144 volatile u_int8_t vme_buserr; 145 146 int8_t pad13; 147 volatile u_int8_t vme_gcsr; 148 149 int8_t pad14[4]; 150 151 /* 152 * Global Status and Control registers. 153 */ 154 155 int8_t pad15; 156 volatile u_int8_t vme_gcsr_gr0; 157 158 int8_t pad16; 159 volatile u_int8_t vme_gcsr_gr1; 160 161 int8_t pad17; 162 volatile u_int8_t vme_gcsr_boardid; 163 164 int8_t pad18; 165 volatile u_int8_t vme_gcsr_gpr0; 166 167 int8_t pad19; 168 volatile u_int8_t vme_gcsr_gpr1; 169 170 int8_t pad20; 171 volatile u_int8_t vme_gcsr_gpr2; 172 173 int8_t pad21; 174 volatile u_int8_t vme_gcsr_gpr3; 175 176 int8_t pad22; 177 volatile u_int8_t vme_gcsr_gpr4; 178 }; 179 180 /* 181 * The Type 1 VMEchip decoder maps VME address space to system addresses 182 * like this: 183 * 184 * A24/32D32: end of RAM - 0xefffffff 185 * A32D16: 0xf0000000 - 0xff7fffff 186 * A16D16: 0xffff0000 - 0xffffffff 187 * 188 * Note that an A24D32 access on a machine with 16MB of RAM will lose, 189 * since you'll be out of address bits. 190 */ 191 #define VME1_A32D32_START (0x00000000) 192 #define VME1_A32D32_END (0xefffffff) 193 #define VME1_A32D32_LEN ((VME1_A32D32_END - VME1_A32D32_START) + 1) 194 195 #define VME1_A32D16_START (0xf0000000) 196 #define VME1_A32D16_END (0xff7fffff) 197 #define VME1_A32D16_LEN ((VME1_A32D16_END - VME1_A32D16_START) + 1) 198 199 #define VME1_A16D16_START (0xffff0000) 200 #define VME1_A16D16_END (0xffffffff) 201 #define VME1_A16D16_LEN ((VME1_A16D16_END - VME1_A16D16_START) + 1) 202
Indexes created Tue Sep 30 11:09:46 GMT 2025