vme_pccreg.h revision 1.3
1 /* $NetBSD: vme_pccreg.h,v 1.3 2000/03/18 22:33:04 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MVME68K_VME_PCCREG_H 40 #define _MVME68K_VME_PCCREG_H 41 42 /* 43 * Register map of the Type 1 VMEchip found on the MVME-147 44 * Peripheral Channel Controller. 45 */ 46 47 /* 48 * Local control registers... 49 */ 50 #define VME1REG_SCON 0x01 51 #define VME1_SCON_SWITCH 0x01 /* SCON jumper is set */ 52 #define VME1_SCON_SRESET 0x02 /* assert SRESET on bus */ 53 #define VME1_SCON_SYSFAIL 0x04 /* assert SYSFAIL on bus */ 54 #define VME1_SCON_ROBIN 0x08 /* round robin bus requests */ 55 56 #define VME1REG_REQCONF 0x03 57 #define VME1_REQ_IPLMASK 0x03 /* interrupt level for requester */ 58 #define VME1_REQ_RNEVER 0x08 59 #define VME1_REQ_RWD 0x10 60 #define VME1_REQ_DHB 0x40 61 #define VME1_REQ_DWB 0x80 62 63 #define VME1REG_MASCONF 0x05 64 #define VME1_MAS_D16 0x01 /* force d8/16 accesses only */ 65 #define VME1_MAS_MASA24 0x02 /* send address mod for A24 access */ 66 #define VME1_MAS_MASA16 0x04 /* send address mod for A16 access */ 67 #define VME1_MAS_MASUAT 0x08 /* handle unaligned VME cycles */ 68 #define VME1_MAS_CFILL 0x10 /* DO NOT USE */ 69 #define VME1_MAS_MASWP 0x20 /* VME fast mode (DO NOT USE) */ 70 71 #define VME1REG_SLCONF 0x07 72 #define VME1_SLAVE_SLVD16 0x01 /* DO NOT USE */ 73 #define VME1_SLAVE_SLVWP 0x20 /* DO NOT USE */ 74 #define VME1_SLAVE_SLVEN 0x80 /* allow access to onboard DRAM */ 75 76 #define VME1REG_TIMERCONF 0x09 77 #define VME1_TIMER_LOCAL_MASK 0x03 78 #define VME1_TIMER_LOCAL_T0 0x00 /* local timeout 102 microsec */ 79 #define VME1_TIMER_LOCAL_T1 0x01 /* local timeout 205 microsec */ 80 #define VME1_TIMER_LOCAL_T2 0x02 /* local timeout 410 microsec */ 81 #define VME1_TIMER_LOCAL_T3 0x03 /* local timeout disabled */ 82 #define VME1_TIMER_VMEACC_MASK 0x0c 83 #define VME1_TIMER_VMEACC_T0 0x00 /* VME access timeout 102 microsec */ 84 #define VME1_TIMER_VMEACC_T1 0x04 /* VME access timeout 1.6 millisec */ 85 #define VME1_TIMER_VMEACC_T2 0x08 /* VME access timeout 51 millisec */ 86 #define VME1_TIMER_VMEACC_T3 0x0c /* VME access timeout disabled */ 87 #define VME1_TIMER_VMEGLO_MASK 0x30 88 #define VME1_TIMER_VMEGLO_T0 0x00 /* VME glob timeout 102 microsec */ 89 #define VME1_TIMER_VMEGLO_T1 0x10 /* VME glob timeout 205 microsec */ 90 #define VME1_TIMER_VMEGLO_T2 0x20 /* VME glob timeout 410 microsec */ 91 #define VME1_TIMER_VMEGLO_T3 0x30 /* VME glob timeout disabled */ 92 #define VME1_TIMER_ARBTO 0x40 /* enable VME arbitration timer */ 93 94 #define VME1REG_SLADDRMOD 0x0b 95 #define VME1_SLMOD_DATA 0x01 96 #define VME1_SLMOD_PRGRM 0x02 97 #define VME1_SLMOD_BLOCK 0x04 98 #define VME1_SLMOD_SHORT 0x08 99 #define VME1_SLMOD_STND 0x10 100 #define VME1_SLMOD_EXTED 0x20 101 #define VME1_SLMOD_USER 0x40 102 #define VME1_SLMOD_SUPER 0x80 103 104 #define VME1REG_MSADDRMOD 0x0d 105 #define VME1_MSMOD_AM_MASK 0x3f 106 #define VME1_MSMOD_AMSEL 0x80 107 108 #define VME1REG_IRQEN 0x0f 109 #define VME1_IRQ_VME(x) (1 << (x)) 110 111 #define VME1REG_UIREQEN 0x11 112 #define VME1REG_UIRQ 0x13 113 #define VME1REG_IRQ 0x15 114 #define VME1REG_VMEID 0x17 115 #define VME1REG_BUSERR 0x19 116 #define VME1REG_GCSR 0x1b 117 118 119 /* 120 * Global Status and Control registers. 121 */ 122 #define VME1REG_GCSR_GR0 0x21 123 #define VME1REG_GCSR_GR1 0x23 124 #define VME1REG_GCSR_BOARDID 0x25 125 #define VME1REG_GCSR_GPR0 0x27 126 #define VME1REG_GCSR_GPR1 0x29 127 #define VME1REG_GCSR_GPR2 0x2b 128 #define VME1REG_GCSR_GPR3 0x2d 129 #define VME1REG_GCSR_GPR4 0x2f 130 131 /* 132 * Length of the VME chip's register mapping 133 */ 134 #define VME1REG_SIZE 0x30 135 136 137 /* 138 * Convenience macros for reading and writing the registers 139 */ 140 #define vme1_reg_read(sc,r) \ 141 bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, (r)) 142 #define vme1_reg_write(sc,r,v) \ 143 bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, (r), (v)) 144 145 /* 146 * The Type 1 VMEchip decoder maps VME address space to system addresses 147 * like this: 148 * 149 * A24D32: 0x00000000 - 0x00ffffff 150 * A32D32: 0x01000000 - 0xefffffff 151 * A24D16: 0xf0000000 - 0xf0ffffff 152 * A32D16: 0xf1000000 - 0xff7fffff 153 * A16D16: 0xffff0000 - 0xffffffff 154 * 155 * Note that the first A24D32 range is overlayed with onboard RAM. Thus 156 * an 8Mb board will only allow A24D32:0x00800000 - 0x00ffffff. When 157 * onboard RAM is >= 16Mb, the A24D32 range is unavailable and the RAM 158 * starts encroaching on the A32D32 range. 159 */ 160 #define VME1_A24D32_LOC_START (0x00000000u) 161 #define VME1_A24D32_START (0x00000000u) 162 #define VME1_A24D32_END (0x00ffffffu) 163 164 #define VME1_A32D32_LOC_START (0x00000000u) 165 #define VME1_A32D32_START (0x01000000u) 166 #define VME1_A32D32_END (0xefffffffu) 167 168 #define VME1_A24D16_LOC_START (0xf0000000u) 169 #define VME1_A24D16_START (0x00000000u) 170 #define VME1_A24D16_END (0x00ffffffu) 171 172 #define VME1_A32D16_LOC_START (0x00000000u) 173 #define VME1_A32D16_START (0xf1000000u) 174 #define VME1_A32D16_END (0xff7fffffu) 175 176 #define VME1_A16D16_LOC_START (0xffff0000u) 177 #define VME1_A16D16_START (0x00000000u) 178 #define VME1_A16D16_END (0x0000ffffu) 179 180 #define VME1_A32_MASK (0xffffffffu) 181 #define VME1_A24_MASK (0x00ffffffu) 182 #define VME1_A16_MASK (0x0000ffffu) 183 184 #endif /* _MVME68K_VME_PCCREG_H */ 185
Indexes created Mon Sep 29 21:09:56 GMT 2025