wdsc.c revision 1.28 1 1.28 scw /* $NetBSD: wdsc.c,v 1.28 2004/03/28 15:35:33 scw Exp $ */
2 1.1 chuck
3 1.1 chuck /*
4 1.1 chuck * Copyright (c) 1982, 1990 The Regents of the University of California.
5 1.1 chuck * All rights reserved.
6 1.1 chuck *
7 1.1 chuck * Redistribution and use in source and binary forms, with or without
8 1.1 chuck * modification, are permitted provided that the following conditions
9 1.1 chuck * are met:
10 1.1 chuck * 1. Redistributions of source code must retain the above copyright
11 1.1 chuck * notice, this list of conditions and the following disclaimer.
12 1.1 chuck * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 chuck * notice, this list of conditions and the following disclaimer in the
14 1.1 chuck * documentation and/or other materials provided with the distribution.
15 1.27 agc * 3. Neither the name of the University nor the names of its contributors
16 1.27 agc * may be used to endorse or promote products derived from this software
17 1.27 agc * without specific prior written permission.
18 1.27 agc *
19 1.27 agc * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 1.27 agc * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 1.27 agc * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 1.27 agc * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 1.27 agc * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 1.27 agc * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 1.27 agc * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 1.27 agc * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 1.27 agc * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 1.27 agc * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 1.27 agc * SUCH DAMAGE.
30 1.27 agc *
31 1.27 agc * @(#)wdsc.c
32 1.27 agc */
33 1.27 agc
34 1.28 scw /*-
35 1.28 scw * Copyright (c) 1996-2004 The NetBSD Foundation, Inc.
36 1.28 scw * All rights reserved.
37 1.28 scw *
38 1.28 scw * This code is derived from software contributed to The NetBSD Foundation
39 1.28 scw * by Steve C. Woodford.
40 1.27 agc *
41 1.27 agc * Redistribution and use in source and binary forms, with or without
42 1.27 agc * modification, are permitted provided that the following conditions
43 1.27 agc * are met:
44 1.27 agc * 1. Redistributions of source code must retain the above copyright
45 1.27 agc * notice, this list of conditions and the following disclaimer.
46 1.27 agc * 2. Redistributions in binary form must reproduce the above copyright
47 1.27 agc * notice, this list of conditions and the following disclaimer in the
48 1.27 agc * documentation and/or other materials provided with the distribution.
49 1.1 chuck * 3. All advertising materials mentioning features or use of this software
50 1.1 chuck * must display the following acknowledgement:
51 1.28 scw * This product includes software developed by the NetBSD
52 1.28 scw * Foundation, Inc. and its contributors.
53 1.28 scw * 4. Neither the name of The NetBSD Foundation nor the names of its
54 1.28 scw * contributors may be used to endorse or promote products derived
55 1.28 scw * from this software without specific prior written permission.
56 1.1 chuck *
57 1.28 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
58 1.28 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
59 1.28 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
60 1.28 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
61 1.28 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
62 1.28 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
63 1.28 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
64 1.28 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
65 1.28 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
66 1.28 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
67 1.28 scw * POSSIBILITY OF SUCH DAMAGE.
68 1.1 chuck */
69 1.26 lukem
70 1.26 lukem #include <sys/cdefs.h>
71 1.28 scw __KERNEL_RCSID(0, "$NetBSD: wdsc.c,v 1.28 2004/03/28 15:35:33 scw Exp $");
72 1.2 chuck
73 1.1 chuck #include <sys/param.h>
74 1.1 chuck #include <sys/systm.h>
75 1.1 chuck #include <sys/kernel.h>
76 1.1 chuck #include <sys/device.h>
77 1.2 chuck
78 1.10 bouyer #include <dev/scsipi/scsi_all.h>
79 1.10 bouyer #include <dev/scsipi/scsipi_all.h>
80 1.10 bouyer #include <dev/scsipi/scsiconf.h>
81 1.2 chuck
82 1.16 scw #include <machine/cpu.h>
83 1.17 scw #include <machine/bus.h>
84 1.3 chuck #include <machine/autoconf.h>
85 1.3 chuck
86 1.2 chuck #include <mvme68k/dev/dmavar.h>
87 1.1 chuck #include <mvme68k/dev/pccreg.h>
88 1.2 chuck #include <mvme68k/dev/pccvar.h>
89 1.1 chuck #include <mvme68k/dev/sbicreg.h>
90 1.1 chuck #include <mvme68k/dev/sbicvar.h>
91 1.1 chuck #include <mvme68k/dev/wdscreg.h>
92 1.1 chuck
93 1.2 chuck void wdsc_pcc_attach __P((struct device *, struct device *, void *));
94 1.9 gwr int wdsc_pcc_match __P((struct device *, struct cfdata *, void *));
95 1.1 chuck
96 1.23 thorpej CFATTACH_DECL(wdsc_pcc, sizeof(struct sbic_softc),
97 1.23 thorpej wdsc_pcc_match, wdsc_pcc_attach, NULL, NULL);
98 1.17 scw
99 1.17 scw extern struct cfdriver wdsc_cd;
100 1.17 scw
101 1.1 chuck void wdsc_enintr __P((struct sbic_softc *));
102 1.1 chuck int wdsc_dmago __P((struct sbic_softc *, char *, int, int));
103 1.1 chuck int wdsc_dmanext __P((struct sbic_softc *));
104 1.1 chuck void wdsc_dmastop __P((struct sbic_softc *));
105 1.2 chuck int wdsc_dmaintr __P((void *));
106 1.2 chuck int wdsc_scsiintr __P((void *));
107 1.1 chuck
108 1.1 chuck /*
109 1.1 chuck * Match for SCSI devices on the onboard WD33C93 chip
110 1.1 chuck */
111 1.1 chuck int
112 1.9 gwr wdsc_pcc_match(pdp, cf, auxp)
113 1.1 chuck struct device *pdp;
114 1.9 gwr struct cfdata *cf;
115 1.9 gwr void *auxp;
116 1.1 chuck {
117 1.2 chuck struct pcc_attach_args *pa = auxp;
118 1.2 chuck
119 1.2 chuck if (strcmp(pa->pa_name, wdsc_cd.cd_name))
120 1.2 chuck return (0);
121 1.2 chuck
122 1.2 chuck pa->pa_ipl = cf->pcccf_ipl;
123 1.2 chuck return (1);
124 1.1 chuck }
125 1.1 chuck
126 1.1 chuck /*
127 1.1 chuck * Attach the wdsc driver
128 1.1 chuck */
129 1.1 chuck void
130 1.2 chuck wdsc_pcc_attach(pdp, dp, auxp)
131 1.1 chuck struct device *pdp, *dp;
132 1.1 chuck void *auxp;
133 1.1 chuck {
134 1.17 scw struct sbic_softc *sc;
135 1.17 scw struct pcc_attach_args *pa;
136 1.17 scw bus_space_handle_t bush;
137 1.21 scw static struct evcnt evcnt; /* XXXSCW: Temporary hack */
138 1.1 chuck
139 1.17 scw sc = (struct sbic_softc *)dp;
140 1.17 scw pa = auxp;
141 1.17 scw
142 1.17 scw bus_space_map(pa->pa_bust, pa->pa_offset, 0x20, 0, &bush);
143 1.1 chuck
144 1.17 scw /*
145 1.17 scw * XXXSCW: We *need* an MI, bus_spaced WD33C93 driver...
146 1.17 scw */
147 1.17 scw sc->sc_sbicp = (sbic_regmap_p) bush;
148 1.1 chuck
149 1.21 scw sc->sc_driver = (void *) &evcnt;
150 1.1 chuck sc->sc_enintr = wdsc_enintr;
151 1.1 chuck sc->sc_dmago = wdsc_dmago;
152 1.1 chuck sc->sc_dmanext = wdsc_dmanext;
153 1.1 chuck sc->sc_dmastop = wdsc_dmastop;
154 1.1 chuck sc->sc_dmacmd = 0;
155 1.1 chuck
156 1.20 bouyer sc->sc_adapter.adapt_dev = &sc->sc_dev;
157 1.20 bouyer sc->sc_adapter.adapt_nchannels = 1;
158 1.20 bouyer sc->sc_adapter.adapt_openings = 7;
159 1.20 bouyer sc->sc_adapter.adapt_max_periph = 1;
160 1.20 bouyer sc->sc_adapter.adapt_ioctl = NULL;
161 1.20 bouyer sc->sc_adapter.adapt_minphys = sbic_minphys;
162 1.20 bouyer sc->sc_adapter.adapt_request = sbic_scsi_request;
163 1.20 bouyer
164 1.20 bouyer sc->sc_channel.chan_adapter = &sc->sc_adapter;
165 1.20 bouyer sc->sc_channel.chan_bustype = &scsi_bustype;
166 1.20 bouyer sc->sc_channel.chan_channel = 0;
167 1.20 bouyer sc->sc_channel.chan_ntargets = 8;
168 1.20 bouyer sc->sc_channel.chan_nluns = 8;
169 1.20 bouyer sc->sc_channel.chan_id = 7;
170 1.1 chuck
171 1.20 bouyer printf(": WD33C93 SCSI, target %d\n", sc->sc_channel.chan_id);
172 1.1 chuck
173 1.1 chuck /*
174 1.25 wiz * Everything is a valid DMA address.
175 1.1 chuck */
176 1.1 chuck sc->sc_dmamask = 0;
177 1.1 chuck
178 1.1 chuck /*
179 1.1 chuck * The onboard WD33C93 of the '147 is usually clocked at 10MHz...
180 1.1 chuck * (We use 10 times this for accuracy in later calculations)
181 1.1 chuck */
182 1.1 chuck sc->sc_clkfreq = 100;
183 1.1 chuck
184 1.1 chuck /*
185 1.1 chuck * Initialise the hardware
186 1.1 chuck */
187 1.1 chuck sbicinit(sc);
188 1.1 chuck
189 1.1 chuck /*
190 1.1 chuck * Fix up the interrupts
191 1.1 chuck */
192 1.2 chuck sc->sc_ipl = pa->pa_ipl & PCC_IMASK;
193 1.1 chuck
194 1.17 scw pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, PCC_ICLEAR);
195 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, PCC_ICLEAR);
196 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0);
197 1.17 scw
198 1.21 scw evcnt_attach_dynamic(&evcnt, EVCNT_TYPE_INTR, pccintr_evcnt(sc->sc_ipl),
199 1.21 scw "disk", sc->sc_dev.dv_xname);
200 1.21 scw pccintr_establish(PCCV_DMA, wdsc_dmaintr, sc->sc_ipl, sc, &evcnt);
201 1.21 scw pccintr_establish(PCCV_SCSI, wdsc_scsiintr, sc->sc_ipl, sc, &evcnt);
202 1.17 scw pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL,
203 1.17 scw sc->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
204 1.1 chuck
205 1.20 bouyer (void)config_found(dp, &sc->sc_channel, scsiprint);
206 1.1 chuck }
207 1.1 chuck
208 1.1 chuck /*
209 1.1 chuck * Enable DMA interrupts
210 1.1 chuck */
211 1.1 chuck void
212 1.1 chuck wdsc_enintr(dev)
213 1.1 chuck struct sbic_softc *dev;
214 1.1 chuck {
215 1.1 chuck dev->sc_flags |= SBICF_INTR;
216 1.1 chuck
217 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL,
218 1.17 scw dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
219 1.1 chuck }
220 1.1 chuck
221 1.1 chuck /*
222 1.1 chuck * Prime the hardware for a DMA transfer
223 1.1 chuck */
224 1.1 chuck int
225 1.1 chuck wdsc_dmago(dev, addr, count, flags)
226 1.1 chuck struct sbic_softc *dev;
227 1.1 chuck char *addr;
228 1.1 chuck int count, flags;
229 1.1 chuck {
230 1.1 chuck /*
231 1.1 chuck * Set up the command word based on flags
232 1.1 chuck */
233 1.1 chuck if ( (flags & DMAGO_READ) == 0 )
234 1.1 chuck dev->sc_dmacmd = DMAC_CSR_ENABLE | DMAC_CSR_WRITE;
235 1.1 chuck else
236 1.1 chuck dev->sc_dmacmd = DMAC_CSR_ENABLE;
237 1.1 chuck
238 1.1 chuck dev->sc_flags |= SBICF_INTR;
239 1.1 chuck dev->sc_tcnt = dev->sc_cur->dc_count << 1;
240 1.1 chuck
241 1.1 chuck /*
242 1.1 chuck * Prime the hardware.
243 1.1 chuck * Note, it's probably not necessary to do this here, since dmanext
244 1.1 chuck * is called just prior to the actual transfer.
245 1.1 chuck */
246 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0);
247 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL,
248 1.17 scw dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
249 1.17 scw pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR,
250 1.17 scw (u_int32_t) dev->sc_cur->dc_addr);
251 1.17 scw pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT,
252 1.17 scw (u_int32_t) dev->sc_tcnt | (1 << 24));
253 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd);
254 1.1 chuck
255 1.1 chuck return(dev->sc_tcnt);
256 1.1 chuck }
257 1.1 chuck
258 1.1 chuck /*
259 1.1 chuck * Prime the hardware for the next DMA transfer
260 1.1 chuck */
261 1.1 chuck int
262 1.1 chuck wdsc_dmanext(dev)
263 1.1 chuck struct sbic_softc *dev;
264 1.1 chuck {
265 1.1 chuck if ( dev->sc_cur > dev->sc_last ) {
266 1.1 chuck /*
267 1.1 chuck * Shouldn't happen !!
268 1.1 chuck */
269 1.7 christos printf("wdsc_dmanext at end !!!\n");
270 1.1 chuck wdsc_dmastop(dev);
271 1.1 chuck return(0);
272 1.1 chuck }
273 1.1 chuck
274 1.1 chuck dev->sc_tcnt = dev->sc_cur->dc_count << 1;
275 1.1 chuck
276 1.1 chuck /*
277 1.1 chuck * Load the next DMA address
278 1.1 chuck */
279 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0);
280 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL,
281 1.17 scw dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
282 1.17 scw pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR,
283 1.17 scw (u_int32_t) dev->sc_cur->dc_addr);
284 1.17 scw pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT,
285 1.17 scw (u_int32_t) dev->sc_tcnt | (1 << 24));
286 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd);
287 1.1 chuck
288 1.1 chuck return(dev->sc_tcnt);
289 1.1 chuck }
290 1.1 chuck
291 1.1 chuck /*
292 1.1 chuck * Stop DMA, and disable interrupts
293 1.1 chuck */
294 1.1 chuck void
295 1.1 chuck wdsc_dmastop(dev)
296 1.1 chuck struct sbic_softc *dev;
297 1.1 chuck {
298 1.17 scw int s;
299 1.1 chuck
300 1.1 chuck s = splbio();
301 1.1 chuck
302 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0);
303 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, dev->sc_ipl | PCC_ICLEAR);
304 1.1 chuck
305 1.1 chuck splx(s);
306 1.1 chuck }
307 1.1 chuck
308 1.1 chuck /*
309 1.1 chuck * Come here following a DMA interrupt
310 1.1 chuck */
311 1.1 chuck int
312 1.2 chuck wdsc_dmaintr(arg)
313 1.2 chuck void *arg;
314 1.1 chuck {
315 1.2 chuck struct sbic_softc *dev = arg;
316 1.17 scw int found = 0;
317 1.1 chuck
318 1.1 chuck /*
319 1.1 chuck * Really a DMA interrupt?
320 1.1 chuck */
321 1.17 scw if ( (pcc_reg_read(sys_pcc, PCCREG_DMA_INTR_CTRL) & 0x80) == 0 )
322 1.1 chuck return(0);
323 1.1 chuck
324 1.1 chuck /*
325 1.1 chuck * Was it a completion interrupt?
326 1.1 chuck * XXXSCW Note: Support for other DMA interrupts is required, eg. buserr
327 1.1 chuck */
328 1.17 scw if ( pcc_reg_read(sys_pcc, PCCREG_DMA_CONTROL) & DMAC_CSR_DONE ) {
329 1.1 chuck ++found;
330 1.1 chuck
331 1.17 scw pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL,
332 1.17 scw dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
333 1.1 chuck }
334 1.1 chuck
335 1.1 chuck return(found);
336 1.1 chuck }
337 1.1 chuck
338 1.1 chuck /*
339 1.1 chuck * Come here for SCSI interrupts
340 1.1 chuck */
341 1.1 chuck int
342 1.2 chuck wdsc_scsiintr(arg)
343 1.2 chuck void *arg;
344 1.1 chuck {
345 1.2 chuck struct sbic_softc *dev = arg;
346 1.17 scw int found;
347 1.1 chuck
348 1.1 chuck /*
349 1.1 chuck * Really a SCSI interrupt?
350 1.1 chuck */
351 1.17 scw if ( (pcc_reg_read(sys_pcc, PCCREG_SCSI_INTR_CTRL) & 0x80) == 0 )
352 1.1 chuck return(0);
353 1.1 chuck
354 1.1 chuck /*
355 1.1 chuck * Go handle it
356 1.1 chuck */
357 1.1 chuck found = sbicintr(dev);
358 1.1 chuck
359 1.1 chuck /*
360 1.1 chuck * Acknowledge and clear the interrupt
361 1.1 chuck */
362 1.17 scw pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL,
363 1.17 scw dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
364 1.1 chuck
365 1.1 chuck return(found);
366 1.1 chuck }
367