wdsc.c revision 1.18
1 /* $NetBSD: wdsc.c,v 1.18 2000/07/25 20:52:29 scw Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Steve Woodford 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)wdsc.c 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsiconf.h> 47 48 #include <machine/cpu.h> 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 52 #include <mvme68k/dev/dmavar.h> 53 #include <mvme68k/dev/pccreg.h> 54 #include <mvme68k/dev/pccvar.h> 55 #include <mvme68k/dev/sbicreg.h> 56 #include <mvme68k/dev/sbicvar.h> 57 #include <mvme68k/dev/wdscreg.h> 58 59 void wdsc_pcc_attach __P((struct device *, struct device *, void *)); 60 int wdsc_pcc_match __P((struct device *, struct cfdata *, void *)); 61 62 struct cfattach wdsc_pcc_ca = { 63 sizeof(struct sbic_softc), wdsc_pcc_match, wdsc_pcc_attach 64 }; 65 66 extern struct cfdriver wdsc_cd; 67 68 void wdsc_enintr __P((struct sbic_softc *)); 69 int wdsc_dmago __P((struct sbic_softc *, char *, int, int)); 70 int wdsc_dmanext __P((struct sbic_softc *)); 71 void wdsc_dmastop __P((struct sbic_softc *)); 72 int wdsc_dmaintr __P((void *)); 73 int wdsc_scsiintr __P((void *)); 74 75 struct scsipi_device wdsc_scsidev = { 76 NULL, /* use default error handler */ 77 NULL, /* do not have a start functio */ 78 NULL, /* have no async handler */ 79 NULL, /* Use default done routine */ 80 }; 81 82 83 /* 84 * Match for SCSI devices on the onboard WD33C93 chip 85 */ 86 int 87 wdsc_pcc_match(pdp, cf, auxp) 88 struct device *pdp; 89 struct cfdata *cf; 90 void *auxp; 91 { 92 struct pcc_attach_args *pa = auxp; 93 94 if (strcmp(pa->pa_name, wdsc_cd.cd_name)) 95 return (0); 96 97 pa->pa_ipl = cf->pcccf_ipl; 98 return (1); 99 } 100 101 /* 102 * Attach the wdsc driver 103 */ 104 void 105 wdsc_pcc_attach(pdp, dp, auxp) 106 struct device *pdp, *dp; 107 void *auxp; 108 { 109 struct sbic_softc *sc; 110 struct pcc_attach_args *pa; 111 bus_space_handle_t bush; 112 int tmp; 113 114 sc = (struct sbic_softc *)dp; 115 pa = auxp; 116 117 bus_space_map(pa->pa_bust, pa->pa_offset, 0x20, 0, &bush); 118 119 /* 120 * XXXSCW: We *need* an MI, bus_spaced WD33C93 driver... 121 */ 122 sc->sc_sbicp = (sbic_regmap_p) bush; 123 124 sc->sc_enintr = wdsc_enintr; 125 sc->sc_dmago = wdsc_dmago; 126 sc->sc_dmanext = wdsc_dmanext; 127 sc->sc_dmastop = wdsc_dmastop; 128 sc->sc_dmacmd = 0; 129 130 sc->sc_adapter.scsipi_cmd = sbic_scsicmd; 131 sc->sc_adapter.scsipi_minphys = sbic_minphys; 132 133 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 134 sc->sc_link.adapter_softc = sc; 135 sc->sc_link.scsipi_scsi.adapter_target = 7; 136 sc->sc_link.adapter = &sc->sc_adapter; 137 sc->sc_link.device = &wdsc_scsidev; 138 sc->sc_link.openings = 2; 139 sc->sc_link.scsipi_scsi.max_target = 7; 140 sc->sc_link.scsipi_scsi.max_lun = 7; 141 sc->sc_link.type = BUS_SCSI; 142 143 printf(": WD33C93 SCSI, target %d\n", 144 sc->sc_link.scsipi_scsi.adapter_target); 145 146 /* 147 * Eveything is a valid dma address. 148 */ 149 sc->sc_dmamask = 0; 150 151 /* 152 * The onboard WD33C93 of the '147 is usually clocked at 10MHz... 153 * (We use 10 times this for accuracy in later calculations) 154 */ 155 sc->sc_clkfreq = 100; 156 157 /* 158 * Initialise the hardware 159 */ 160 sbicinit(sc); 161 162 /* 163 * Fix up the interrupts 164 */ 165 sc->sc_ipl = pa->pa_ipl & PCC_IMASK; 166 167 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, PCC_ICLEAR); 168 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, PCC_ICLEAR); 169 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 170 171 pccintr_establish(PCCV_DMA, wdsc_dmaintr, sc->sc_ipl, sc); 172 pccintr_establish(PCCV_SCSI, wdsc_scsiintr, sc->sc_ipl, sc); 173 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 174 sc->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 175 176 (void)config_found(dp, &sc->sc_link, scsiprint); 177 } 178 179 /* 180 * Enable DMA interrupts 181 */ 182 void 183 wdsc_enintr(dev) 184 struct sbic_softc *dev; 185 { 186 dev->sc_flags |= SBICF_INTR; 187 188 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 189 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 190 } 191 192 /* 193 * Prime the hardware for a DMA transfer 194 */ 195 int 196 wdsc_dmago(dev, addr, count, flags) 197 struct sbic_softc *dev; 198 char *addr; 199 int count, flags; 200 { 201 /* 202 * Set up the command word based on flags 203 */ 204 if ( (flags & DMAGO_READ) == 0 ) 205 dev->sc_dmacmd = DMAC_CSR_ENABLE | DMAC_CSR_WRITE; 206 else 207 dev->sc_dmacmd = DMAC_CSR_ENABLE; 208 209 dev->sc_flags |= SBICF_INTR; 210 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 211 212 /* 213 * Prime the hardware. 214 * Note, it's probably not necessary to do this here, since dmanext 215 * is called just prior to the actual transfer. 216 */ 217 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 218 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 219 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 220 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 221 (u_int32_t) dev->sc_cur->dc_addr); 222 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 223 (u_int32_t) dev->sc_tcnt | (1 << 24)); 224 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 225 226 return(dev->sc_tcnt); 227 } 228 229 /* 230 * Prime the hardware for the next DMA transfer 231 */ 232 int 233 wdsc_dmanext(dev) 234 struct sbic_softc *dev; 235 { 236 if ( dev->sc_cur > dev->sc_last ) { 237 /* 238 * Shouldn't happen !! 239 */ 240 printf("wdsc_dmanext at end !!!\n"); 241 wdsc_dmastop(dev); 242 return(0); 243 } 244 245 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 246 247 /* 248 * Load the next DMA address 249 */ 250 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 251 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 252 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 253 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 254 (u_int32_t) dev->sc_cur->dc_addr); 255 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 256 (u_int32_t) dev->sc_tcnt | (1 << 24)); 257 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 258 259 return(dev->sc_tcnt); 260 } 261 262 /* 263 * Stop DMA, and disable interrupts 264 */ 265 void 266 wdsc_dmastop(dev) 267 struct sbic_softc *dev; 268 { 269 int s; 270 271 s = splbio(); 272 273 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 274 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, dev->sc_ipl | PCC_ICLEAR); 275 276 splx(s); 277 } 278 279 /* 280 * Come here following a DMA interrupt 281 */ 282 int 283 wdsc_dmaintr(arg) 284 void *arg; 285 { 286 struct sbic_softc *dev = arg; 287 int found = 0; 288 289 /* 290 * Really a DMA interrupt? 291 */ 292 if ( (pcc_reg_read(sys_pcc, PCCREG_DMA_INTR_CTRL) & 0x80) == 0 ) 293 return(0); 294 295 /* 296 * Was it a completion interrupt? 297 * XXXSCW Note: Support for other DMA interrupts is required, eg. buserr 298 */ 299 if ( pcc_reg_read(sys_pcc, PCCREG_DMA_CONTROL) & DMAC_CSR_DONE ) { 300 ++found; 301 302 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 303 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 304 } 305 306 return(found); 307 } 308 309 /* 310 * Come here for SCSI interrupts 311 */ 312 int 313 wdsc_scsiintr(arg) 314 void *arg; 315 { 316 struct sbic_softc *dev = arg; 317 int found; 318 319 /* 320 * Really a SCSI interrupt? 321 */ 322 if ( (pcc_reg_read(sys_pcc, PCCREG_SCSI_INTR_CTRL) & 0x80) == 0 ) 323 return(0); 324 325 /* 326 * Go handle it 327 */ 328 found = sbicintr(dev); 329 330 /* 331 * Acknowledge and clear the interrupt 332 */ 333 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 334 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 335 336 return(found); 337 } 338
Indexes created Sun Oct 19 16:10:00 GMT 2025