wdsc.c revision 1.19
1 /* $NetBSD: wdsc.c,v 1.19 2000/08/12 20:09:12 scw Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Steve Woodford 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)wdsc.c 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsiconf.h> 47 48 #include <machine/cpu.h> 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 52 #include <mvme68k/dev/dmavar.h> 53 #include <mvme68k/dev/pccreg.h> 54 #include <mvme68k/dev/pccvar.h> 55 #include <mvme68k/dev/sbicreg.h> 56 #include <mvme68k/dev/sbicvar.h> 57 #include <mvme68k/dev/wdscreg.h> 58 59 void wdsc_pcc_attach __P((struct device *, struct device *, void *)); 60 int wdsc_pcc_match __P((struct device *, struct cfdata *, void *)); 61 62 struct cfattach wdsc_pcc_ca = { 63 sizeof(struct sbic_softc), wdsc_pcc_match, wdsc_pcc_attach 64 }; 65 66 extern struct cfdriver wdsc_cd; 67 68 void wdsc_enintr __P((struct sbic_softc *)); 69 int wdsc_dmago __P((struct sbic_softc *, char *, int, int)); 70 int wdsc_dmanext __P((struct sbic_softc *)); 71 void wdsc_dmastop __P((struct sbic_softc *)); 72 int wdsc_dmaintr __P((void *)); 73 int wdsc_scsiintr __P((void *)); 74 75 struct scsipi_device wdsc_scsidev = { 76 NULL, /* use default error handler */ 77 NULL, /* do not have a start functio */ 78 NULL, /* have no async handler */ 79 NULL, /* Use default done routine */ 80 }; 81 82 83 /* 84 * Match for SCSI devices on the onboard WD33C93 chip 85 */ 86 int 87 wdsc_pcc_match(pdp, cf, auxp) 88 struct device *pdp; 89 struct cfdata *cf; 90 void *auxp; 91 { 92 struct pcc_attach_args *pa = auxp; 93 94 if (strcmp(pa->pa_name, wdsc_cd.cd_name)) 95 return (0); 96 97 pa->pa_ipl = cf->pcccf_ipl; 98 return (1); 99 } 100 101 /* 102 * Attach the wdsc driver 103 */ 104 void 105 wdsc_pcc_attach(pdp, dp, auxp) 106 struct device *pdp, *dp; 107 void *auxp; 108 { 109 struct sbic_softc *sc; 110 struct pcc_attach_args *pa; 111 bus_space_handle_t bush; 112 113 sc = (struct sbic_softc *)dp; 114 pa = auxp; 115 116 bus_space_map(pa->pa_bust, pa->pa_offset, 0x20, 0, &bush); 117 118 /* 119 * XXXSCW: We *need* an MI, bus_spaced WD33C93 driver... 120 */ 121 sc->sc_sbicp = (sbic_regmap_p) bush; 122 123 sc->sc_enintr = wdsc_enintr; 124 sc->sc_dmago = wdsc_dmago; 125 sc->sc_dmanext = wdsc_dmanext; 126 sc->sc_dmastop = wdsc_dmastop; 127 sc->sc_dmacmd = 0; 128 129 sc->sc_adapter.scsipi_cmd = sbic_scsicmd; 130 sc->sc_adapter.scsipi_minphys = sbic_minphys; 131 132 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 133 sc->sc_link.adapter_softc = sc; 134 sc->sc_link.scsipi_scsi.adapter_target = 7; 135 sc->sc_link.adapter = &sc->sc_adapter; 136 sc->sc_link.device = &wdsc_scsidev; 137 sc->sc_link.openings = 2; 138 sc->sc_link.scsipi_scsi.max_target = 7; 139 sc->sc_link.scsipi_scsi.max_lun = 7; 140 sc->sc_link.type = BUS_SCSI; 141 142 printf(": WD33C93 SCSI, target %d\n", 143 sc->sc_link.scsipi_scsi.adapter_target); 144 145 /* 146 * Eveything is a valid dma address. 147 */ 148 sc->sc_dmamask = 0; 149 150 /* 151 * The onboard WD33C93 of the '147 is usually clocked at 10MHz... 152 * (We use 10 times this for accuracy in later calculations) 153 */ 154 sc->sc_clkfreq = 100; 155 156 /* 157 * Initialise the hardware 158 */ 159 sbicinit(sc); 160 161 /* 162 * Fix up the interrupts 163 */ 164 sc->sc_ipl = pa->pa_ipl & PCC_IMASK; 165 166 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, PCC_ICLEAR); 167 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, PCC_ICLEAR); 168 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 169 170 pccintr_establish(PCCV_DMA, wdsc_dmaintr, sc->sc_ipl, sc); 171 pccintr_establish(PCCV_SCSI, wdsc_scsiintr, sc->sc_ipl, sc); 172 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 173 sc->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 174 175 (void)config_found(dp, &sc->sc_link, scsiprint); 176 } 177 178 /* 179 * Enable DMA interrupts 180 */ 181 void 182 wdsc_enintr(dev) 183 struct sbic_softc *dev; 184 { 185 dev->sc_flags |= SBICF_INTR; 186 187 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 188 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 189 } 190 191 /* 192 * Prime the hardware for a DMA transfer 193 */ 194 int 195 wdsc_dmago(dev, addr, count, flags) 196 struct sbic_softc *dev; 197 char *addr; 198 int count, flags; 199 { 200 /* 201 * Set up the command word based on flags 202 */ 203 if ( (flags & DMAGO_READ) == 0 ) 204 dev->sc_dmacmd = DMAC_CSR_ENABLE | DMAC_CSR_WRITE; 205 else 206 dev->sc_dmacmd = DMAC_CSR_ENABLE; 207 208 dev->sc_flags |= SBICF_INTR; 209 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 210 211 /* 212 * Prime the hardware. 213 * Note, it's probably not necessary to do this here, since dmanext 214 * is called just prior to the actual transfer. 215 */ 216 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 217 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 218 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 219 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 220 (u_int32_t) dev->sc_cur->dc_addr); 221 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 222 (u_int32_t) dev->sc_tcnt | (1 << 24)); 223 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 224 225 return(dev->sc_tcnt); 226 } 227 228 /* 229 * Prime the hardware for the next DMA transfer 230 */ 231 int 232 wdsc_dmanext(dev) 233 struct sbic_softc *dev; 234 { 235 if ( dev->sc_cur > dev->sc_last ) { 236 /* 237 * Shouldn't happen !! 238 */ 239 printf("wdsc_dmanext at end !!!\n"); 240 wdsc_dmastop(dev); 241 return(0); 242 } 243 244 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 245 246 /* 247 * Load the next DMA address 248 */ 249 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 250 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 251 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 252 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 253 (u_int32_t) dev->sc_cur->dc_addr); 254 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 255 (u_int32_t) dev->sc_tcnt | (1 << 24)); 256 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 257 258 return(dev->sc_tcnt); 259 } 260 261 /* 262 * Stop DMA, and disable interrupts 263 */ 264 void 265 wdsc_dmastop(dev) 266 struct sbic_softc *dev; 267 { 268 int s; 269 270 s = splbio(); 271 272 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 273 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, dev->sc_ipl | PCC_ICLEAR); 274 275 splx(s); 276 } 277 278 /* 279 * Come here following a DMA interrupt 280 */ 281 int 282 wdsc_dmaintr(arg) 283 void *arg; 284 { 285 struct sbic_softc *dev = arg; 286 int found = 0; 287 288 /* 289 * Really a DMA interrupt? 290 */ 291 if ( (pcc_reg_read(sys_pcc, PCCREG_DMA_INTR_CTRL) & 0x80) == 0 ) 292 return(0); 293 294 /* 295 * Was it a completion interrupt? 296 * XXXSCW Note: Support for other DMA interrupts is required, eg. buserr 297 */ 298 if ( pcc_reg_read(sys_pcc, PCCREG_DMA_CONTROL) & DMAC_CSR_DONE ) { 299 ++found; 300 301 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 302 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 303 } 304 305 return(found); 306 } 307 308 /* 309 * Come here for SCSI interrupts 310 */ 311 int 312 wdsc_scsiintr(arg) 313 void *arg; 314 { 315 struct sbic_softc *dev = arg; 316 int found; 317 318 /* 319 * Really a SCSI interrupt? 320 */ 321 if ( (pcc_reg_read(sys_pcc, PCCREG_SCSI_INTR_CTRL) & 0x80) == 0 ) 322 return(0); 323 324 /* 325 * Go handle it 326 */ 327 found = sbicintr(dev); 328 329 /* 330 * Acknowledge and clear the interrupt 331 */ 332 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 333 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 334 335 return(found); 336 } 337
Indexes created Thu Oct 23 18:09:57 GMT 2025