wdsc.c revision 1.20
1 /* $NetBSD: wdsc.c,v 1.20 2001/04/25 17:53:17 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Steve Woodford 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)wdsc.c 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsiconf.h> 47 48 #include <machine/cpu.h> 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 52 #include <mvme68k/dev/dmavar.h> 53 #include <mvme68k/dev/pccreg.h> 54 #include <mvme68k/dev/pccvar.h> 55 #include <mvme68k/dev/sbicreg.h> 56 #include <mvme68k/dev/sbicvar.h> 57 #include <mvme68k/dev/wdscreg.h> 58 59 void wdsc_pcc_attach __P((struct device *, struct device *, void *)); 60 int wdsc_pcc_match __P((struct device *, struct cfdata *, void *)); 61 62 struct cfattach wdsc_pcc_ca = { 63 sizeof(struct sbic_softc), wdsc_pcc_match, wdsc_pcc_attach 64 }; 65 66 extern struct cfdriver wdsc_cd; 67 68 void wdsc_enintr __P((struct sbic_softc *)); 69 int wdsc_dmago __P((struct sbic_softc *, char *, int, int)); 70 int wdsc_dmanext __P((struct sbic_softc *)); 71 void wdsc_dmastop __P((struct sbic_softc *)); 72 int wdsc_dmaintr __P((void *)); 73 int wdsc_scsiintr __P((void *)); 74 75 /* 76 * Match for SCSI devices on the onboard WD33C93 chip 77 */ 78 int 79 wdsc_pcc_match(pdp, cf, auxp) 80 struct device *pdp; 81 struct cfdata *cf; 82 void *auxp; 83 { 84 struct pcc_attach_args *pa = auxp; 85 86 if (strcmp(pa->pa_name, wdsc_cd.cd_name)) 87 return (0); 88 89 pa->pa_ipl = cf->pcccf_ipl; 90 return (1); 91 } 92 93 /* 94 * Attach the wdsc driver 95 */ 96 void 97 wdsc_pcc_attach(pdp, dp, auxp) 98 struct device *pdp, *dp; 99 void *auxp; 100 { 101 struct sbic_softc *sc; 102 struct pcc_attach_args *pa; 103 bus_space_handle_t bush; 104 105 sc = (struct sbic_softc *)dp; 106 pa = auxp; 107 108 bus_space_map(pa->pa_bust, pa->pa_offset, 0x20, 0, &bush); 109 110 /* 111 * XXXSCW: We *need* an MI, bus_spaced WD33C93 driver... 112 */ 113 sc->sc_sbicp = (sbic_regmap_p) bush; 114 115 sc->sc_enintr = wdsc_enintr; 116 sc->sc_dmago = wdsc_dmago; 117 sc->sc_dmanext = wdsc_dmanext; 118 sc->sc_dmastop = wdsc_dmastop; 119 sc->sc_dmacmd = 0; 120 121 sc->sc_adapter.adapt_dev = &sc->sc_dev; 122 sc->sc_adapter.adapt_nchannels = 1; 123 sc->sc_adapter.adapt_openings = 7; 124 sc->sc_adapter.adapt_max_periph = 1; 125 sc->sc_adapter.adapt_ioctl = NULL; 126 sc->sc_adapter.adapt_minphys = sbic_minphys; 127 sc->sc_adapter.adapt_request = sbic_scsi_request; 128 129 sc->sc_channel.chan_adapter = &sc->sc_adapter; 130 sc->sc_channel.chan_bustype = &scsi_bustype; 131 sc->sc_channel.chan_channel = 0; 132 sc->sc_channel.chan_ntargets = 8; 133 sc->sc_channel.chan_nluns = 8; 134 sc->sc_channel.chan_id = 7; 135 136 printf(": WD33C93 SCSI, target %d\n", sc->sc_channel.chan_id); 137 138 /* 139 * Eveything is a valid dma address. 140 */ 141 sc->sc_dmamask = 0; 142 143 /* 144 * The onboard WD33C93 of the '147 is usually clocked at 10MHz... 145 * (We use 10 times this for accuracy in later calculations) 146 */ 147 sc->sc_clkfreq = 100; 148 149 /* 150 * Initialise the hardware 151 */ 152 sbicinit(sc); 153 154 /* 155 * Fix up the interrupts 156 */ 157 sc->sc_ipl = pa->pa_ipl & PCC_IMASK; 158 159 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, PCC_ICLEAR); 160 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, PCC_ICLEAR); 161 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 162 163 pccintr_establish(PCCV_DMA, wdsc_dmaintr, sc->sc_ipl, sc); 164 pccintr_establish(PCCV_SCSI, wdsc_scsiintr, sc->sc_ipl, sc); 165 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 166 sc->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 167 168 (void)config_found(dp, &sc->sc_channel, scsiprint); 169 } 170 171 /* 172 * Enable DMA interrupts 173 */ 174 void 175 wdsc_enintr(dev) 176 struct sbic_softc *dev; 177 { 178 dev->sc_flags |= SBICF_INTR; 179 180 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 181 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 182 } 183 184 /* 185 * Prime the hardware for a DMA transfer 186 */ 187 int 188 wdsc_dmago(dev, addr, count, flags) 189 struct sbic_softc *dev; 190 char *addr; 191 int count, flags; 192 { 193 /* 194 * Set up the command word based on flags 195 */ 196 if ( (flags & DMAGO_READ) == 0 ) 197 dev->sc_dmacmd = DMAC_CSR_ENABLE | DMAC_CSR_WRITE; 198 else 199 dev->sc_dmacmd = DMAC_CSR_ENABLE; 200 201 dev->sc_flags |= SBICF_INTR; 202 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 203 204 /* 205 * Prime the hardware. 206 * Note, it's probably not necessary to do this here, since dmanext 207 * is called just prior to the actual transfer. 208 */ 209 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 210 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 211 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 212 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 213 (u_int32_t) dev->sc_cur->dc_addr); 214 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 215 (u_int32_t) dev->sc_tcnt | (1 << 24)); 216 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 217 218 return(dev->sc_tcnt); 219 } 220 221 /* 222 * Prime the hardware for the next DMA transfer 223 */ 224 int 225 wdsc_dmanext(dev) 226 struct sbic_softc *dev; 227 { 228 if ( dev->sc_cur > dev->sc_last ) { 229 /* 230 * Shouldn't happen !! 231 */ 232 printf("wdsc_dmanext at end !!!\n"); 233 wdsc_dmastop(dev); 234 return(0); 235 } 236 237 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 238 239 /* 240 * Load the next DMA address 241 */ 242 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 243 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 244 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 245 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 246 (u_int32_t) dev->sc_cur->dc_addr); 247 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 248 (u_int32_t) dev->sc_tcnt | (1 << 24)); 249 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 250 251 return(dev->sc_tcnt); 252 } 253 254 /* 255 * Stop DMA, and disable interrupts 256 */ 257 void 258 wdsc_dmastop(dev) 259 struct sbic_softc *dev; 260 { 261 int s; 262 263 s = splbio(); 264 265 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 266 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, dev->sc_ipl | PCC_ICLEAR); 267 268 splx(s); 269 } 270 271 /* 272 * Come here following a DMA interrupt 273 */ 274 int 275 wdsc_dmaintr(arg) 276 void *arg; 277 { 278 struct sbic_softc *dev = arg; 279 int found = 0; 280 281 /* 282 * Really a DMA interrupt? 283 */ 284 if ( (pcc_reg_read(sys_pcc, PCCREG_DMA_INTR_CTRL) & 0x80) == 0 ) 285 return(0); 286 287 /* 288 * Was it a completion interrupt? 289 * XXXSCW Note: Support for other DMA interrupts is required, eg. buserr 290 */ 291 if ( pcc_reg_read(sys_pcc, PCCREG_DMA_CONTROL) & DMAC_CSR_DONE ) { 292 ++found; 293 294 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 295 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 296 } 297 298 return(found); 299 } 300 301 /* 302 * Come here for SCSI interrupts 303 */ 304 int 305 wdsc_scsiintr(arg) 306 void *arg; 307 { 308 struct sbic_softc *dev = arg; 309 int found; 310 311 /* 312 * Really a SCSI interrupt? 313 */ 314 if ( (pcc_reg_read(sys_pcc, PCCREG_SCSI_INTR_CTRL) & 0x80) == 0 ) 315 return(0); 316 317 /* 318 * Go handle it 319 */ 320 found = sbicintr(dev); 321 322 /* 323 * Acknowledge and clear the interrupt 324 */ 325 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 326 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 327 328 return(found); 329 } 330
Indexes created Tue Sep 30 20:09:53 GMT 2025