wdsc.c revision 1.25
1 /* $NetBSD: wdsc.c,v 1.25 2003/05/14 12:45:46 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Steve Woodford 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)wdsc.c 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsiconf.h> 47 48 #include <machine/cpu.h> 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 52 #include <mvme68k/dev/dmavar.h> 53 #include <mvme68k/dev/pccreg.h> 54 #include <mvme68k/dev/pccvar.h> 55 #include <mvme68k/dev/sbicreg.h> 56 #include <mvme68k/dev/sbicvar.h> 57 #include <mvme68k/dev/wdscreg.h> 58 59 void wdsc_pcc_attach __P((struct device *, struct device *, void *)); 60 int wdsc_pcc_match __P((struct device *, struct cfdata *, void *)); 61 62 CFATTACH_DECL(wdsc_pcc, sizeof(struct sbic_softc), 63 wdsc_pcc_match, wdsc_pcc_attach, NULL, NULL); 64 65 extern struct cfdriver wdsc_cd; 66 67 void wdsc_enintr __P((struct sbic_softc *)); 68 int wdsc_dmago __P((struct sbic_softc *, char *, int, int)); 69 int wdsc_dmanext __P((struct sbic_softc *)); 70 void wdsc_dmastop __P((struct sbic_softc *)); 71 int wdsc_dmaintr __P((void *)); 72 int wdsc_scsiintr __P((void *)); 73 74 /* 75 * Match for SCSI devices on the onboard WD33C93 chip 76 */ 77 int 78 wdsc_pcc_match(pdp, cf, auxp) 79 struct device *pdp; 80 struct cfdata *cf; 81 void *auxp; 82 { 83 struct pcc_attach_args *pa = auxp; 84 85 if (strcmp(pa->pa_name, wdsc_cd.cd_name)) 86 return (0); 87 88 pa->pa_ipl = cf->pcccf_ipl; 89 return (1); 90 } 91 92 /* 93 * Attach the wdsc driver 94 */ 95 void 96 wdsc_pcc_attach(pdp, dp, auxp) 97 struct device *pdp, *dp; 98 void *auxp; 99 { 100 struct sbic_softc *sc; 101 struct pcc_attach_args *pa; 102 bus_space_handle_t bush; 103 static struct evcnt evcnt; /* XXXSCW: Temporary hack */ 104 105 sc = (struct sbic_softc *)dp; 106 pa = auxp; 107 108 bus_space_map(pa->pa_bust, pa->pa_offset, 0x20, 0, &bush); 109 110 /* 111 * XXXSCW: We *need* an MI, bus_spaced WD33C93 driver... 112 */ 113 sc->sc_sbicp = (sbic_regmap_p) bush; 114 115 sc->sc_driver = (void *) &evcnt; 116 sc->sc_enintr = wdsc_enintr; 117 sc->sc_dmago = wdsc_dmago; 118 sc->sc_dmanext = wdsc_dmanext; 119 sc->sc_dmastop = wdsc_dmastop; 120 sc->sc_dmacmd = 0; 121 122 sc->sc_adapter.adapt_dev = &sc->sc_dev; 123 sc->sc_adapter.adapt_nchannels = 1; 124 sc->sc_adapter.adapt_openings = 7; 125 sc->sc_adapter.adapt_max_periph = 1; 126 sc->sc_adapter.adapt_ioctl = NULL; 127 sc->sc_adapter.adapt_minphys = sbic_minphys; 128 sc->sc_adapter.adapt_request = sbic_scsi_request; 129 130 sc->sc_channel.chan_adapter = &sc->sc_adapter; 131 sc->sc_channel.chan_bustype = &scsi_bustype; 132 sc->sc_channel.chan_channel = 0; 133 sc->sc_channel.chan_ntargets = 8; 134 sc->sc_channel.chan_nluns = 8; 135 sc->sc_channel.chan_id = 7; 136 137 printf(": WD33C93 SCSI, target %d\n", sc->sc_channel.chan_id); 138 139 /* 140 * Everything is a valid DMA address. 141 */ 142 sc->sc_dmamask = 0; 143 144 /* 145 * The onboard WD33C93 of the '147 is usually clocked at 10MHz... 146 * (We use 10 times this for accuracy in later calculations) 147 */ 148 sc->sc_clkfreq = 100; 149 150 /* 151 * Initialise the hardware 152 */ 153 sbicinit(sc); 154 155 /* 156 * Fix up the interrupts 157 */ 158 sc->sc_ipl = pa->pa_ipl & PCC_IMASK; 159 160 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, PCC_ICLEAR); 161 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, PCC_ICLEAR); 162 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 163 164 evcnt_attach_dynamic(&evcnt, EVCNT_TYPE_INTR, pccintr_evcnt(sc->sc_ipl), 165 "disk", sc->sc_dev.dv_xname); 166 pccintr_establish(PCCV_DMA, wdsc_dmaintr, sc->sc_ipl, sc, &evcnt); 167 pccintr_establish(PCCV_SCSI, wdsc_scsiintr, sc->sc_ipl, sc, &evcnt); 168 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 169 sc->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 170 171 (void)config_found(dp, &sc->sc_channel, scsiprint); 172 } 173 174 /* 175 * Enable DMA interrupts 176 */ 177 void 178 wdsc_enintr(dev) 179 struct sbic_softc *dev; 180 { 181 dev->sc_flags |= SBICF_INTR; 182 183 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 184 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 185 } 186 187 /* 188 * Prime the hardware for a DMA transfer 189 */ 190 int 191 wdsc_dmago(dev, addr, count, flags) 192 struct sbic_softc *dev; 193 char *addr; 194 int count, flags; 195 { 196 /* 197 * Set up the command word based on flags 198 */ 199 if ( (flags & DMAGO_READ) == 0 ) 200 dev->sc_dmacmd = DMAC_CSR_ENABLE | DMAC_CSR_WRITE; 201 else 202 dev->sc_dmacmd = DMAC_CSR_ENABLE; 203 204 dev->sc_flags |= SBICF_INTR; 205 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 206 207 /* 208 * Prime the hardware. 209 * Note, it's probably not necessary to do this here, since dmanext 210 * is called just prior to the actual transfer. 211 */ 212 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 213 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 214 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 215 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 216 (u_int32_t) dev->sc_cur->dc_addr); 217 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 218 (u_int32_t) dev->sc_tcnt | (1 << 24)); 219 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 220 221 return(dev->sc_tcnt); 222 } 223 224 /* 225 * Prime the hardware for the next DMA transfer 226 */ 227 int 228 wdsc_dmanext(dev) 229 struct sbic_softc *dev; 230 { 231 if ( dev->sc_cur > dev->sc_last ) { 232 /* 233 * Shouldn't happen !! 234 */ 235 printf("wdsc_dmanext at end !!!\n"); 236 wdsc_dmastop(dev); 237 return(0); 238 } 239 240 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 241 242 /* 243 * Load the next DMA address 244 */ 245 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 246 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 247 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 248 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 249 (u_int32_t) dev->sc_cur->dc_addr); 250 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 251 (u_int32_t) dev->sc_tcnt | (1 << 24)); 252 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 253 254 return(dev->sc_tcnt); 255 } 256 257 /* 258 * Stop DMA, and disable interrupts 259 */ 260 void 261 wdsc_dmastop(dev) 262 struct sbic_softc *dev; 263 { 264 int s; 265 266 s = splbio(); 267 268 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 269 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, dev->sc_ipl | PCC_ICLEAR); 270 271 splx(s); 272 } 273 274 /* 275 * Come here following a DMA interrupt 276 */ 277 int 278 wdsc_dmaintr(arg) 279 void *arg; 280 { 281 struct sbic_softc *dev = arg; 282 int found = 0; 283 284 /* 285 * Really a DMA interrupt? 286 */ 287 if ( (pcc_reg_read(sys_pcc, PCCREG_DMA_INTR_CTRL) & 0x80) == 0 ) 288 return(0); 289 290 /* 291 * Was it a completion interrupt? 292 * XXXSCW Note: Support for other DMA interrupts is required, eg. buserr 293 */ 294 if ( pcc_reg_read(sys_pcc, PCCREG_DMA_CONTROL) & DMAC_CSR_DONE ) { 295 ++found; 296 297 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 298 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 299 } 300 301 return(found); 302 } 303 304 /* 305 * Come here for SCSI interrupts 306 */ 307 int 308 wdsc_scsiintr(arg) 309 void *arg; 310 { 311 struct sbic_softc *dev = arg; 312 int found; 313 314 /* 315 * Really a SCSI interrupt? 316 */ 317 if ( (pcc_reg_read(sys_pcc, PCCREG_SCSI_INTR_CTRL) & 0x80) == 0 ) 318 return(0); 319 320 /* 321 * Go handle it 322 */ 323 found = sbicintr(dev); 324 325 /* 326 * Acknowledge and clear the interrupt 327 */ 328 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 329 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 330 331 return(found); 332 } 333
Indexes created Tue Sep 30 20:09:53 GMT 2025