wdsc.c revision 1.26
1 /* $NetBSD: wdsc.c,v 1.26 2003/07/15 02:43:47 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Steve Woodford 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)wdsc.c 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: wdsc.c,v 1.26 2003/07/15 02:43:47 lukem Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 51 #include <machine/cpu.h> 52 #include <machine/bus.h> 53 #include <machine/autoconf.h> 54 55 #include <mvme68k/dev/dmavar.h> 56 #include <mvme68k/dev/pccreg.h> 57 #include <mvme68k/dev/pccvar.h> 58 #include <mvme68k/dev/sbicreg.h> 59 #include <mvme68k/dev/sbicvar.h> 60 #include <mvme68k/dev/wdscreg.h> 61 62 void wdsc_pcc_attach __P((struct device *, struct device *, void *)); 63 int wdsc_pcc_match __P((struct device *, struct cfdata *, void *)); 64 65 CFATTACH_DECL(wdsc_pcc, sizeof(struct sbic_softc), 66 wdsc_pcc_match, wdsc_pcc_attach, NULL, NULL); 67 68 extern struct cfdriver wdsc_cd; 69 70 void wdsc_enintr __P((struct sbic_softc *)); 71 int wdsc_dmago __P((struct sbic_softc *, char *, int, int)); 72 int wdsc_dmanext __P((struct sbic_softc *)); 73 void wdsc_dmastop __P((struct sbic_softc *)); 74 int wdsc_dmaintr __P((void *)); 75 int wdsc_scsiintr __P((void *)); 76 77 /* 78 * Match for SCSI devices on the onboard WD33C93 chip 79 */ 80 int 81 wdsc_pcc_match(pdp, cf, auxp) 82 struct device *pdp; 83 struct cfdata *cf; 84 void *auxp; 85 { 86 struct pcc_attach_args *pa = auxp; 87 88 if (strcmp(pa->pa_name, wdsc_cd.cd_name)) 89 return (0); 90 91 pa->pa_ipl = cf->pcccf_ipl; 92 return (1); 93 } 94 95 /* 96 * Attach the wdsc driver 97 */ 98 void 99 wdsc_pcc_attach(pdp, dp, auxp) 100 struct device *pdp, *dp; 101 void *auxp; 102 { 103 struct sbic_softc *sc; 104 struct pcc_attach_args *pa; 105 bus_space_handle_t bush; 106 static struct evcnt evcnt; /* XXXSCW: Temporary hack */ 107 108 sc = (struct sbic_softc *)dp; 109 pa = auxp; 110 111 bus_space_map(pa->pa_bust, pa->pa_offset, 0x20, 0, &bush); 112 113 /* 114 * XXXSCW: We *need* an MI, bus_spaced WD33C93 driver... 115 */ 116 sc->sc_sbicp = (sbic_regmap_p) bush; 117 118 sc->sc_driver = (void *) &evcnt; 119 sc->sc_enintr = wdsc_enintr; 120 sc->sc_dmago = wdsc_dmago; 121 sc->sc_dmanext = wdsc_dmanext; 122 sc->sc_dmastop = wdsc_dmastop; 123 sc->sc_dmacmd = 0; 124 125 sc->sc_adapter.adapt_dev = &sc->sc_dev; 126 sc->sc_adapter.adapt_nchannels = 1; 127 sc->sc_adapter.adapt_openings = 7; 128 sc->sc_adapter.adapt_max_periph = 1; 129 sc->sc_adapter.adapt_ioctl = NULL; 130 sc->sc_adapter.adapt_minphys = sbic_minphys; 131 sc->sc_adapter.adapt_request = sbic_scsi_request; 132 133 sc->sc_channel.chan_adapter = &sc->sc_adapter; 134 sc->sc_channel.chan_bustype = &scsi_bustype; 135 sc->sc_channel.chan_channel = 0; 136 sc->sc_channel.chan_ntargets = 8; 137 sc->sc_channel.chan_nluns = 8; 138 sc->sc_channel.chan_id = 7; 139 140 printf(": WD33C93 SCSI, target %d\n", sc->sc_channel.chan_id); 141 142 /* 143 * Everything is a valid DMA address. 144 */ 145 sc->sc_dmamask = 0; 146 147 /* 148 * The onboard WD33C93 of the '147 is usually clocked at 10MHz... 149 * (We use 10 times this for accuracy in later calculations) 150 */ 151 sc->sc_clkfreq = 100; 152 153 /* 154 * Initialise the hardware 155 */ 156 sbicinit(sc); 157 158 /* 159 * Fix up the interrupts 160 */ 161 sc->sc_ipl = pa->pa_ipl & PCC_IMASK; 162 163 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, PCC_ICLEAR); 164 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, PCC_ICLEAR); 165 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 166 167 evcnt_attach_dynamic(&evcnt, EVCNT_TYPE_INTR, pccintr_evcnt(sc->sc_ipl), 168 "disk", sc->sc_dev.dv_xname); 169 pccintr_establish(PCCV_DMA, wdsc_dmaintr, sc->sc_ipl, sc, &evcnt); 170 pccintr_establish(PCCV_SCSI, wdsc_scsiintr, sc->sc_ipl, sc, &evcnt); 171 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 172 sc->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 173 174 (void)config_found(dp, &sc->sc_channel, scsiprint); 175 } 176 177 /* 178 * Enable DMA interrupts 179 */ 180 void 181 wdsc_enintr(dev) 182 struct sbic_softc *dev; 183 { 184 dev->sc_flags |= SBICF_INTR; 185 186 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 187 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 188 } 189 190 /* 191 * Prime the hardware for a DMA transfer 192 */ 193 int 194 wdsc_dmago(dev, addr, count, flags) 195 struct sbic_softc *dev; 196 char *addr; 197 int count, flags; 198 { 199 /* 200 * Set up the command word based on flags 201 */ 202 if ( (flags & DMAGO_READ) == 0 ) 203 dev->sc_dmacmd = DMAC_CSR_ENABLE | DMAC_CSR_WRITE; 204 else 205 dev->sc_dmacmd = DMAC_CSR_ENABLE; 206 207 dev->sc_flags |= SBICF_INTR; 208 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 209 210 /* 211 * Prime the hardware. 212 * Note, it's probably not necessary to do this here, since dmanext 213 * is called just prior to the actual transfer. 214 */ 215 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 216 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 217 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 218 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 219 (u_int32_t) dev->sc_cur->dc_addr); 220 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 221 (u_int32_t) dev->sc_tcnt | (1 << 24)); 222 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 223 224 return(dev->sc_tcnt); 225 } 226 227 /* 228 * Prime the hardware for the next DMA transfer 229 */ 230 int 231 wdsc_dmanext(dev) 232 struct sbic_softc *dev; 233 { 234 if ( dev->sc_cur > dev->sc_last ) { 235 /* 236 * Shouldn't happen !! 237 */ 238 printf("wdsc_dmanext at end !!!\n"); 239 wdsc_dmastop(dev); 240 return(0); 241 } 242 243 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 244 245 /* 246 * Load the next DMA address 247 */ 248 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 249 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 250 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 251 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 252 (u_int32_t) dev->sc_cur->dc_addr); 253 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 254 (u_int32_t) dev->sc_tcnt | (1 << 24)); 255 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 256 257 return(dev->sc_tcnt); 258 } 259 260 /* 261 * Stop DMA, and disable interrupts 262 */ 263 void 264 wdsc_dmastop(dev) 265 struct sbic_softc *dev; 266 { 267 int s; 268 269 s = splbio(); 270 271 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 272 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, dev->sc_ipl | PCC_ICLEAR); 273 274 splx(s); 275 } 276 277 /* 278 * Come here following a DMA interrupt 279 */ 280 int 281 wdsc_dmaintr(arg) 282 void *arg; 283 { 284 struct sbic_softc *dev = arg; 285 int found = 0; 286 287 /* 288 * Really a DMA interrupt? 289 */ 290 if ( (pcc_reg_read(sys_pcc, PCCREG_DMA_INTR_CTRL) & 0x80) == 0 ) 291 return(0); 292 293 /* 294 * Was it a completion interrupt? 295 * XXXSCW Note: Support for other DMA interrupts is required, eg. buserr 296 */ 297 if ( pcc_reg_read(sys_pcc, PCCREG_DMA_CONTROL) & DMAC_CSR_DONE ) { 298 ++found; 299 300 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 301 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 302 } 303 304 return(found); 305 } 306 307 /* 308 * Come here for SCSI interrupts 309 */ 310 int 311 wdsc_scsiintr(arg) 312 void *arg; 313 { 314 struct sbic_softc *dev = arg; 315 int found; 316 317 /* 318 * Really a SCSI interrupt? 319 */ 320 if ( (pcc_reg_read(sys_pcc, PCCREG_SCSI_INTR_CTRL) & 0x80) == 0 ) 321 return(0); 322 323 /* 324 * Go handle it 325 */ 326 found = sbicintr(dev); 327 328 /* 329 * Acknowledge and clear the interrupt 330 */ 331 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 332 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 333 334 return(found); 335 } 336
Indexes created Tue Sep 30 20:09:53 GMT 2025