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wdsc.c revision 1.9
      1 /*	$NetBSD: wdsc.c,v 1.9 1997/03/19 16:24:43 gwr Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996 Steve Woodford
      5  * Copyright (c) 1982, 1990 The Regents of the University of California.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *  This product includes software developed by the University of
     19  *  California, Berkeley and its contributors.
     20  * 4. Neither the name of the University nor the names of its contributors
     21  *    may be used to endorse or promote products derived from this software
     22  *    without specific prior written permission.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     34  * SUCH DAMAGE.
     35  *
     36  *  @(#)wdsc.c
     37  */
     38 
     39 #include <sys/param.h>
     40 #include <sys/systm.h>
     41 #include <sys/kernel.h>
     42 #include <sys/device.h>
     43 
     44 #include <scsi/scsi_all.h>
     45 #include <scsi/scsiconf.h>
     46 
     47 #include <machine/autoconf.h>
     48 
     49 #include <mvme68k/dev/dmavar.h>
     50 #include <mvme68k/dev/pccreg.h>
     51 #include <mvme68k/dev/pccvar.h>
     52 #include <mvme68k/dev/sbicreg.h>
     53 #include <mvme68k/dev/sbicvar.h>
     54 #include <mvme68k/dev/wdscreg.h>
     55 
     56 void    wdsc_pcc_attach __P((struct device *, struct device *, void *));
     57 int     wdsc_pcc_match  __P((struct device *, struct cfdata *, void *));
     58 
     59 void    wdsc_enintr     __P((struct sbic_softc *));
     60 int     wdsc_dmago      __P((struct sbic_softc *, char *, int, int));
     61 int     wdsc_dmanext    __P((struct sbic_softc *));
     62 void    wdsc_dmastop    __P((struct sbic_softc *));
     63 int     wdsc_dmaintr    __P((void *));
     64 int     wdsc_scsiintr   __P((void *));
     65 
     66 struct scsi_adapter wdsc_scsiswitch = {
     67     sbic_scsicmd,
     68     sbic_minphys,
     69     0,          /* no lun support */
     70     0,          /* no lun support */
     71 };
     72 
     73 struct scsi_device wdsc_scsidev = {
     74     NULL,       /* use default error handler */
     75     NULL,       /* do not have a start functio */
     76     NULL,       /* have no async handler */
     77     NULL,       /* Use default done routine */
     78 };
     79 
     80 struct cfattach wdsc_pcc_ca = {
     81 	sizeof(struct sbic_softc), wdsc_pcc_match, wdsc_pcc_attach
     82 };
     83 
     84 struct cfdriver wdsc_cd = {
     85     NULL, "wdsc", DV_DULL, NULL, 0
     86 };
     87 
     88 /*
     89  * Define 'scsi_nosync = 0x00' to enable sync SCSI mode.
     90  * This is untested as yet, use at your own risk...
     91  */
     92 u_long      scsi_nosync  = 0xff;
     93 int         shift_nosync = 0;
     94 
     95 /*
     96  * Match for SCSI devices on the onboard WD33C93 chip
     97  */
     98 int
     99 wdsc_pcc_match(pdp, cf, auxp)
    100     struct device *pdp;
    101 	struct cfdata *cf;
    102     void *auxp;
    103 {
    104     struct pcc_attach_args *pa = auxp;
    105 
    106     if (strcmp(pa->pa_name, wdsc_cd.cd_name))
    107 	return (0);
    108 
    109     pa->pa_ipl = cf->pcccf_ipl;
    110     return (1);
    111 }
    112 
    113 /*
    114  * Attach the wdsc driver
    115  */
    116 void
    117 wdsc_pcc_attach(pdp, dp, auxp)
    118     struct device *pdp, *dp;
    119     void *auxp;
    120 {
    121     struct sbic_softc   *sc = (struct sbic_softc *)dp;
    122     struct pcc_attach_args *pa = auxp;
    123     static int          attached = 0;
    124     int tmp;
    125 
    126     if ( attached )
    127         panic("wdsc: Driver already attached!");
    128 
    129     attached = 1;
    130 
    131     sc->sc_enintr  = wdsc_enintr;
    132     sc->sc_dmago   = wdsc_dmago;
    133     sc->sc_dmanext = wdsc_dmanext;
    134     sc->sc_dmastop = wdsc_dmastop;
    135     sc->sc_dmacmd  = 0;
    136 
    137     sc->sc_link.channel        = SCSI_CHANNEL_ONLY_ONE;
    138     sc->sc_link.adapter_softc  = sc;
    139     sc->sc_link.adapter_target = 7;
    140     sc->sc_link.adapter        = &wdsc_scsiswitch;
    141     sc->sc_link.device         = &wdsc_scsidev;
    142     sc->sc_link.openings       = 2;
    143     sc->sc_link.max_target     = 7;
    144 
    145     printf(": WD33C93 SCSI, target %d\n", sc->sc_link.adapter_target);
    146 
    147     sc->sc_cregs = (volatile void *)sys_pcc;
    148     sc->sc_sbicp = (sbic_regmap_p) PCC_VADDR(pa->pa_offset);
    149 
    150     /*
    151      * Eveything is a valid dma address.
    152      */
    153     sc->sc_dmamask = 0;
    154 
    155     /*
    156      * The onboard WD33C93 of the '147 is usually clocked at 10MHz...
    157      * (We use 10 times this for accuracy in later calculations)
    158      */
    159     sc->sc_clkfreq = 100;
    160 
    161     /*
    162      * Initialise the hardware
    163      */
    164     sbicinit(sc);
    165 
    166     /*
    167      * Fix up the interrupts
    168      */
    169     sc->sc_ipl = pa->pa_ipl & PCC_IMASK;
    170 
    171     sys_pcc->scsi_int = sc->sc_ipl | PCC_ICLEAR;
    172     sys_pcc->dma_int  = sc->sc_ipl | PCC_ICLEAR;
    173     sys_pcc->dma_csr  = 0;
    174 
    175     pccintr_establish(PCCV_SCSID, wdsc_dmaintr,  sc->sc_ipl, sc);
    176     pccintr_establish(PCCV_SCSIP, wdsc_scsiintr, sc->sc_ipl, sc);
    177 
    178     sys_pcc->scsi_int = sc->sc_ipl | PCC_IENABLE | PCC_ICLEAR;
    179 
    180     /*
    181      * Attach all scsi units on us, watching for boot device
    182      * (see dk_establish).
    183      */
    184     tmp = bootpart;
    185     if (PCC_PADDR(pa->pa_offset) != bootaddr)
    186 	bootpart = -1;		/* invalid flag to dk_establish */
    187     (void)config_found(dp, &sc->sc_link, scsiprint);
    188     bootpart = tmp;		/* restore old value */
    189 }
    190 
    191 /*
    192  * Enable DMA interrupts
    193  */
    194 void
    195 wdsc_enintr(dev)
    196     struct sbic_softc *dev;
    197 {
    198     volatile struct pcc *pc = dev->sc_cregs;
    199 
    200     dev->sc_flags |= SBICF_INTR;
    201 
    202     pc->dma_int = dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR;
    203 }
    204 
    205 /*
    206  * Prime the hardware for a DMA transfer
    207  */
    208 int
    209 wdsc_dmago(dev, addr, count, flags)
    210     struct sbic_softc *dev;
    211     char *addr;
    212     int count, flags;
    213 {
    214     volatile struct pcc *pc = dev->sc_cregs;
    215 
    216     /*
    217      * Set up the command word based on flags
    218      */
    219     if ( (flags & DMAGO_READ) == 0 )
    220         dev->sc_dmacmd = DMAC_CSR_ENABLE | DMAC_CSR_WRITE;
    221     else
    222         dev->sc_dmacmd = DMAC_CSR_ENABLE;
    223 
    224     dev->sc_flags |= SBICF_INTR;
    225     dev->sc_tcnt   = dev->sc_cur->dc_count << 1;
    226 
    227     /*
    228      * Prime the hardware.
    229      * Note, it's probably not necessary to do this here, since dmanext
    230      * is called just prior to the actual transfer.
    231      */
    232     pc->dma_csr   = 0;
    233     pc->dma_int   = dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR;
    234     pc->dma_daddr = (unsigned long)dev->sc_cur->dc_addr;
    235     pc->dma_bcnt  = (unsigned long)dev->sc_tcnt | (1 << 24);
    236     pc->dma_csr   = dev->sc_dmacmd;
    237 
    238     return(dev->sc_tcnt);
    239 }
    240 
    241 /*
    242  * Prime the hardware for the next DMA transfer
    243  */
    244 int
    245 wdsc_dmanext(dev)
    246     struct sbic_softc *dev;
    247 {
    248     volatile struct pcc *pc = dev->sc_cregs;
    249 
    250     if ( dev->sc_cur > dev->sc_last ) {
    251         /*
    252          * Shouldn't happen !!
    253          */
    254         printf("wdsc_dmanext at end !!!\n");
    255         wdsc_dmastop(dev);
    256         return(0);
    257     }
    258 
    259     dev->sc_tcnt = dev->sc_cur->dc_count << 1;
    260 
    261     /*
    262      * Load the next DMA address
    263      */
    264     pc->dma_csr   = 0;
    265     pc->dma_int   = dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR;
    266     pc->dma_daddr = (unsigned long)dev->sc_cur->dc_addr;
    267     pc->dma_bcnt  = (unsigned long)dev->sc_tcnt | (1 << 24);
    268     pc->dma_csr   = dev->sc_dmacmd;
    269 
    270     return(dev->sc_tcnt);
    271 }
    272 
    273 /*
    274  * Stop DMA, and disable interrupts
    275  */
    276 void
    277 wdsc_dmastop(dev)
    278     struct sbic_softc *dev;
    279 {
    280     volatile struct pcc *pc = dev->sc_cregs;
    281     int                 s;
    282 
    283     s = splbio();
    284 
    285     pc->dma_csr    = 0;
    286     pc->dma_int    = dev->sc_ipl | PCC_ICLEAR;
    287 
    288     splx(s);
    289 }
    290 
    291 /*
    292  * Come here following a DMA interrupt
    293  */
    294 int
    295 wdsc_dmaintr(arg)
    296     void *arg;
    297 {
    298     struct sbic_softc *dev = arg;
    299     volatile struct pcc *pc = dev->sc_cregs;
    300     int                 found = 0;
    301 
    302     /*
    303      * Really a DMA interrupt?
    304      */
    305     if ( (pc->dma_int & 0x80) == 0 )
    306         return(0);
    307 
    308     /*
    309      * Was it a completion interrupt?
    310      * XXXSCW Note: Support for other DMA interrupts is required, eg. buserr
    311      */
    312     if ( pc->dma_csr & DMAC_CSR_DONE ) {
    313         ++found;
    314 
    315         pc->dma_int = dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR;
    316     }
    317 
    318     return(found);
    319 }
    320 
    321 /*
    322  * Come here for SCSI interrupts
    323  */
    324 int
    325 wdsc_scsiintr(arg)
    326     void *arg;
    327 {
    328     struct sbic_softc *dev = arg;
    329     volatile struct pcc *pc = dev->sc_cregs;
    330     int                 found;
    331 
    332     /*
    333      * Really a SCSI interrupt?
    334      */
    335     if ( (pc->scsi_int & 0x80) == 0 )
    336         return(0);
    337 
    338     /*
    339      * Go handle it
    340      */
    341     found = sbicintr(dev);
    342 
    343     /*
    344      * Acknowledge and clear the interrupt
    345      */
    346     pc->scsi_int = dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR;
    347 
    348     return(found);
    349 }
    350