zs.c revision 1.11
1 /* $NetBSD: zs.c,v 1.11 1996/12/17 22:30:13 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE 30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 66 #include <mvme68k/dev/zsvar.h> 67 68 /* 69 * Some warts needed by z8530tty.c - 70 * The default parity REALLY needs to be the same as the PROM uses, 71 * or you can not see messages done with printf during boot-up... 72 */ 73 int zs_def_cflag = (CREAD | CS8 | HUPCL); 74 /* XXX Shouldn't hardcode the minor number... */ 75 int zs_major = 12; 76 77 static u_long zs_sir; /* software interrupt cookie */ 78 79 /* Flags from zscnprobe() */ 80 static int zs_hwflags[NZSC][2]; 81 82 /* Default speed for each channel */ 83 static int zs_defspeed[NZSC][2] = { 84 { 9600, /* port 1 */ 85 9600 }, /* port 2 */ 86 { 9600, /* port 3 */ 87 9600 }, /* port 4 */ 88 }; 89 90 static struct zs_chanstate zs_conschan_store; 91 static struct zs_chanstate *zs_conschan; 92 93 u_char zs_init_reg[16] = { 94 0, /* 0: CMD (reset, etc.) */ 95 0, /* 1: No interrupts yet. */ 96 0x18 + ZSHARD_PRI, /* IVECT */ 97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 100 0, /* 6: TXSYNC/SYNCLO */ 101 0, /* 7: RXSYNC/SYNCHI */ 102 0, /* 8: alias for data port */ 103 ZSWR9_MASTER_IE, 104 0, /*10: Misc. TX/RX control bits */ 105 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 106 14, /*12: BAUDLO (default=9600) */ 107 0, /*13: BAUDHI (default=9600) */ 108 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 109 ZSWR15_BREAK_IE | ZSWR15_DCD_IE, 110 }; 111 112 113 /**************************************************************** 114 * Autoconfig 115 ****************************************************************/ 116 117 /* Definition of the driver for autoconfig. */ 118 static int zsc_print __P((void *, const char *name)); 119 120 struct cfdriver zsc_cd = { 121 NULL, "zsc", DV_DULL 122 }; 123 124 static int zs_get_speed __P((struct zs_chanstate *)); 125 126 127 /* 128 * Configure children of an SCC. 129 */ 130 void 131 zs_config(zsc, chan_addr) 132 struct zsc_softc *zsc; 133 struct zschan *(*chan_addr) __P((int, int)); 134 { 135 struct zsc_attach_args zsc_args; 136 volatile struct zschan *zc; 137 struct zs_chanstate *cs; 138 int zsc_unit, channel, s; 139 140 zsc_unit = zsc->zsc_dev.dv_unit; 141 printf(": Zilog 8530 SCC\n"); 142 143 /* 144 * Initialize software state for each channel. 145 */ 146 for (channel = 0; channel < 2; channel++) { 147 zsc_args.channel = channel; 148 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 149 cs = &zsc->zsc_cs_store[channel]; 150 zsc->zsc_cs[channel] = cs; 151 152 /* 153 * If we're the console, copy the channel state, and 154 * adjust the console channel pointer. 155 */ 156 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 157 bcopy(zs_conschan, cs, sizeof(struct zs_chanstate)); 158 zs_conschan = cs; 159 } else { 160 zc = (*chan_addr)(zsc_unit, channel); 161 cs->cs_reg_csr = &zc->zc_csr; 162 cs->cs_reg_data = &zc->zc_data; 163 bcopy(zs_init_reg, cs->cs_creg, 16); 164 bcopy(zs_init_reg, cs->cs_preg, 16); 165 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 166 } 167 cs->cs_defcflag = zs_def_cflag; 168 169 cs->cs_channel = channel; 170 cs->cs_private = NULL; 171 cs->cs_ops = &zsops_null; 172 cs->cs_brg_clk = PCLK / 16; 173 174 /* 175 * Clear the master interrupt enable. 176 * The INTENA is common to both channels, 177 * so just do it on the A channel. 178 */ 179 if (channel == 0) { 180 zs_write_reg(cs, 9, 0); 181 } 182 183 /* 184 * Look for a child driver for this channel. 185 * The child attach will setup the hardware. 186 */ 187 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 188 /* No sub-driver. Just reset it. */ 189 u_char reset = (channel == 0) ? 190 ZSWR9_A_RESET : ZSWR9_B_RESET; 191 s = splzs(); 192 zs_write_reg(cs, 9, reset); 193 splx(s); 194 } 195 } 196 197 /* 198 * Allocate a software interrupt cookie. Note that the argument 199 * "zsc" is never actually used in the software interrupt 200 * handler. 201 */ 202 if (zs_sir == 0) 203 zs_sir = allocate_sir(zssoft, zsc); 204 } 205 206 static int 207 zsc_print(aux, name) 208 void *aux; 209 const char *name; 210 { 211 struct zsc_attach_args *args = aux; 212 213 if (name != NULL) 214 printf("%s: ", name); 215 216 if (args->channel != -1) 217 printf(" channel %d", args->channel); 218 219 return UNCONF; 220 } 221 222 static int zssoftpending; 223 224 /* 225 * Our ZS chips all share a common, autovectored interrupt, 226 * so we have to look at all of them on each interrupt. 227 */ 228 int 229 zshard(arg) 230 void *arg; 231 { 232 register struct zsc_softc *zsc; 233 register int unit, rval; 234 235 rval = 0; 236 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 237 zsc = zsc_cd.cd_devs[unit]; 238 if (zsc == NULL) 239 continue; 240 rval |= zsc_intr_hard(zsc); 241 if ((zsc->zsc_cs[0]->cs_softreq) || 242 (zsc->zsc_cs[1]->cs_softreq)) 243 { 244 /* zsc_req_softint(zsc); */ 245 /* We are at splzs here, so no need to lock. */ 246 if (zssoftpending == 0) { 247 zssoftpending = zs_sir; 248 setsoftint(zs_sir); 249 } 250 } 251 } 252 return (rval); 253 } 254 255 /* 256 * Similar scheme as for zshard (look at all of them) 257 */ 258 int 259 zssoft(arg) 260 void *arg; 261 { 262 register struct zsc_softc *zsc; 263 register int unit; 264 265 /* This is not the only ISR on this IPL. */ 266 if (zssoftpending == 0) 267 return (0); 268 269 /* 270 * The soft intr. bit will be set by zshard only if 271 * the variable zssoftpending is zero. 272 */ 273 zssoftpending = 0; 274 275 for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) { 276 zsc = zsc_cd.cd_devs[unit]; 277 if (zsc == NULL) 278 continue; 279 (void) zsc_intr_soft(zsc); 280 } 281 return (1); 282 } 283 284 285 /* 286 * Compute the current baud rate given a ZSCC channel. 287 */ 288 static int 289 zs_get_speed(cs) 290 struct zs_chanstate *cs; 291 { 292 int tconst; 293 294 tconst = zs_read_reg(cs, 12); 295 tconst |= zs_read_reg(cs, 13) << 8; 296 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 297 } 298 299 /* 300 * MD functions for setting the baud rate and control modes. 301 */ 302 int 303 zs_set_speed(cs, bps) 304 struct zs_chanstate *cs; 305 int bps; /* bits per second */ 306 { 307 int tconst, real_bps; 308 309 if (bps == 0) 310 return (0); 311 312 #ifdef DIAGNOSTIC 313 if (cs->cs_brg_clk == 0) 314 panic("zs_set_speed"); 315 #endif 316 317 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 318 if (tconst < 0) 319 return (EINVAL); 320 321 /* Convert back to make sure we can do it. */ 322 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 323 324 /* XXX - Allow some tolerance here? */ 325 if (real_bps != bps) 326 return (EINVAL); 327 328 cs->cs_preg[12] = tconst; 329 cs->cs_preg[13] = tconst >> 8; 330 331 /* Caller will stuff the pending registers. */ 332 return (0); 333 } 334 335 int 336 zs_set_modes(cs, cflag) 337 struct zs_chanstate *cs; 338 int cflag; /* bits per second */ 339 { 340 int s; 341 342 /* 343 * Output hardware flow control on the chip is horrendous: 344 * if carrier detect drops, the receiver is disabled, and if 345 * CTS drops, the transmitter is stoped IN MID CHARACTER! 346 * Therefore, NEVER set the HFC bit, and instead use the 347 * status interrupt to detect CTS changes. 348 */ 349 s = splzs(); 350 if (cflag & CLOCAL) { 351 cs->cs_rr0_dcd = 0; 352 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; 353 } else { 354 cs->cs_rr0_dcd = ZSRR0_DCD; 355 cs->cs_preg[15] |= ZSWR15_DCD_IE; 356 } 357 if (cflag & CRTSCTS) { 358 cs->cs_wr5_dtr = ZSWR5_DTR; 359 cs->cs_wr5_rts = ZSWR5_RTS; 360 cs->cs_rr0_cts = ZSRR0_CTS; 361 cs->cs_preg[15] |= ZSWR15_CTS_IE; 362 } else { 363 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 364 cs->cs_wr5_rts = 0; 365 cs->cs_rr0_cts = 0; 366 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 367 } 368 splx(s); 369 370 /* Caller will stuff the pending registers. */ 371 return (0); 372 } 373 374 375 /* 376 * Read or write the chip with suitable delays. 377 */ 378 379 u_char 380 zs_read_reg(cs, reg) 381 struct zs_chanstate *cs; 382 u_char reg; 383 { 384 u_char val; 385 386 *cs->cs_reg_csr = reg; 387 ZS_DELAY(); 388 val = *cs->cs_reg_csr; 389 ZS_DELAY(); 390 return val; 391 } 392 393 void 394 zs_write_reg(cs, reg, val) 395 struct zs_chanstate *cs; 396 u_char reg, val; 397 { 398 *cs->cs_reg_csr = reg; 399 ZS_DELAY(); 400 *cs->cs_reg_csr = val; 401 ZS_DELAY(); 402 } 403 404 u_char zs_read_csr(cs) 405 struct zs_chanstate *cs; 406 { 407 register u_char val; 408 409 val = *cs->cs_reg_csr; 410 ZS_DELAY(); 411 return val; 412 } 413 414 void zs_write_csr(cs, val) 415 struct zs_chanstate *cs; 416 u_char val; 417 { 418 *cs->cs_reg_csr = val; 419 ZS_DELAY(); 420 } 421 422 u_char zs_read_data(cs) 423 struct zs_chanstate *cs; 424 { 425 register u_char val; 426 427 val = *cs->cs_reg_data; 428 ZS_DELAY(); 429 return val; 430 } 431 432 void zs_write_data(cs, val) 433 struct zs_chanstate *cs; 434 u_char val; 435 { 436 *cs->cs_reg_data = val; 437 ZS_DELAY(); 438 } 439 440 /**************************************************************** 441 * Console support functions (MVME specific!) 442 ****************************************************************/ 443 444 /* 445 * Polled input char. 446 */ 447 int 448 zs_getc(arg) 449 void *arg; 450 { 451 register struct zs_chanstate *cs = arg; 452 register int s, c, rr0, stat; 453 454 s = splhigh(); 455 top: 456 /* Wait for a character to arrive. */ 457 do { 458 rr0 = *cs->cs_reg_csr; 459 ZS_DELAY(); 460 } while ((rr0 & ZSRR0_RX_READY) == 0); 461 462 /* Read error register. */ 463 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 464 if (stat) { 465 zs_write_csr(cs, ZSM_RESET_ERR); 466 goto top; 467 } 468 469 /* Read character. */ 470 c = *cs->cs_reg_data; 471 ZS_DELAY(); 472 splx(s); 473 474 return (c); 475 } 476 477 /* 478 * Polled output char. 479 */ 480 void 481 zs_putc(arg, c) 482 void *arg; 483 int c; 484 { 485 register struct zs_chanstate *cs = arg; 486 register int s, rr0; 487 488 s = splhigh(); 489 /* Wait for transmitter to become ready. */ 490 do { 491 rr0 = *cs->cs_reg_csr; 492 ZS_DELAY(); 493 } while ((rr0 & ZSRR0_TX_READY) == 0); 494 495 *cs->cs_reg_data = c; 496 ZS_DELAY(); 497 splx(s); 498 } 499 500 /* 501 * Common parts of console init. 502 */ 503 void 504 zs_cnconfig(zsc_unit, channel, zc) 505 int zsc_unit, channel; 506 struct zschan *zc; 507 { 508 struct zs_chanstate *cs; 509 510 /* 511 * Pointer to channel state. Later, the console channel 512 * state is copied into the softc, and the console channel 513 * pointer adjusted to point to the new copy. 514 */ 515 zs_conschan = cs = &zs_conschan_store; 516 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 517 518 /* Setup temporary chanstate. */ 519 cs->cs_reg_csr = &zc->zc_csr; 520 cs->cs_reg_data = &zc->zc_data; 521 522 /* Initialize the pending registers. */ 523 bcopy(zs_init_reg, cs->cs_preg, 16); 524 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 525 526 /* XXX: Preserve BAUD rate from boot loader. */ 527 /* XXX: Also, why reset the chip here? -gwr */ 528 /* cs->cs_defspeed = zs_get_speed(cs); */ 529 cs->cs_defspeed = 9600; /* XXX */ 530 531 /* Clear the master interrupt enable. */ 532 zs_write_reg(cs, 9, 0); 533 534 /* Reset the whole SCC chip. */ 535 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 536 537 /* Copy "pending" to "current" and H/W. */ 538 zs_loadchannelregs(cs); 539 } 540 541 /* 542 * Polled console input putchar. 543 */ 544 int 545 zscngetc(dev) 546 dev_t dev; 547 { 548 register struct zs_chanstate *cs = zs_conschan; 549 register int c; 550 551 c = zs_getc(cs); 552 return (c); 553 } 554 555 /* 556 * Polled console output putchar. 557 */ 558 void 559 zscnputc(dev, c) 560 dev_t dev; 561 int c; 562 { 563 register struct zs_chanstate *cs = zs_conschan; 564 565 zs_putc(cs, c); 566 } 567 568 /* 569 * Handle user request to enter kernel debugger. 570 */ 571 void 572 zs_abort(cs) 573 struct zs_chanstate *cs; 574 { 575 int rr0; 576 577 /* Wait for end of break to avoid PROM abort. */ 578 /* XXX - Limit the wait? */ 579 do { 580 rr0 = *cs->cs_reg_csr; 581 ZS_DELAY(); 582 } while (rr0 & ZSRR0_BREAK); 583 584 mvme68k_abort("SERIAL LINE ABORT"); 585 } 586
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