zs.c revision 1.12
1 /* $NetBSD: zs.c,v 1.12 1997/02/05 14:06:58 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 66 #include <mvme68k/dev/zsvar.h> 67 68 /* 69 * Some warts needed by z8530tty.c - 70 * The default parity REALLY needs to be the same as the PROM uses, 71 * or you can not see messages done with printf during boot-up... 72 */ 73 int zs_def_cflag = (CREAD | CS8 | HUPCL); 74 /* XXX Shouldn't hardcode the minor number... */ 75 int zs_major = 12; 76 77 static u_long zs_sir; /* software interrupt cookie */ 78 79 /* Flags from zscnprobe() */ 80 static int zs_hwflags[NZSC][2]; 81 82 /* Default speed for each channel */ 83 static int zs_defspeed[NZSC][2] = { 84 { 9600, /* port 1 */ 85 9600 }, /* port 2 */ 86 { 9600, /* port 3 */ 87 9600 }, /* port 4 */ 88 }; 89 90 static struct zs_chanstate zs_conschan_store; 91 static struct zs_chanstate *zs_conschan; 92 93 u_char zs_init_reg[16] = { 94 0, /* 0: CMD (reset, etc.) */ 95 0, /* 1: No interrupts yet. */ 96 0x18 + ZSHARD_PRI, /* IVECT */ 97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 100 0, /* 6: TXSYNC/SYNCLO */ 101 0, /* 7: RXSYNC/SYNCHI */ 102 0, /* 8: alias for data port */ 103 ZSWR9_MASTER_IE, 104 0, /*10: Misc. TX/RX control bits */ 105 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 106 14, /*12: BAUDLO (default=9600) */ 107 0, /*13: BAUDHI (default=9600) */ 108 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 109 ZSWR15_BREAK_IE | ZSWR15_DCD_IE, 110 }; 111 112 113 /**************************************************************** 114 * Autoconfig 115 ****************************************************************/ 116 117 /* Definition of the driver for autoconfig. */ 118 static int zsc_print __P((void *, const char *name)); 119 120 struct cfdriver zsc_cd = { 121 NULL, "zsc", DV_DULL 122 }; 123 124 static int zs_get_speed __P((struct zs_chanstate *)); 125 126 127 /* 128 * Configure children of an SCC. 129 */ 130 void 131 zs_config(zsc, chan_addr) 132 struct zsc_softc *zsc; 133 struct zschan *(*chan_addr) __P((int, int)); 134 { 135 struct zsc_attach_args zsc_args; 136 volatile struct zschan *zc; 137 struct zs_chanstate *cs; 138 int zsc_unit, channel, s; 139 140 zsc_unit = zsc->zsc_dev.dv_unit; 141 printf(": Zilog 8530 SCC\n"); 142 143 /* 144 * Initialize software state for each channel. 145 */ 146 for (channel = 0; channel < 2; channel++) { 147 zsc_args.channel = channel; 148 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 149 cs = &zsc->zsc_cs_store[channel]; 150 zsc->zsc_cs[channel] = cs; 151 152 /* 153 * If we're the console, copy the channel state, and 154 * adjust the console channel pointer. 155 */ 156 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 157 bcopy(zs_conschan, cs, sizeof(struct zs_chanstate)); 158 zs_conschan = cs; 159 } else { 160 zc = (*chan_addr)(zsc_unit, channel); 161 cs->cs_reg_csr = &zc->zc_csr; 162 cs->cs_reg_data = &zc->zc_data; 163 bcopy(zs_init_reg, cs->cs_creg, 16); 164 bcopy(zs_init_reg, cs->cs_preg, 16); 165 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 166 } 167 cs->cs_defcflag = zs_def_cflag; 168 169 /* Make these correspond to cs_defcflag (-crtscts) */ 170 cs->cs_rr0_dcd = ZSRR0_DCD; 171 cs->cs_rr0_cts = 0; 172 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 173 cs->cs_wr5_rts = 0; 174 175 cs->cs_channel = channel; 176 cs->cs_private = NULL; 177 cs->cs_ops = &zsops_null; 178 cs->cs_brg_clk = PCLK / 16; 179 180 /* 181 * Clear the master interrupt enable. 182 * The INTENA is common to both channels, 183 * so just do it on the A channel. 184 */ 185 if (channel == 0) { 186 zs_write_reg(cs, 9, 0); 187 } 188 189 /* 190 * Look for a child driver for this channel. 191 * The child attach will setup the hardware. 192 */ 193 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 194 /* No sub-driver. Just reset it. */ 195 u_char reset = (channel == 0) ? 196 ZSWR9_A_RESET : ZSWR9_B_RESET; 197 s = splzs(); 198 zs_write_reg(cs, 9, reset); 199 splx(s); 200 } 201 } 202 203 /* 204 * Allocate a software interrupt cookie. Note that the argument 205 * "zsc" is never actually used in the software interrupt 206 * handler. 207 */ 208 if (zs_sir == 0) 209 zs_sir = allocate_sir(zssoft, zsc); 210 } 211 212 static int 213 zsc_print(aux, name) 214 void *aux; 215 const char *name; 216 { 217 struct zsc_attach_args *args = aux; 218 219 if (name != NULL) 220 printf("%s: ", name); 221 222 if (args->channel != -1) 223 printf(" channel %d", args->channel); 224 225 return UNCONF; 226 } 227 228 static int zssoftpending; 229 230 /* 231 * Our ZS chips all share a common, autovectored interrupt, 232 * so we have to look at all of them on each interrupt. 233 */ 234 int 235 zshard(arg) 236 void *arg; 237 { 238 register struct zsc_softc *zsc; 239 register int unit, rval; 240 241 rval = 0; 242 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 243 zsc = zsc_cd.cd_devs[unit]; 244 if (zsc == NULL) 245 continue; 246 rval |= zsc_intr_hard(zsc); 247 if ((zsc->zsc_cs[0]->cs_softreq) || 248 (zsc->zsc_cs[1]->cs_softreq)) 249 { 250 /* zsc_req_softint(zsc); */ 251 /* We are at splzs here, so no need to lock. */ 252 if (zssoftpending == 0) { 253 zssoftpending = zs_sir; 254 setsoftint(zs_sir); 255 } 256 } 257 } 258 return (rval); 259 } 260 261 /* 262 * Similar scheme as for zshard (look at all of them) 263 */ 264 int 265 zssoft(arg) 266 void *arg; 267 { 268 register struct zsc_softc *zsc; 269 register int unit; 270 271 /* This is not the only ISR on this IPL. */ 272 if (zssoftpending == 0) 273 return (0); 274 275 /* 276 * The soft intr. bit will be set by zshard only if 277 * the variable zssoftpending is zero. 278 */ 279 zssoftpending = 0; 280 281 for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) { 282 zsc = zsc_cd.cd_devs[unit]; 283 if (zsc == NULL) 284 continue; 285 (void) zsc_intr_soft(zsc); 286 } 287 return (1); 288 } 289 290 291 /* 292 * Compute the current baud rate given a ZSCC channel. 293 */ 294 static int 295 zs_get_speed(cs) 296 struct zs_chanstate *cs; 297 { 298 int tconst; 299 300 tconst = zs_read_reg(cs, 12); 301 tconst |= zs_read_reg(cs, 13) << 8; 302 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 303 } 304 305 /* 306 * MD functions for setting the baud rate and control modes. 307 */ 308 int 309 zs_set_speed(cs, bps) 310 struct zs_chanstate *cs; 311 int bps; /* bits per second */ 312 { 313 int tconst, real_bps; 314 315 if (bps == 0) 316 return (0); 317 318 #ifdef DIAGNOSTIC 319 if (cs->cs_brg_clk == 0) 320 panic("zs_set_speed"); 321 #endif 322 323 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 324 if (tconst < 0) 325 return (EINVAL); 326 327 /* Convert back to make sure we can do it. */ 328 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 329 330 /* XXX - Allow some tolerance here? */ 331 if (real_bps != bps) 332 return (EINVAL); 333 334 cs->cs_preg[12] = tconst; 335 cs->cs_preg[13] = tconst >> 8; 336 337 /* Caller will stuff the pending registers. */ 338 return (0); 339 } 340 341 int 342 zs_set_modes(cs, cflag) 343 struct zs_chanstate *cs; 344 int cflag; /* bits per second */ 345 { 346 int s; 347 348 /* 349 * Output hardware flow control on the chip is horrendous: 350 * if carrier detect drops, the receiver is disabled, and if 351 * CTS drops, the transmitter is stoped IN MID CHARACTER! 352 * Therefore, NEVER set the HFC bit, and instead use the 353 * status interrupt to detect CTS changes. 354 */ 355 s = splzs(); 356 #if 0 /* XXX - See below. */ 357 if (cflag & CLOCAL) { 358 cs->cs_rr0_dcd = 0; 359 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; 360 } else { 361 /* XXX - Need to notice DCD change here... */ 362 cs->cs_rr0_dcd = ZSRR0_DCD; 363 cs->cs_preg[15] |= ZSWR15_DCD_IE; 364 } 365 #endif /* XXX */ 366 if (cflag & CRTSCTS) { 367 cs->cs_wr5_dtr = ZSWR5_DTR; 368 cs->cs_wr5_rts = ZSWR5_RTS; 369 cs->cs_rr0_cts = ZSRR0_CTS; 370 cs->cs_preg[15] |= ZSWR15_CTS_IE; 371 } else { 372 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 373 cs->cs_wr5_rts = 0; 374 cs->cs_rr0_cts = 0; 375 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 376 } 377 splx(s); 378 379 /* Caller will stuff the pending registers. */ 380 return (0); 381 } 382 383 384 /* 385 * Read or write the chip with suitable delays. 386 */ 387 388 u_char 389 zs_read_reg(cs, reg) 390 struct zs_chanstate *cs; 391 u_char reg; 392 { 393 u_char val; 394 395 *cs->cs_reg_csr = reg; 396 ZS_DELAY(); 397 val = *cs->cs_reg_csr; 398 ZS_DELAY(); 399 return val; 400 } 401 402 void 403 zs_write_reg(cs, reg, val) 404 struct zs_chanstate *cs; 405 u_char reg, val; 406 { 407 *cs->cs_reg_csr = reg; 408 ZS_DELAY(); 409 *cs->cs_reg_csr = val; 410 ZS_DELAY(); 411 } 412 413 u_char zs_read_csr(cs) 414 struct zs_chanstate *cs; 415 { 416 register u_char val; 417 418 val = *cs->cs_reg_csr; 419 ZS_DELAY(); 420 return val; 421 } 422 423 void zs_write_csr(cs, val) 424 struct zs_chanstate *cs; 425 u_char val; 426 { 427 *cs->cs_reg_csr = val; 428 ZS_DELAY(); 429 } 430 431 u_char zs_read_data(cs) 432 struct zs_chanstate *cs; 433 { 434 register u_char val; 435 436 val = *cs->cs_reg_data; 437 ZS_DELAY(); 438 return val; 439 } 440 441 void zs_write_data(cs, val) 442 struct zs_chanstate *cs; 443 u_char val; 444 { 445 *cs->cs_reg_data = val; 446 ZS_DELAY(); 447 } 448 449 /**************************************************************** 450 * Console support functions (MVME specific!) 451 ****************************************************************/ 452 453 /* 454 * Polled input char. 455 */ 456 int 457 zs_getc(arg) 458 void *arg; 459 { 460 register struct zs_chanstate *cs = arg; 461 register int s, c, rr0, stat; 462 463 s = splhigh(); 464 top: 465 /* Wait for a character to arrive. */ 466 do { 467 rr0 = *cs->cs_reg_csr; 468 ZS_DELAY(); 469 } while ((rr0 & ZSRR0_RX_READY) == 0); 470 471 /* Read error register. */ 472 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 473 if (stat) { 474 zs_write_csr(cs, ZSM_RESET_ERR); 475 goto top; 476 } 477 478 /* Read character. */ 479 c = *cs->cs_reg_data; 480 ZS_DELAY(); 481 splx(s); 482 483 return (c); 484 } 485 486 /* 487 * Polled output char. 488 */ 489 void 490 zs_putc(arg, c) 491 void *arg; 492 int c; 493 { 494 register struct zs_chanstate *cs = arg; 495 register int s, rr0; 496 497 s = splhigh(); 498 /* Wait for transmitter to become ready. */ 499 do { 500 rr0 = *cs->cs_reg_csr; 501 ZS_DELAY(); 502 } while ((rr0 & ZSRR0_TX_READY) == 0); 503 504 *cs->cs_reg_data = c; 505 ZS_DELAY(); 506 splx(s); 507 } 508 509 /* 510 * Common parts of console init. 511 */ 512 void 513 zs_cnconfig(zsc_unit, channel, zc) 514 int zsc_unit, channel; 515 struct zschan *zc; 516 { 517 struct zs_chanstate *cs; 518 519 /* 520 * Pointer to channel state. Later, the console channel 521 * state is copied into the softc, and the console channel 522 * pointer adjusted to point to the new copy. 523 */ 524 zs_conschan = cs = &zs_conschan_store; 525 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 526 527 /* Setup temporary chanstate. */ 528 cs->cs_reg_csr = &zc->zc_csr; 529 cs->cs_reg_data = &zc->zc_data; 530 531 /* Initialize the pending registers. */ 532 bcopy(zs_init_reg, cs->cs_preg, 16); 533 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 534 535 /* XXX: Preserve BAUD rate from boot loader. */ 536 /* XXX: Also, why reset the chip here? -gwr */ 537 /* cs->cs_defspeed = zs_get_speed(cs); */ 538 cs->cs_defspeed = 9600; /* XXX */ 539 540 /* Clear the master interrupt enable. */ 541 zs_write_reg(cs, 9, 0); 542 543 /* Reset the whole SCC chip. */ 544 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 545 546 /* Copy "pending" to "current" and H/W. */ 547 zs_loadchannelregs(cs); 548 } 549 550 /* 551 * Polled console input putchar. 552 */ 553 int 554 zscngetc(dev) 555 dev_t dev; 556 { 557 register struct zs_chanstate *cs = zs_conschan; 558 register int c; 559 560 c = zs_getc(cs); 561 return (c); 562 } 563 564 /* 565 * Polled console output putchar. 566 */ 567 void 568 zscnputc(dev, c) 569 dev_t dev; 570 int c; 571 { 572 register struct zs_chanstate *cs = zs_conschan; 573 574 zs_putc(cs, c); 575 } 576 577 /* 578 * Handle user request to enter kernel debugger. 579 */ 580 void 581 zs_abort(cs) 582 struct zs_chanstate *cs; 583 { 584 int rr0; 585 586 /* Wait for end of break to avoid PROM abort. */ 587 /* XXX - Limit the wait? */ 588 do { 589 rr0 = *cs->cs_reg_csr; 590 ZS_DELAY(); 591 } while (rr0 & ZSRR0_BREAK); 592 593 mvme68k_abort("SERIAL LINE ABORT"); 594 } 595
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