zs.c revision 1.16
1 /* $NetBSD: zs.c,v 1.16 1999/02/03 20:25:06 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 66 #include <mvme68k/dev/zsvar.h> 67 68 /* 69 * Some warts needed by z8530tty.c - 70 * The default parity REALLY needs to be the same as the PROM uses, 71 * or you can not see messages done with printf during boot-up... 72 */ 73 int zs_def_cflag = (CREAD | CS8 | HUPCL); 74 /* XXX Shouldn't hardcode the minor number... */ 75 int zs_major = 12; 76 77 static u_long zs_sir; /* software interrupt cookie */ 78 79 /* Flags from zscnprobe() */ 80 static int zs_hwflags[NZSC][2]; 81 82 /* Default speed for each channel */ 83 static int zs_defspeed[NZSC][2] = { 84 { 9600, /* port 1 */ 85 9600 }, /* port 2 */ 86 { 9600, /* port 3 */ 87 9600 }, /* port 4 */ 88 }; 89 90 static struct zs_chanstate zs_conschan_store; 91 static struct zs_chanstate *zs_conschan; 92 93 u_char zs_init_reg[16] = { 94 0, /* 0: CMD (reset, etc.) */ 95 0, /* 1: No interrupts yet. */ 96 0x18 + ZSHARD_PRI, /* IVECT */ 97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 100 0, /* 6: TXSYNC/SYNCLO */ 101 0, /* 7: RXSYNC/SYNCHI */ 102 0, /* 8: alias for data port */ 103 ZSWR9_MASTER_IE, 104 0, /*10: Misc. TX/RX control bits */ 105 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 106 14, /*12: BAUDLO (default=9600) */ 107 0, /*13: BAUDHI (default=9600) */ 108 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 109 ZSWR15_BREAK_IE, 110 }; 111 112 113 /**************************************************************** 114 * Autoconfig 115 ****************************************************************/ 116 117 /* Definition of the driver for autoconfig. */ 118 static int zsc_print __P((void *, const char *name)); 119 120 static int zs_get_speed __P((struct zs_chanstate *)); 121 122 extern struct cfdriver zsc_cd; 123 124 /* 125 * Configure children of an SCC. 126 */ 127 void 128 zs_config(zsc, chan_addr) 129 struct zsc_softc *zsc; 130 struct zschan *(*chan_addr) __P((int, int)); 131 { 132 struct zsc_attach_args zsc_args; 133 volatile struct zschan *zc; 134 struct zs_chanstate *cs; 135 int zsc_unit, channel, s; 136 137 zsc_unit = zsc->zsc_dev.dv_unit; 138 printf(": Zilog 8530 SCC\n"); 139 140 /* 141 * Initialize software state for each channel. 142 */ 143 for (channel = 0; channel < 2; channel++) { 144 zsc_args.channel = channel; 145 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 146 cs = &zsc->zsc_cs_store[channel]; 147 zsc->zsc_cs[channel] = cs; 148 149 /* 150 * If we're the console, copy the channel state, and 151 * adjust the console channel pointer. 152 */ 153 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 154 bcopy(zs_conschan, cs, sizeof(struct zs_chanstate)); 155 zs_conschan = cs; 156 } else { 157 zc = (*chan_addr)(zsc_unit, channel); 158 cs->cs_reg_csr = &zc->zc_csr; 159 cs->cs_reg_data = &zc->zc_data; 160 bcopy(zs_init_reg, cs->cs_creg, 16); 161 bcopy(zs_init_reg, cs->cs_preg, 16); 162 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 163 } 164 cs->cs_defcflag = zs_def_cflag; 165 166 /* Make these correspond to cs_defcflag (-crtscts) */ 167 cs->cs_rr0_dcd = ZSRR0_DCD; 168 cs->cs_rr0_cts = 0; 169 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 170 cs->cs_wr5_rts = 0; 171 172 cs->cs_channel = channel; 173 cs->cs_private = NULL; 174 cs->cs_ops = &zsops_null; 175 cs->cs_brg_clk = PCLK / 16; 176 177 /* 178 * Clear the master interrupt enable. 179 * The INTENA is common to both channels, 180 * so just do it on the A channel. 181 */ 182 if (channel == 0) { 183 zs_write_reg(cs, 9, 0); 184 } 185 186 /* 187 * Look for a child driver for this channel. 188 * The child attach will setup the hardware. 189 */ 190 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 191 /* No sub-driver. Just reset it. */ 192 u_char reset = (channel == 0) ? 193 ZSWR9_A_RESET : ZSWR9_B_RESET; 194 s = splzs(); 195 zs_write_reg(cs, 9, reset); 196 splx(s); 197 } 198 } 199 200 /* 201 * Allocate a software interrupt cookie. Note that the argument 202 * "zsc" is never actually used in the software interrupt 203 * handler. 204 */ 205 if (zs_sir == 0) 206 zs_sir = allocate_sir(zssoft, zsc); 207 } 208 209 static int 210 zsc_print(aux, name) 211 void *aux; 212 const char *name; 213 { 214 struct zsc_attach_args *args = aux; 215 216 if (name != NULL) 217 printf("%s: ", name); 218 219 if (args->channel != -1) 220 printf(" channel %d", args->channel); 221 222 return UNCONF; 223 } 224 225 static int zssoftpending; 226 227 /* 228 * Our ZS chips all share a common, autovectored interrupt, 229 * so we have to look at all of them on each interrupt. 230 */ 231 int 232 zshard(arg) 233 void *arg; 234 { 235 struct zsc_softc *zsc; 236 int unit, rval; 237 238 rval = 0; 239 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 240 zsc = zsc_cd.cd_devs[unit]; 241 if (zsc == NULL) 242 continue; 243 rval |= zsc_intr_hard(zsc); 244 if ((zsc->zsc_cs[0]->cs_softreq) || 245 (zsc->zsc_cs[1]->cs_softreq)) 246 { 247 /* zsc_req_softint(zsc); */ 248 /* We are at splzs here, so no need to lock. */ 249 if (zssoftpending == 0) { 250 zssoftpending = zs_sir; 251 setsoftint(zs_sir); 252 } 253 } 254 } 255 return (rval); 256 } 257 258 /* 259 * Similar scheme as for zshard (look at all of them) 260 */ 261 int 262 zssoft(arg) 263 void *arg; 264 { 265 struct zsc_softc *zsc; 266 int unit; 267 268 /* This is not the only ISR on this IPL. */ 269 if (zssoftpending == 0) 270 return (0); 271 272 /* 273 * The soft intr. bit will be set by zshard only if 274 * the variable zssoftpending is zero. 275 */ 276 zssoftpending = 0; 277 278 for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) { 279 zsc = zsc_cd.cd_devs[unit]; 280 if (zsc == NULL) 281 continue; 282 (void) zsc_intr_soft(zsc); 283 } 284 return (1); 285 } 286 287 288 /* 289 * Compute the current baud rate given a ZSCC channel. 290 */ 291 static int 292 zs_get_speed(cs) 293 struct zs_chanstate *cs; 294 { 295 int tconst; 296 297 tconst = zs_read_reg(cs, 12); 298 tconst |= zs_read_reg(cs, 13) << 8; 299 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 300 } 301 302 /* 303 * MD functions for setting the baud rate and control modes. 304 */ 305 int 306 zs_set_speed(cs, bps) 307 struct zs_chanstate *cs; 308 int bps; /* bits per second */ 309 { 310 int tconst, real_bps; 311 312 if (bps == 0) 313 return (0); 314 315 #ifdef DIAGNOSTIC 316 if (cs->cs_brg_clk == 0) 317 panic("zs_set_speed"); 318 #endif 319 320 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 321 if (tconst < 0) 322 return (EINVAL); 323 324 /* Convert back to make sure we can do it. */ 325 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 326 327 /* XXX - Allow some tolerance here? */ 328 if (real_bps != bps) 329 return (EINVAL); 330 331 cs->cs_preg[12] = tconst; 332 cs->cs_preg[13] = tconst >> 8; 333 334 /* Caller will stuff the pending registers. */ 335 return (0); 336 } 337 338 int 339 zs_set_modes(cs, cflag) 340 struct zs_chanstate *cs; 341 int cflag; /* bits per second */ 342 { 343 int s; 344 345 /* 346 * Output hardware flow control on the chip is horrendous: 347 * if carrier detect drops, the receiver is disabled, and if 348 * CTS drops, the transmitter is stoped IN MID CHARACTER! 349 * Therefore, NEVER set the HFC bit, and instead use the 350 * status interrupt to detect CTS changes. 351 */ 352 s = splzs(); 353 if ((cflag & (CLOCAL | MDMBUF)) != 0) 354 cs->cs_rr0_dcd = 0; 355 else 356 cs->cs_rr0_dcd = ZSRR0_DCD; 357 if ((cflag & CRTSCTS) != 0) { 358 cs->cs_wr5_dtr = ZSWR5_DTR; 359 cs->cs_wr5_rts = ZSWR5_RTS; 360 cs->cs_rr0_cts = ZSRR0_CTS; 361 } else if ((cflag & MDMBUF) != 0) { 362 cs->cs_wr5_dtr = 0; 363 cs->cs_wr5_rts = ZSWR5_DTR; 364 cs->cs_rr0_cts = ZSRR0_DCD; 365 } else { 366 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 367 cs->cs_wr5_rts = 0; 368 cs->cs_rr0_cts = 0; 369 } 370 splx(s); 371 372 /* Caller will stuff the pending registers. */ 373 return (0); 374 } 375 376 377 /* 378 * Read or write the chip with suitable delays. 379 */ 380 381 u_char 382 zs_read_reg(cs, reg) 383 struct zs_chanstate *cs; 384 u_char reg; 385 { 386 u_char val; 387 388 *cs->cs_reg_csr = reg; 389 ZS_DELAY(); 390 val = *cs->cs_reg_csr; 391 ZS_DELAY(); 392 return val; 393 } 394 395 void 396 zs_write_reg(cs, reg, val) 397 struct zs_chanstate *cs; 398 u_char reg, val; 399 { 400 *cs->cs_reg_csr = reg; 401 ZS_DELAY(); 402 *cs->cs_reg_csr = val; 403 ZS_DELAY(); 404 } 405 406 u_char zs_read_csr(cs) 407 struct zs_chanstate *cs; 408 { 409 u_char val; 410 411 val = *cs->cs_reg_csr; 412 ZS_DELAY(); 413 return val; 414 } 415 416 void zs_write_csr(cs, val) 417 struct zs_chanstate *cs; 418 u_char val; 419 { 420 *cs->cs_reg_csr = val; 421 ZS_DELAY(); 422 } 423 424 u_char zs_read_data(cs) 425 struct zs_chanstate *cs; 426 { 427 u_char val; 428 429 val = *cs->cs_reg_data; 430 ZS_DELAY(); 431 return val; 432 } 433 434 void zs_write_data(cs, val) 435 struct zs_chanstate *cs; 436 u_char val; 437 { 438 *cs->cs_reg_data = val; 439 ZS_DELAY(); 440 } 441 442 /**************************************************************** 443 * Console support functions (MVME specific!) 444 ****************************************************************/ 445 446 /* 447 * Polled input char. 448 */ 449 int 450 zs_getc(arg) 451 void *arg; 452 { 453 struct zs_chanstate *cs = arg; 454 int s, c, rr0, stat; 455 456 s = splhigh(); 457 top: 458 /* Wait for a character to arrive. */ 459 do { 460 rr0 = *cs->cs_reg_csr; 461 ZS_DELAY(); 462 } while ((rr0 & ZSRR0_RX_READY) == 0); 463 464 /* Read error register. */ 465 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 466 if (stat) { 467 zs_write_csr(cs, ZSM_RESET_ERR); 468 goto top; 469 } 470 471 /* Read character. */ 472 c = *cs->cs_reg_data; 473 ZS_DELAY(); 474 splx(s); 475 476 return (c); 477 } 478 479 /* 480 * Polled output char. 481 */ 482 void 483 zs_putc(arg, c) 484 void *arg; 485 int c; 486 { 487 struct zs_chanstate *cs = arg; 488 int s, rr0; 489 490 s = splhigh(); 491 /* Wait for transmitter to become ready. */ 492 do { 493 rr0 = *cs->cs_reg_csr; 494 ZS_DELAY(); 495 } while ((rr0 & ZSRR0_TX_READY) == 0); 496 497 *cs->cs_reg_data = c; 498 ZS_DELAY(); 499 splx(s); 500 } 501 502 /* 503 * Common parts of console init. 504 */ 505 void 506 zs_cnconfig(zsc_unit, channel, zc) 507 int zsc_unit, channel; 508 struct zschan *zc; 509 { 510 struct zs_chanstate *cs; 511 512 /* 513 * Pointer to channel state. Later, the console channel 514 * state is copied into the softc, and the console channel 515 * pointer adjusted to point to the new copy. 516 */ 517 zs_conschan = cs = &zs_conschan_store; 518 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 519 520 /* Setup temporary chanstate. */ 521 cs->cs_reg_csr = &zc->zc_csr; 522 cs->cs_reg_data = &zc->zc_data; 523 524 /* Initialize the pending registers. */ 525 bcopy(zs_init_reg, cs->cs_preg, 16); 526 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 527 528 /* XXX: Preserve BAUD rate from boot loader. */ 529 /* XXX: Also, why reset the chip here? -gwr */ 530 /* cs->cs_defspeed = zs_get_speed(cs); */ 531 cs->cs_defspeed = 9600; /* XXX */ 532 533 /* Clear the master interrupt enable. */ 534 zs_write_reg(cs, 9, 0); 535 536 /* Reset the whole SCC chip. */ 537 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 538 539 /* Copy "pending" to "current" and H/W. */ 540 zs_loadchannelregs(cs); 541 } 542 543 /* 544 * Polled console input putchar. 545 */ 546 int 547 zscngetc(dev) 548 dev_t dev; 549 { 550 struct zs_chanstate *cs = zs_conschan; 551 int c; 552 553 c = zs_getc(cs); 554 return (c); 555 } 556 557 /* 558 * Polled console output putchar. 559 */ 560 void 561 zscnputc(dev, c) 562 dev_t dev; 563 int c; 564 { 565 struct zs_chanstate *cs = zs_conschan; 566 567 zs_putc(cs, c); 568 } 569 570 /* 571 * Handle user request to enter kernel debugger. 572 */ 573 void 574 zs_abort(cs) 575 struct zs_chanstate *cs; 576 { 577 int rr0; 578 579 /* Wait for end of break to avoid PROM abort. */ 580 /* XXX - Limit the wait? */ 581 do { 582 rr0 = *cs->cs_reg_csr; 583 ZS_DELAY(); 584 } while (rr0 & ZSRR0_BREAK); 585 586 mvme68k_abort("SERIAL LINE ABORT"); 587 } 588
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