zs.c revision 1.19
1 /* $NetBSD: zs.c,v 1.19 2000/03/18 22:33:05 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 67 #include <mvme68k/dev/zsvar.h> 68 69 /* 70 * Some warts needed by z8530tty.c - 71 * The default parity REALLY needs to be the same as the PROM uses, 72 * or you can not see messages done with printf during boot-up... 73 */ 74 int zs_def_cflag = (CREAD | CS8 | HUPCL); 75 /* XXX Shouldn't hardcode the minor number... */ 76 int zs_major = 12; 77 78 static u_long zs_sir; /* software interrupt cookie */ 79 80 /* Flags from zscnprobe() */ 81 static int zs_hwflags[NZSC][2]; 82 83 /* Default speed for each channel */ 84 static int zs_defspeed[NZSC][2] = { 85 { 9600, /* port 1 */ 86 9600 }, /* port 2 */ 87 { 9600, /* port 3 */ 88 9600 }, /* port 4 */ 89 }; 90 91 static struct zs_chanstate zs_conschan_store; 92 static struct zs_chanstate *zs_conschan; 93 94 u_char zs_init_reg[16] = { 95 0, /* 0: CMD (reset, etc.) */ 96 0, /* 1: No interrupts yet. */ 97 0x18 + ZSHARD_PRI, /* IVECT */ 98 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 99 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 100 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 101 0, /* 6: TXSYNC/SYNCLO */ 102 0, /* 7: RXSYNC/SYNCHI */ 103 0, /* 8: alias for data port */ 104 ZSWR9_MASTER_IE, 105 0, /*10: Misc. TX/RX control bits */ 106 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 107 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 108 0, /*13: BAUDHI (default=9600) */ 109 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 110 ZSWR15_BREAK_IE, 111 }; 112 113 114 /**************************************************************** 115 * Autoconfig 116 ****************************************************************/ 117 118 /* Definition of the driver for autoconfig. */ 119 static int zsc_print __P((void *, const char *name)); 120 int zs_getc __P((void *)); 121 void zs_putc __P((void *, int)); 122 123 #if 0 124 static int zs_get_speed __P((struct zs_chanstate *)); 125 #endif 126 127 extern struct cfdriver zsc_cd; 128 129 cons_decl(zsc_pcc); 130 131 132 /* 133 * Configure children of an SCC. 134 */ 135 void 136 zs_config(zsc, bust, bush) 137 struct zsc_softc *zsc; 138 bus_space_tag_t bust; 139 bus_space_handle_t bush; 140 { 141 struct zsc_attach_args zsc_args; 142 struct zsdevice *zs; 143 volatile struct zschan *zc; 144 struct zs_chanstate *cs; 145 int zsc_unit, channel, s; 146 147 zsc_unit = zsc->zsc_dev.dv_unit; 148 printf(": Zilog 8530 SCC\n"); 149 150 zs = (struct zsdevice *) bush; /* XXXXXXXX */ 151 152 /* 153 * Initialize software state for each channel. 154 */ 155 for (channel = 0; channel < 2; channel++) { 156 zsc_args.channel = channel; 157 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 158 cs = &zsc->zsc_cs_store[channel]; 159 zsc->zsc_cs[channel] = cs; 160 161 /* 162 * If we're the console, copy the channel state, and 163 * adjust the console channel pointer. 164 */ 165 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 166 bcopy(zs_conschan, cs, sizeof(struct zs_chanstate)); 167 zs_conschan = cs; 168 } else { 169 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 170 cs->cs_reg_csr = &zc->zc_csr; 171 cs->cs_reg_data = &zc->zc_data; 172 bcopy(zs_init_reg, cs->cs_creg, 16); 173 bcopy(zs_init_reg, cs->cs_preg, 16); 174 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 175 } 176 cs->cs_defcflag = zs_def_cflag; 177 178 /* Make these correspond to cs_defcflag (-crtscts) */ 179 cs->cs_rr0_dcd = ZSRR0_DCD; 180 cs->cs_rr0_cts = 0; 181 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 182 cs->cs_wr5_rts = 0; 183 184 cs->cs_channel = channel; 185 cs->cs_private = NULL; 186 cs->cs_ops = &zsops_null; 187 cs->cs_brg_clk = PCLK / 16; 188 189 /* 190 * Clear the master interrupt enable. 191 * The INTENA is common to both channels, 192 * so just do it on the A channel. 193 */ 194 if (channel == 0) { 195 zs_write_reg(cs, 9, 0); 196 } 197 198 /* 199 * Look for a child driver for this channel. 200 * The child attach will setup the hardware. 201 */ 202 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 203 /* No sub-driver. Just reset it. */ 204 u_char reset = (channel == 0) ? 205 ZSWR9_A_RESET : ZSWR9_B_RESET; 206 s = splzs(); 207 zs_write_reg(cs, 9, reset); 208 splx(s); 209 } 210 } 211 212 /* 213 * Allocate a software interrupt cookie. Note that the argument 214 * "zsc" is never actually used in the software interrupt 215 * handler. 216 */ 217 if (zs_sir == 0) 218 zs_sir = allocate_sir(zssoft, zsc); 219 } 220 221 static int 222 zsc_print(aux, name) 223 void *aux; 224 const char *name; 225 { 226 struct zsc_attach_args *args = aux; 227 228 if (name != NULL) 229 printf("%s: ", name); 230 231 if (args->channel != -1) 232 printf(" channel %d", args->channel); 233 234 return UNCONF; 235 } 236 237 static int zssoftpending; 238 239 /* 240 * Our ZS chips all share a common, autovectored interrupt, 241 * so we have to look at all of them on each interrupt. 242 */ 243 int 244 zshard(arg) 245 void *arg; 246 { 247 struct zsc_softc *zsc; 248 int unit, rval; 249 250 rval = 0; 251 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 252 zsc = zsc_cd.cd_devs[unit]; 253 if (zsc == NULL) 254 continue; 255 rval |= zsc_intr_hard(zsc); 256 if ((zsc->zsc_cs[0]->cs_softreq) || 257 (zsc->zsc_cs[1]->cs_softreq)) 258 { 259 /* zsc_req_softint(zsc); */ 260 /* We are at splzs here, so no need to lock. */ 261 if (zssoftpending == 0) { 262 zssoftpending = zs_sir; 263 setsoftint(zs_sir); 264 } 265 } 266 } 267 return (rval); 268 } 269 270 /* 271 * Similar scheme as for zshard (look at all of them) 272 */ 273 void 274 zssoft(arg) 275 void *arg; 276 { 277 struct zsc_softc *zsc; 278 int unit; 279 280 /* This is not the only ISR on this IPL. */ 281 if (zssoftpending == 0) 282 return; 283 284 /* 285 * The soft intr. bit will be set by zshard only if 286 * the variable zssoftpending is zero. 287 */ 288 zssoftpending = 0; 289 290 for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) { 291 zsc = zsc_cd.cd_devs[unit]; 292 if (zsc == NULL) 293 continue; 294 (void) zsc_intr_soft(zsc); 295 } 296 } 297 298 #if 0 299 /* 300 * Compute the current baud rate given a ZSCC channel. 301 */ 302 static int 303 zs_get_speed(cs) 304 struct zs_chanstate *cs; 305 { 306 int tconst; 307 308 tconst = zs_read_reg(cs, 12); 309 tconst |= zs_read_reg(cs, 13) << 8; 310 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 311 } 312 #endif 313 314 /* 315 * MD functions for setting the baud rate and control modes. 316 */ 317 int 318 zs_set_speed(cs, bps) 319 struct zs_chanstate *cs; 320 int bps; /* bits per second */ 321 { 322 int tconst, real_bps; 323 324 if (bps == 0) 325 return (0); 326 327 #ifdef DIAGNOSTIC 328 if (cs->cs_brg_clk == 0) 329 panic("zs_set_speed"); 330 #endif 331 332 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 333 if (tconst < 0) 334 return (EINVAL); 335 336 /* Convert back to make sure we can do it. */ 337 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 338 339 /* XXX - Allow some tolerance here? */ 340 if (real_bps != bps) 341 return (EINVAL); 342 343 cs->cs_preg[12] = tconst; 344 cs->cs_preg[13] = tconst >> 8; 345 346 /* Caller will stuff the pending registers. */ 347 return (0); 348 } 349 350 int 351 zs_set_modes(cs, cflag) 352 struct zs_chanstate *cs; 353 int cflag; /* bits per second */ 354 { 355 int s; 356 357 /* 358 * Output hardware flow control on the chip is horrendous: 359 * if carrier detect drops, the receiver is disabled, and if 360 * CTS drops, the transmitter is stoped IN MID CHARACTER! 361 * Therefore, NEVER set the HFC bit, and instead use the 362 * status interrupt to detect CTS changes. 363 */ 364 s = splzs(); 365 cs->cs_rr0_pps = 0; 366 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 367 cs->cs_rr0_dcd = 0; 368 if ((cflag & MDMBUF) == 0) 369 cs->cs_rr0_pps = ZSRR0_DCD; 370 } else 371 cs->cs_rr0_dcd = ZSRR0_DCD; 372 if ((cflag & CRTSCTS) != 0) { 373 cs->cs_wr5_dtr = ZSWR5_DTR; 374 cs->cs_wr5_rts = ZSWR5_RTS; 375 cs->cs_rr0_cts = ZSRR0_CTS; 376 } else if ((cflag & MDMBUF) != 0) { 377 cs->cs_wr5_dtr = 0; 378 cs->cs_wr5_rts = ZSWR5_DTR; 379 cs->cs_rr0_cts = ZSRR0_DCD; 380 } else { 381 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 382 cs->cs_wr5_rts = 0; 383 cs->cs_rr0_cts = 0; 384 } 385 splx(s); 386 387 /* Caller will stuff the pending registers. */ 388 return (0); 389 } 390 391 392 /* 393 * Read or write the chip with suitable delays. 394 */ 395 396 u_char 397 zs_read_reg(cs, reg) 398 struct zs_chanstate *cs; 399 u_char reg; 400 { 401 u_char val; 402 403 *cs->cs_reg_csr = reg; 404 ZS_DELAY(); 405 val = *cs->cs_reg_csr; 406 ZS_DELAY(); 407 return val; 408 } 409 410 void 411 zs_write_reg(cs, reg, val) 412 struct zs_chanstate *cs; 413 u_char reg, val; 414 { 415 *cs->cs_reg_csr = reg; 416 ZS_DELAY(); 417 *cs->cs_reg_csr = val; 418 ZS_DELAY(); 419 } 420 421 u_char zs_read_csr(cs) 422 struct zs_chanstate *cs; 423 { 424 u_char val; 425 426 val = *cs->cs_reg_csr; 427 ZS_DELAY(); 428 return val; 429 } 430 431 void zs_write_csr(cs, val) 432 struct zs_chanstate *cs; 433 u_char val; 434 { 435 *cs->cs_reg_csr = val; 436 ZS_DELAY(); 437 } 438 439 u_char zs_read_data(cs) 440 struct zs_chanstate *cs; 441 { 442 u_char val; 443 444 val = *cs->cs_reg_data; 445 ZS_DELAY(); 446 return val; 447 } 448 449 void zs_write_data(cs, val) 450 struct zs_chanstate *cs; 451 u_char val; 452 { 453 *cs->cs_reg_data = val; 454 ZS_DELAY(); 455 } 456 457 /**************************************************************** 458 * Console support functions (MVME specific!) 459 ****************************************************************/ 460 461 /* 462 * Polled input char. 463 */ 464 int 465 zs_getc(arg) 466 void *arg; 467 { 468 struct zs_chanstate *cs = arg; 469 int s, c, rr0, stat; 470 471 s = splhigh(); 472 top: 473 /* Wait for a character to arrive. */ 474 do { 475 rr0 = *cs->cs_reg_csr; 476 ZS_DELAY(); 477 } while ((rr0 & ZSRR0_RX_READY) == 0); 478 479 /* Read error register. */ 480 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 481 if (stat) { 482 zs_write_csr(cs, ZSM_RESET_ERR); 483 goto top; 484 } 485 486 /* Read character. */ 487 c = *cs->cs_reg_data; 488 ZS_DELAY(); 489 splx(s); 490 491 return (c); 492 } 493 494 /* 495 * Polled output char. 496 */ 497 void 498 zs_putc(arg, c) 499 void *arg; 500 int c; 501 { 502 struct zs_chanstate *cs = arg; 503 int s, rr0; 504 505 s = splhigh(); 506 /* Wait for transmitter to become ready. */ 507 do { 508 rr0 = *cs->cs_reg_csr; 509 ZS_DELAY(); 510 } while ((rr0 & ZSRR0_TX_READY) == 0); 511 512 *cs->cs_reg_data = c; 513 ZS_DELAY(); 514 splx(s); 515 } 516 517 /* 518 * Common parts of console init. 519 */ 520 void 521 zs_cnconfig(zsc_unit, channel, bust, bush) 522 int zsc_unit, channel; 523 bus_space_tag_t bust; 524 bus_space_handle_t bush; 525 { 526 struct zs_chanstate *cs; 527 struct zsdevice *zs; 528 struct zschan *zc; 529 530 zs = (struct zsdevice *) bush; /* XXXXXXXX */ 531 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 532 533 /* 534 * Pointer to channel state. Later, the console channel 535 * state is copied into the softc, and the console channel 536 * pointer adjusted to point to the new copy. 537 */ 538 zs_conschan = cs = &zs_conschan_store; 539 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 540 541 /* Setup temporary chanstate. */ 542 cs->cs_reg_csr = &zc->zc_csr; 543 cs->cs_reg_data = &zc->zc_data; 544 545 /* Initialize the pending registers. */ 546 bcopy(zs_init_reg, cs->cs_preg, 16); 547 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 548 549 #if 0 550 /* XXX: Preserve BAUD rate from boot loader. */ 551 /* XXX: Also, why reset the chip here? -gwr */ 552 cs->cs_defspeed = zs_get_speed(cs); 553 #else 554 cs->cs_defspeed = 9600; /* XXX */ 555 #endif 556 557 /* Clear the master interrupt enable. */ 558 zs_write_reg(cs, 9, 0); 559 560 /* Reset the whole SCC chip. */ 561 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 562 563 /* Copy "pending" to "current" and H/W. */ 564 zs_loadchannelregs(cs); 565 } 566 567 /* 568 * Polled console input putchar. 569 */ 570 int 571 zsc_pcccngetc(dev) 572 dev_t dev; 573 { 574 struct zs_chanstate *cs = zs_conschan; 575 int c; 576 577 c = zs_getc(cs); 578 return (c); 579 } 580 581 /* 582 * Polled console output putchar. 583 */ 584 void 585 zsc_pcccnputc(dev, c) 586 dev_t dev; 587 int c; 588 { 589 struct zs_chanstate *cs = zs_conschan; 590 591 zs_putc(cs, c); 592 } 593 594 /* 595 * Handle user request to enter kernel debugger. 596 */ 597 void 598 zs_abort(cs) 599 struct zs_chanstate *cs; 600 { 601 int rr0; 602 603 /* Wait for end of break to avoid PROM abort. */ 604 /* XXX - Limit the wait? */ 605 do { 606 rr0 = *cs->cs_reg_csr; 607 ZS_DELAY(); 608 } while (rr0 & ZSRR0_BREAK); 609 610 mvme68k_abort("SERIAL LINE ABORT"); 611 } 612
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