zs.c revision 1.20
1 /* $NetBSD: zs.c,v 1.20 2000/07/20 20:40:37 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <mvme68k/dev/zsvar.h> 69 70 /* 71 * Some warts needed by z8530tty.c - 72 * The default parity REALLY needs to be the same as the PROM uses, 73 * or you can not see messages done with printf during boot-up... 74 */ 75 int zs_def_cflag = (CREAD | CS8 | HUPCL); 76 /* XXX Shouldn't hardcode the minor number... */ 77 int zs_major = 12; 78 79 /* Flags from zscnprobe() */ 80 static int zs_hwflags[NZSC][2]; 81 82 /* Default speed for each channel */ 83 static int zs_defspeed[NZSC][2] = { 84 { 9600, /* port 1 */ 85 9600 }, /* port 2 */ 86 { 9600, /* port 3 */ 87 9600 }, /* port 4 */ 88 }; 89 90 static struct zs_chanstate zs_conschan_store; 91 static struct zs_chanstate *zs_conschan; 92 93 u_char zs_init_reg[16] = { 94 0, /* 0: CMD (reset, etc.) */ 95 0, /* 1: No interrupts yet. */ 96 0x18 + ZSHARD_PRI, /* IVECT */ 97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 100 0, /* 6: TXSYNC/SYNCLO */ 101 0, /* 7: RXSYNC/SYNCHI */ 102 0, /* 8: alias for data port */ 103 ZSWR9_MASTER_IE, 104 0, /*10: Misc. TX/RX control bits */ 105 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 106 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 107 0, /*13: BAUDHI (default=9600) */ 108 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 109 ZSWR15_BREAK_IE, 110 }; 111 112 113 /**************************************************************** 114 * Autoconfig 115 ****************************************************************/ 116 117 /* Definition of the driver for autoconfig. */ 118 static int zsc_print __P((void *, const char *name)); 119 int zs_getc __P((void *)); 120 void zs_putc __P((void *, int)); 121 122 #if 0 123 static int zs_get_speed __P((struct zs_chanstate *)); 124 #endif 125 126 extern struct cfdriver zsc_cd; 127 128 cons_decl(zsc_pcc); 129 130 131 /* 132 * Configure children of an SCC. 133 */ 134 void 135 zs_config(zsc, bust, bush) 136 struct zsc_softc *zsc; 137 bus_space_tag_t bust; 138 bus_space_handle_t bush; 139 { 140 struct zsc_attach_args zsc_args; 141 struct zsdevice *zs; 142 volatile struct zschan *zc; 143 struct zs_chanstate *cs; 144 int zsc_unit, channel, s; 145 146 zsc_unit = zsc->zsc_dev.dv_unit; 147 printf(": Zilog 8530 SCC\n"); 148 149 zs = (struct zsdevice *) bush; /* XXXXXXXX */ 150 151 /* 152 * Initialize software state for each channel. 153 */ 154 for (channel = 0; channel < 2; channel++) { 155 zsc_args.channel = channel; 156 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 157 cs = &zsc->zsc_cs_store[channel]; 158 zsc->zsc_cs[channel] = cs; 159 160 /* 161 * If we're the console, copy the channel state, and 162 * adjust the console channel pointer. 163 */ 164 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 165 bcopy(zs_conschan, cs, sizeof(struct zs_chanstate)); 166 zs_conschan = cs; 167 } else { 168 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 169 cs->cs_reg_csr = &zc->zc_csr; 170 cs->cs_reg_data = &zc->zc_data; 171 bcopy(zs_init_reg, cs->cs_creg, 16); 172 bcopy(zs_init_reg, cs->cs_preg, 16); 173 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 174 } 175 cs->cs_defcflag = zs_def_cflag; 176 177 /* Make these correspond to cs_defcflag (-crtscts) */ 178 cs->cs_rr0_dcd = ZSRR0_DCD; 179 cs->cs_rr0_cts = 0; 180 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 181 cs->cs_wr5_rts = 0; 182 183 cs->cs_channel = channel; 184 cs->cs_private = NULL; 185 cs->cs_ops = &zsops_null; 186 cs->cs_brg_clk = PCLK / 16; 187 188 /* 189 * Clear the master interrupt enable. 190 * The INTENA is common to both channels, 191 * so just do it on the A channel. 192 */ 193 if (channel == 0) { 194 zs_write_reg(cs, 9, 0); 195 } 196 197 /* 198 * Look for a child driver for this channel. 199 * The child attach will setup the hardware. 200 */ 201 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 202 /* No sub-driver. Just reset it. */ 203 u_char reset = (channel == 0) ? 204 ZSWR9_A_RESET : ZSWR9_B_RESET; 205 s = splzs(); 206 zs_write_reg(cs, 9, reset); 207 splx(s); 208 } 209 } 210 211 /* 212 * Allocate a software interrupt cookie. 213 */ 214 zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL, 215 (void (*)(void *)) zsc_intr_soft, zsc); 216 assert(zsc->zsc_softintr_cookie); 217 } 218 219 static int 220 zsc_print(aux, name) 221 void *aux; 222 const char *name; 223 { 224 struct zsc_attach_args *args = aux; 225 226 if (name != NULL) 227 printf("%s: ", name); 228 229 if (args->channel != -1) 230 printf(" channel %d", args->channel); 231 232 return UNCONF; 233 } 234 235 /* 236 * Our ZS chips all share a common, autovectored interrupt, 237 * so we have to look at all of them on each interrupt. 238 */ 239 int 240 zshard(arg) 241 void *arg; 242 { 243 struct zsc_softc *zsc; 244 int unit, rval; 245 246 rval = 0; 247 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 248 zsc = zsc_cd.cd_devs[unit]; 249 if (zsc == NULL) 250 continue; 251 rval |= zsc_intr_hard(zsc); 252 if ((zsc->zsc_cs[0]->cs_softreq) || 253 (zsc->zsc_cs[1]->cs_softreq)) 254 softintr_schedule(zsc); 255 } 256 return (rval); 257 } 258 259 260 #if 0 261 /* 262 * Compute the current baud rate given a ZSCC channel. 263 */ 264 static int 265 zs_get_speed(cs) 266 struct zs_chanstate *cs; 267 { 268 int tconst; 269 270 tconst = zs_read_reg(cs, 12); 271 tconst |= zs_read_reg(cs, 13) << 8; 272 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 273 } 274 #endif 275 276 /* 277 * MD functions for setting the baud rate and control modes. 278 */ 279 int 280 zs_set_speed(cs, bps) 281 struct zs_chanstate *cs; 282 int bps; /* bits per second */ 283 { 284 int tconst, real_bps; 285 286 if (bps == 0) 287 return (0); 288 289 #ifdef DIAGNOSTIC 290 if (cs->cs_brg_clk == 0) 291 panic("zs_set_speed"); 292 #endif 293 294 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 295 if (tconst < 0) 296 return (EINVAL); 297 298 /* Convert back to make sure we can do it. */ 299 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 300 301 /* XXX - Allow some tolerance here? */ 302 if (real_bps != bps) 303 return (EINVAL); 304 305 cs->cs_preg[12] = tconst; 306 cs->cs_preg[13] = tconst >> 8; 307 308 /* Caller will stuff the pending registers. */ 309 return (0); 310 } 311 312 int 313 zs_set_modes(cs, cflag) 314 struct zs_chanstate *cs; 315 int cflag; /* bits per second */ 316 { 317 int s; 318 319 /* 320 * Output hardware flow control on the chip is horrendous: 321 * if carrier detect drops, the receiver is disabled, and if 322 * CTS drops, the transmitter is stoped IN MID CHARACTER! 323 * Therefore, NEVER set the HFC bit, and instead use the 324 * status interrupt to detect CTS changes. 325 */ 326 s = splzs(); 327 cs->cs_rr0_pps = 0; 328 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 329 cs->cs_rr0_dcd = 0; 330 if ((cflag & MDMBUF) == 0) 331 cs->cs_rr0_pps = ZSRR0_DCD; 332 } else 333 cs->cs_rr0_dcd = ZSRR0_DCD; 334 if ((cflag & CRTSCTS) != 0) { 335 cs->cs_wr5_dtr = ZSWR5_DTR; 336 cs->cs_wr5_rts = ZSWR5_RTS; 337 cs->cs_rr0_cts = ZSRR0_CTS; 338 } else if ((cflag & MDMBUF) != 0) { 339 cs->cs_wr5_dtr = 0; 340 cs->cs_wr5_rts = ZSWR5_DTR; 341 cs->cs_rr0_cts = ZSRR0_DCD; 342 } else { 343 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 344 cs->cs_wr5_rts = 0; 345 cs->cs_rr0_cts = 0; 346 } 347 splx(s); 348 349 /* Caller will stuff the pending registers. */ 350 return (0); 351 } 352 353 354 /* 355 * Read or write the chip with suitable delays. 356 */ 357 358 u_char 359 zs_read_reg(cs, reg) 360 struct zs_chanstate *cs; 361 u_char reg; 362 { 363 u_char val; 364 365 *cs->cs_reg_csr = reg; 366 ZS_DELAY(); 367 val = *cs->cs_reg_csr; 368 ZS_DELAY(); 369 return val; 370 } 371 372 void 373 zs_write_reg(cs, reg, val) 374 struct zs_chanstate *cs; 375 u_char reg, val; 376 { 377 *cs->cs_reg_csr = reg; 378 ZS_DELAY(); 379 *cs->cs_reg_csr = val; 380 ZS_DELAY(); 381 } 382 383 u_char zs_read_csr(cs) 384 struct zs_chanstate *cs; 385 { 386 u_char val; 387 388 val = *cs->cs_reg_csr; 389 ZS_DELAY(); 390 return val; 391 } 392 393 void zs_write_csr(cs, val) 394 struct zs_chanstate *cs; 395 u_char val; 396 { 397 *cs->cs_reg_csr = val; 398 ZS_DELAY(); 399 } 400 401 u_char zs_read_data(cs) 402 struct zs_chanstate *cs; 403 { 404 u_char val; 405 406 val = *cs->cs_reg_data; 407 ZS_DELAY(); 408 return val; 409 } 410 411 void zs_write_data(cs, val) 412 struct zs_chanstate *cs; 413 u_char val; 414 { 415 *cs->cs_reg_data = val; 416 ZS_DELAY(); 417 } 418 419 /**************************************************************** 420 * Console support functions (MVME specific!) 421 ****************************************************************/ 422 423 /* 424 * Polled input char. 425 */ 426 int 427 zs_getc(arg) 428 void *arg; 429 { 430 struct zs_chanstate *cs = arg; 431 int s, c, rr0, stat; 432 433 s = splhigh(); 434 top: 435 /* Wait for a character to arrive. */ 436 do { 437 rr0 = *cs->cs_reg_csr; 438 ZS_DELAY(); 439 } while ((rr0 & ZSRR0_RX_READY) == 0); 440 441 /* Read error register. */ 442 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 443 if (stat) { 444 zs_write_csr(cs, ZSM_RESET_ERR); 445 goto top; 446 } 447 448 /* Read character. */ 449 c = *cs->cs_reg_data; 450 ZS_DELAY(); 451 splx(s); 452 453 return (c); 454 } 455 456 /* 457 * Polled output char. 458 */ 459 void 460 zs_putc(arg, c) 461 void *arg; 462 int c; 463 { 464 struct zs_chanstate *cs = arg; 465 int s, rr0; 466 467 s = splhigh(); 468 /* Wait for transmitter to become ready. */ 469 do { 470 rr0 = *cs->cs_reg_csr; 471 ZS_DELAY(); 472 } while ((rr0 & ZSRR0_TX_READY) == 0); 473 474 *cs->cs_reg_data = c; 475 ZS_DELAY(); 476 splx(s); 477 } 478 479 /* 480 * Common parts of console init. 481 */ 482 void 483 zs_cnconfig(zsc_unit, channel, bust, bush) 484 int zsc_unit, channel; 485 bus_space_tag_t bust; 486 bus_space_handle_t bush; 487 { 488 struct zs_chanstate *cs; 489 struct zsdevice *zs; 490 struct zschan *zc; 491 492 zs = (struct zsdevice *) bush; /* XXXXXXXX */ 493 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 494 495 /* 496 * Pointer to channel state. Later, the console channel 497 * state is copied into the softc, and the console channel 498 * pointer adjusted to point to the new copy. 499 */ 500 zs_conschan = cs = &zs_conschan_store; 501 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 502 503 /* Setup temporary chanstate. */ 504 cs->cs_reg_csr = &zc->zc_csr; 505 cs->cs_reg_data = &zc->zc_data; 506 507 /* Initialize the pending registers. */ 508 bcopy(zs_init_reg, cs->cs_preg, 16); 509 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 510 511 #if 0 512 /* XXX: Preserve BAUD rate from boot loader. */ 513 /* XXX: Also, why reset the chip here? -gwr */ 514 cs->cs_defspeed = zs_get_speed(cs); 515 #else 516 cs->cs_defspeed = 9600; /* XXX */ 517 #endif 518 519 /* Clear the master interrupt enable. */ 520 zs_write_reg(cs, 9, 0); 521 522 /* Reset the whole SCC chip. */ 523 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 524 525 /* Copy "pending" to "current" and H/W. */ 526 zs_loadchannelregs(cs); 527 } 528 529 /* 530 * Polled console input putchar. 531 */ 532 int 533 zsc_pcccngetc(dev) 534 dev_t dev; 535 { 536 struct zs_chanstate *cs = zs_conschan; 537 int c; 538 539 c = zs_getc(cs); 540 return (c); 541 } 542 543 /* 544 * Polled console output putchar. 545 */ 546 void 547 zsc_pcccnputc(dev, c) 548 dev_t dev; 549 int c; 550 { 551 struct zs_chanstate *cs = zs_conschan; 552 553 zs_putc(cs, c); 554 } 555 556 /* 557 * Handle user request to enter kernel debugger. 558 */ 559 void 560 zs_abort(cs) 561 struct zs_chanstate *cs; 562 { 563 int rr0; 564 565 /* Wait for end of break to avoid PROM abort. */ 566 /* XXX - Limit the wait? */ 567 do { 568 rr0 = *cs->cs_reg_csr; 569 ZS_DELAY(); 570 } while (rr0 & ZSRR0_BREAK); 571 572 mvme68k_abort("SERIAL LINE ABORT"); 573 } 574
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