zs.c revision 1.21
1 /* $NetBSD: zs.c,v 1.21 2000/07/21 20:18:35 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <mvme68k/dev/zsvar.h> 69 70 /* 71 * Some warts needed by z8530tty.c - 72 * The default parity REALLY needs to be the same as the PROM uses, 73 * or you can not see messages done with printf during boot-up... 74 */ 75 int zs_def_cflag = (CREAD | CS8 | HUPCL); 76 /* XXX Shouldn't hardcode the minor number... */ 77 int zs_major = 12; 78 79 /* Flags from zscnprobe() */ 80 static int zs_hwflags[NZSC][2]; 81 82 /* Default speed for each channel */ 83 static int zs_defspeed[NZSC][2] = { 84 { 9600, /* port 1 */ 85 9600 }, /* port 2 */ 86 { 9600, /* port 3 */ 87 9600 }, /* port 4 */ 88 }; 89 90 static struct zs_chanstate zs_conschan_store; 91 static struct zs_chanstate *zs_conschan; 92 93 u_char zs_init_reg[16] = { 94 0, /* 0: CMD (reset, etc.) */ 95 0, /* 1: No interrupts yet. */ 96 0x18 + ZSHARD_PRI, /* IVECT */ 97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 100 0, /* 6: TXSYNC/SYNCLO */ 101 0, /* 7: RXSYNC/SYNCHI */ 102 0, /* 8: alias for data port */ 103 ZSWR9_MASTER_IE, 104 0, /*10: Misc. TX/RX control bits */ 105 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 106 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 107 0, /*13: BAUDHI (default=9600) */ 108 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 109 ZSWR15_BREAK_IE, 110 }; 111 112 113 /**************************************************************** 114 * Autoconfig 115 ****************************************************************/ 116 117 /* Definition of the driver for autoconfig. */ 118 static int zsc_print __P((void *, const char *name)); 119 int zs_getc __P((void *)); 120 void zs_putc __P((void *, int)); 121 122 #if 0 123 static int zs_get_speed __P((struct zs_chanstate *)); 124 #endif 125 126 extern struct cfdriver zsc_cd; 127 128 cons_decl(zsc_pcc); 129 130 131 /* 132 * Configure children of an SCC. 133 */ 134 void 135 zs_config(zsc, bust, bush) 136 struct zsc_softc *zsc; 137 bus_space_tag_t bust; 138 bus_space_handle_t bush; 139 { 140 struct zsc_attach_args zsc_args; 141 struct zsdevice *zs; 142 volatile struct zschan *zc; 143 struct zs_chanstate *cs; 144 int zsc_unit, channel, s; 145 146 zsc_unit = zsc->zsc_dev.dv_unit; 147 printf(": Zilog 8530 SCC\n"); 148 149 zs = (struct zsdevice *) bush; /* XXXXXXXX */ 150 151 /* 152 * Initialize software state for each channel. 153 */ 154 for (channel = 0; channel < 2; channel++) { 155 zsc_args.channel = channel; 156 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 157 cs = &zsc->zsc_cs_store[channel]; 158 zsc->zsc_cs[channel] = cs; 159 160 /* 161 * If we're the console, copy the channel state, and 162 * adjust the console channel pointer. 163 */ 164 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 165 bcopy(zs_conschan, cs, sizeof(struct zs_chanstate)); 166 zs_conschan = cs; 167 } else { 168 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 169 cs->cs_reg_csr = &zc->zc_csr; 170 cs->cs_reg_data = &zc->zc_data; 171 bcopy(zs_init_reg, cs->cs_creg, 16); 172 bcopy(zs_init_reg, cs->cs_preg, 16); 173 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 174 } 175 cs->cs_defcflag = zs_def_cflag; 176 177 /* Make these correspond to cs_defcflag (-crtscts) */ 178 cs->cs_rr0_dcd = ZSRR0_DCD; 179 cs->cs_rr0_cts = 0; 180 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 181 cs->cs_wr5_rts = 0; 182 183 cs->cs_channel = channel; 184 cs->cs_private = NULL; 185 cs->cs_ops = &zsops_null; 186 cs->cs_brg_clk = PCLK / 16; 187 188 /* 189 * Clear the master interrupt enable. 190 * The INTENA is common to both channels, 191 * so just do it on the A channel. 192 */ 193 if (channel == 0) { 194 zs_write_reg(cs, 9, 0); 195 } 196 197 /* 198 * Look for a child driver for this channel. 199 * The child attach will setup the hardware. 200 */ 201 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 202 /* No sub-driver. Just reset it. */ 203 u_char reset = (channel == 0) ? 204 ZSWR9_A_RESET : ZSWR9_B_RESET; 205 s = splzs(); 206 zs_write_reg(cs, 9, reset); 207 splx(s); 208 } 209 } 210 211 /* 212 * Allocate a software interrupt cookie. 213 */ 214 zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL, 215 (void (*)(void *)) zsc_intr_soft, zsc); 216 #ifdef DEBUG 217 assert(zsc->zsc_softintr_cookie); 218 #endif 219 } 220 221 static int 222 zsc_print(aux, name) 223 void *aux; 224 const char *name; 225 { 226 struct zsc_attach_args *args = aux; 227 228 if (name != NULL) 229 printf("%s: ", name); 230 231 if (args->channel != -1) 232 printf(" channel %d", args->channel); 233 234 return UNCONF; 235 } 236 237 /* 238 * Our ZS chips all share a common, autovectored interrupt, 239 * so we have to look at all of them on each interrupt. 240 */ 241 int 242 zshard(arg) 243 void *arg; 244 { 245 struct zsc_softc *zsc; 246 int unit, rval; 247 248 rval = 0; 249 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 250 zsc = zsc_cd.cd_devs[unit]; 251 if (zsc == NULL) 252 continue; 253 rval |= zsc_intr_hard(zsc); 254 if ((zsc->zsc_cs[0]->cs_softreq) || 255 (zsc->zsc_cs[1]->cs_softreq)) 256 softintr_schedule(zsc->zsc_softintr_cookie); 257 } 258 return (rval); 259 } 260 261 262 #if 0 263 /* 264 * Compute the current baud rate given a ZSCC channel. 265 */ 266 static int 267 zs_get_speed(cs) 268 struct zs_chanstate *cs; 269 { 270 int tconst; 271 272 tconst = zs_read_reg(cs, 12); 273 tconst |= zs_read_reg(cs, 13) << 8; 274 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 275 } 276 #endif 277 278 /* 279 * MD functions for setting the baud rate and control modes. 280 */ 281 int 282 zs_set_speed(cs, bps) 283 struct zs_chanstate *cs; 284 int bps; /* bits per second */ 285 { 286 int tconst, real_bps; 287 288 if (bps == 0) 289 return (0); 290 291 #ifdef DIAGNOSTIC 292 if (cs->cs_brg_clk == 0) 293 panic("zs_set_speed"); 294 #endif 295 296 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 297 if (tconst < 0) 298 return (EINVAL); 299 300 /* Convert back to make sure we can do it. */ 301 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 302 303 /* XXX - Allow some tolerance here? */ 304 if (real_bps != bps) 305 return (EINVAL); 306 307 cs->cs_preg[12] = tconst; 308 cs->cs_preg[13] = tconst >> 8; 309 310 /* Caller will stuff the pending registers. */ 311 return (0); 312 } 313 314 int 315 zs_set_modes(cs, cflag) 316 struct zs_chanstate *cs; 317 int cflag; /* bits per second */ 318 { 319 int s; 320 321 /* 322 * Output hardware flow control on the chip is horrendous: 323 * if carrier detect drops, the receiver is disabled, and if 324 * CTS drops, the transmitter is stoped IN MID CHARACTER! 325 * Therefore, NEVER set the HFC bit, and instead use the 326 * status interrupt to detect CTS changes. 327 */ 328 s = splzs(); 329 cs->cs_rr0_pps = 0; 330 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 331 cs->cs_rr0_dcd = 0; 332 if ((cflag & MDMBUF) == 0) 333 cs->cs_rr0_pps = ZSRR0_DCD; 334 } else 335 cs->cs_rr0_dcd = ZSRR0_DCD; 336 if ((cflag & CRTSCTS) != 0) { 337 cs->cs_wr5_dtr = ZSWR5_DTR; 338 cs->cs_wr5_rts = ZSWR5_RTS; 339 cs->cs_rr0_cts = ZSRR0_CTS; 340 } else if ((cflag & MDMBUF) != 0) { 341 cs->cs_wr5_dtr = 0; 342 cs->cs_wr5_rts = ZSWR5_DTR; 343 cs->cs_rr0_cts = ZSRR0_DCD; 344 } else { 345 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 346 cs->cs_wr5_rts = 0; 347 cs->cs_rr0_cts = 0; 348 } 349 splx(s); 350 351 /* Caller will stuff the pending registers. */ 352 return (0); 353 } 354 355 356 /* 357 * Read or write the chip with suitable delays. 358 */ 359 360 u_char 361 zs_read_reg(cs, reg) 362 struct zs_chanstate *cs; 363 u_char reg; 364 { 365 u_char val; 366 367 *cs->cs_reg_csr = reg; 368 ZS_DELAY(); 369 val = *cs->cs_reg_csr; 370 ZS_DELAY(); 371 return val; 372 } 373 374 void 375 zs_write_reg(cs, reg, val) 376 struct zs_chanstate *cs; 377 u_char reg, val; 378 { 379 *cs->cs_reg_csr = reg; 380 ZS_DELAY(); 381 *cs->cs_reg_csr = val; 382 ZS_DELAY(); 383 } 384 385 u_char zs_read_csr(cs) 386 struct zs_chanstate *cs; 387 { 388 u_char val; 389 390 val = *cs->cs_reg_csr; 391 ZS_DELAY(); 392 return val; 393 } 394 395 void zs_write_csr(cs, val) 396 struct zs_chanstate *cs; 397 u_char val; 398 { 399 *cs->cs_reg_csr = val; 400 ZS_DELAY(); 401 } 402 403 u_char zs_read_data(cs) 404 struct zs_chanstate *cs; 405 { 406 u_char val; 407 408 val = *cs->cs_reg_data; 409 ZS_DELAY(); 410 return val; 411 } 412 413 void zs_write_data(cs, val) 414 struct zs_chanstate *cs; 415 u_char val; 416 { 417 *cs->cs_reg_data = val; 418 ZS_DELAY(); 419 } 420 421 /**************************************************************** 422 * Console support functions (MVME specific!) 423 ****************************************************************/ 424 425 /* 426 * Polled input char. 427 */ 428 int 429 zs_getc(arg) 430 void *arg; 431 { 432 struct zs_chanstate *cs = arg; 433 int s, c, rr0, stat; 434 435 s = splhigh(); 436 top: 437 /* Wait for a character to arrive. */ 438 do { 439 rr0 = *cs->cs_reg_csr; 440 ZS_DELAY(); 441 } while ((rr0 & ZSRR0_RX_READY) == 0); 442 443 /* Read error register. */ 444 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 445 if (stat) { 446 zs_write_csr(cs, ZSM_RESET_ERR); 447 goto top; 448 } 449 450 /* Read character. */ 451 c = *cs->cs_reg_data; 452 ZS_DELAY(); 453 splx(s); 454 455 return (c); 456 } 457 458 /* 459 * Polled output char. 460 */ 461 void 462 zs_putc(arg, c) 463 void *arg; 464 int c; 465 { 466 struct zs_chanstate *cs = arg; 467 int s, rr0; 468 469 s = splhigh(); 470 /* Wait for transmitter to become ready. */ 471 do { 472 rr0 = *cs->cs_reg_csr; 473 ZS_DELAY(); 474 } while ((rr0 & ZSRR0_TX_READY) == 0); 475 476 *cs->cs_reg_data = c; 477 ZS_DELAY(); 478 splx(s); 479 } 480 481 /* 482 * Common parts of console init. 483 */ 484 void 485 zs_cnconfig(zsc_unit, channel, bust, bush) 486 int zsc_unit, channel; 487 bus_space_tag_t bust; 488 bus_space_handle_t bush; 489 { 490 struct zs_chanstate *cs; 491 struct zsdevice *zs; 492 struct zschan *zc; 493 494 zs = (struct zsdevice *) bush; /* XXXXXXXX */ 495 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 496 497 /* 498 * Pointer to channel state. Later, the console channel 499 * state is copied into the softc, and the console channel 500 * pointer adjusted to point to the new copy. 501 */ 502 zs_conschan = cs = &zs_conschan_store; 503 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 504 505 /* Setup temporary chanstate. */ 506 cs->cs_reg_csr = &zc->zc_csr; 507 cs->cs_reg_data = &zc->zc_data; 508 509 /* Initialize the pending registers. */ 510 bcopy(zs_init_reg, cs->cs_preg, 16); 511 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 512 513 #if 0 514 /* XXX: Preserve BAUD rate from boot loader. */ 515 /* XXX: Also, why reset the chip here? -gwr */ 516 cs->cs_defspeed = zs_get_speed(cs); 517 #else 518 cs->cs_defspeed = 9600; /* XXX */ 519 #endif 520 521 /* Clear the master interrupt enable. */ 522 zs_write_reg(cs, 9, 0); 523 524 /* Reset the whole SCC chip. */ 525 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 526 527 /* Copy "pending" to "current" and H/W. */ 528 zs_loadchannelregs(cs); 529 } 530 531 /* 532 * Polled console input putchar. 533 */ 534 int 535 zsc_pcccngetc(dev) 536 dev_t dev; 537 { 538 struct zs_chanstate *cs = zs_conschan; 539 int c; 540 541 c = zs_getc(cs); 542 return (c); 543 } 544 545 /* 546 * Polled console output putchar. 547 */ 548 void 549 zsc_pcccnputc(dev, c) 550 dev_t dev; 551 int c; 552 { 553 struct zs_chanstate *cs = zs_conschan; 554 555 zs_putc(cs, c); 556 } 557 558 /* 559 * Handle user request to enter kernel debugger. 560 */ 561 void 562 zs_abort(cs) 563 struct zs_chanstate *cs; 564 { 565 int rr0; 566 567 /* Wait for end of break to avoid PROM abort. */ 568 /* XXX - Limit the wait? */ 569 do { 570 rr0 = *cs->cs_reg_csr; 571 ZS_DELAY(); 572 } while (rr0 & ZSRR0_BREAK); 573 574 mvme68k_abort("SERIAL LINE ABORT"); 575 } 576
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