zs.c revision 1.23
1 /* $NetBSD: zs.c,v 1.23 2000/11/18 22:34:25 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <mvme68k/dev/zsvar.h> 69 70 /* 71 * Some warts needed by z8530tty.c - 72 * The default parity REALLY needs to be the same as the PROM uses, 73 * or you can not see messages done with printf during boot-up... 74 */ 75 int zs_def_cflag = (CREAD | CS8 | HUPCL); 76 /* XXX Shouldn't hardcode the minor number... */ 77 int zs_major = 12; 78 79 /* Flags from zscnprobe() */ 80 static int zs_hwflags[NZSC][2]; 81 82 /* Default speed for each channel */ 83 static int zs_defspeed[NZSC][2] = { 84 { 9600, /* port 1 */ 85 9600 }, /* port 2 */ 86 { 9600, /* port 3 */ 87 9600 }, /* port 4 */ 88 }; 89 90 static struct zs_chanstate zs_conschan_store; 91 static struct zs_chanstate *zs_conschan; 92 93 u_char zs_init_reg[16] = { 94 0, /* 0: CMD (reset, etc.) */ 95 0, /* 1: No interrupts yet. */ 96 0x18 + ZSHARD_PRI, /* IVECT */ 97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 100 0, /* 6: TXSYNC/SYNCLO */ 101 0, /* 7: RXSYNC/SYNCHI */ 102 0, /* 8: alias for data port */ 103 ZSWR9_MASTER_IE, 104 0, /*10: Misc. TX/RX control bits */ 105 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 106 0, /*12: BAUDLO (default=9600) */ 107 0, /*13: BAUDHI (default=9600) */ 108 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 109 ZSWR15_BREAK_IE, 110 }; 111 112 113 /**************************************************************** 114 * Autoconfig 115 ****************************************************************/ 116 117 /* Definition of the driver for autoconfig. */ 118 static int zsc_print __P((void *, const char *name)); 119 int zs_getc __P((void *)); 120 void zs_putc __P((void *, int)); 121 122 #if 0 123 static int zs_get_speed __P((struct zs_chanstate *)); 124 #endif 125 126 extern struct cfdriver zsc_cd; 127 128 cons_decl(zsc_pcc); 129 130 131 /* 132 * Configure children of an SCC. 133 */ 134 void 135 zs_config(zsc, zs, vector, pclk) 136 struct zsc_softc *zsc; 137 struct zsdevice *zs; 138 int vector, pclk; 139 { 140 struct zsc_attach_args zsc_args; 141 volatile struct zschan *zc; 142 struct zs_chanstate *cs; 143 int zsc_unit, channel, s; 144 145 zsc_unit = zsc->zsc_dev.dv_unit; 146 printf(": Zilog 8530 SCC at vector 0x%x\n", vector); 147 148 /* 149 * Initialize software state for each channel. 150 */ 151 for (channel = 0; channel < 2; channel++) { 152 zsc_args.channel = channel; 153 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 154 cs = &zsc->zsc_cs_store[channel]; 155 zsc->zsc_cs[channel] = cs; 156 157 /* 158 * If we're the console, copy the channel state, and 159 * adjust the console channel pointer. 160 */ 161 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 162 bcopy(zs_conschan, cs, sizeof(struct zs_chanstate)); 163 zs_conschan = cs; 164 } else { 165 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 166 cs->cs_reg_csr = zc->zc_csr; 167 cs->cs_reg_data = zc->zc_data; 168 bcopy(zs_init_reg, cs->cs_creg, 16); 169 bcopy(zs_init_reg, cs->cs_preg, 16); 170 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 171 } 172 cs->cs_creg[2] = cs->cs_preg[2] = vector; 173 cs->cs_creg[12] = cs->cs_preg[12] = ((pclk / 32) / 9600) - 1; 174 cs->cs_defcflag = zs_def_cflag; 175 176 /* Make these correspond to cs_defcflag (-crtscts) */ 177 cs->cs_rr0_dcd = ZSRR0_DCD; 178 cs->cs_rr0_cts = 0; 179 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 180 cs->cs_wr5_rts = 0; 181 182 cs->cs_channel = channel; 183 cs->cs_private = NULL; 184 cs->cs_ops = &zsops_null; 185 cs->cs_brg_clk = pclk / 16; 186 187 /* 188 * Clear the master interrupt enable. 189 * The INTENA is common to both channels, 190 * so just do it on the A channel. 191 * Write the interrupt vector while we're at it. 192 */ 193 if (channel == 0) { 194 zs_write_reg(cs, 9, 0); 195 zs_write_reg(cs, 2, vector); 196 } 197 198 /* 199 * Look for a child driver for this channel. 200 * The child attach will setup the hardware. 201 */ 202 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 203 /* No sub-driver. Just reset it. */ 204 u_char reset = (channel == 0) ? 205 ZSWR9_A_RESET : ZSWR9_B_RESET; 206 s = splzs(); 207 zs_write_reg(cs, 9, reset); 208 splx(s); 209 } 210 } 211 212 /* 213 * Allocate a software interrupt cookie. 214 */ 215 zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL, 216 (void (*)(void *)) zsc_intr_soft, zsc); 217 #ifdef DEBUG 218 assert(zsc->zsc_softintr_cookie); 219 #endif 220 } 221 222 static int 223 zsc_print(aux, name) 224 void *aux; 225 const char *name; 226 { 227 struct zsc_attach_args *args = aux; 228 229 if (name != NULL) 230 printf("%s: ", name); 231 232 if (args->channel != -1) 233 printf(" channel %d", args->channel); 234 235 return UNCONF; 236 } 237 238 #ifdef MVME162 239 /* 240 * Our ZS chips each have their own interrupt vector. 241 */ 242 int 243 zshard_unshared(arg) 244 void *arg; 245 { 246 struct zsc_softc *zsc = arg; 247 int rval; 248 249 rval = zsc_intr_hard(zsc); 250 251 if ((zsc->zsc_cs[0]->cs_softreq) || 252 (zsc->zsc_cs[1]->cs_softreq)) 253 softintr_schedule(zsc->zsc_softintr_cookie); 254 255 return (rval); 256 } 257 #endif 258 259 #ifdef MVME147 260 /* 261 * Our ZS chips all share a common, PCC-vectored interrupt, 262 * so we have to look at all of them on each interrupt. 263 */ 264 int 265 zshard_shared(arg) 266 void *arg; 267 { 268 struct zsc_softc *zsc; 269 int unit, rval; 270 271 rval = 0; 272 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 273 zsc = zsc_cd.cd_devs[unit]; 274 if (zsc == NULL) 275 continue; 276 rval |= zsc_intr_hard(zsc); 277 if ((zsc->zsc_cs[0]->cs_softreq) || 278 (zsc->zsc_cs[1]->cs_softreq)) 279 softintr_schedule(zsc->zsc_softintr_cookie); 280 } 281 return (rval); 282 } 283 #endif 284 285 286 #if 0 287 /* 288 * Compute the current baud rate given a ZSCC channel. 289 */ 290 static int 291 zs_get_speed(cs) 292 struct zs_chanstate *cs; 293 { 294 int tconst; 295 296 tconst = zs_read_reg(cs, 12); 297 tconst |= zs_read_reg(cs, 13) << 8; 298 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 299 } 300 #endif 301 302 /* 303 * MD functions for setting the baud rate and control modes. 304 */ 305 int 306 zs_set_speed(cs, bps) 307 struct zs_chanstate *cs; 308 int bps; /* bits per second */ 309 { 310 int tconst, real_bps; 311 312 if (bps == 0) 313 return (0); 314 315 #ifdef DIAGNOSTIC 316 if (cs->cs_brg_clk == 0) 317 panic("zs_set_speed"); 318 #endif 319 320 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 321 if (tconst < 0) 322 return (EINVAL); 323 324 /* Convert back to make sure we can do it. */ 325 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 326 327 /* Allow 2% tolerance WRT the required bps */ 328 if (((abs(real_bps - bps) * 1000) / bps) != bps) 329 return (EINVAL); 330 331 cs->cs_preg[12] = tconst; 332 cs->cs_preg[13] = tconst >> 8; 333 334 /* Caller will stuff the pending registers. */ 335 return (0); 336 } 337 338 int 339 zs_set_modes(cs, cflag) 340 struct zs_chanstate *cs; 341 int cflag; /* bits per second */ 342 { 343 int s; 344 345 /* 346 * Output hardware flow control on the chip is horrendous: 347 * if carrier detect drops, the receiver is disabled, and if 348 * CTS drops, the transmitter is stoped IN MID CHARACTER! 349 * Therefore, NEVER set the HFC bit, and instead use the 350 * status interrupt to detect CTS changes. 351 */ 352 s = splzs(); 353 cs->cs_rr0_pps = 0; 354 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 355 cs->cs_rr0_dcd = 0; 356 if ((cflag & MDMBUF) == 0) 357 cs->cs_rr0_pps = ZSRR0_DCD; 358 } else 359 cs->cs_rr0_dcd = ZSRR0_DCD; 360 if ((cflag & CRTSCTS) != 0) { 361 cs->cs_wr5_dtr = ZSWR5_DTR; 362 cs->cs_wr5_rts = ZSWR5_RTS; 363 cs->cs_rr0_cts = ZSRR0_CTS; 364 } else if ((cflag & MDMBUF) != 0) { 365 cs->cs_wr5_dtr = 0; 366 cs->cs_wr5_rts = ZSWR5_DTR; 367 cs->cs_rr0_cts = ZSRR0_DCD; 368 } else { 369 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 370 cs->cs_wr5_rts = 0; 371 cs->cs_rr0_cts = 0; 372 } 373 splx(s); 374 375 /* Caller will stuff the pending registers. */ 376 return (0); 377 } 378 379 380 /* 381 * Read or write the chip with suitable delays. 382 */ 383 384 u_char 385 zs_read_reg(cs, reg) 386 struct zs_chanstate *cs; 387 u_char reg; 388 { 389 u_char val; 390 391 *cs->cs_reg_csr = reg; 392 ZS_DELAY(); 393 val = *cs->cs_reg_csr; 394 ZS_DELAY(); 395 return val; 396 } 397 398 void 399 zs_write_reg(cs, reg, val) 400 struct zs_chanstate *cs; 401 u_char reg, val; 402 { 403 *cs->cs_reg_csr = reg; 404 ZS_DELAY(); 405 *cs->cs_reg_csr = val; 406 ZS_DELAY(); 407 } 408 409 u_char zs_read_csr(cs) 410 struct zs_chanstate *cs; 411 { 412 u_char val; 413 414 val = *cs->cs_reg_csr; 415 ZS_DELAY(); 416 return val; 417 } 418 419 void zs_write_csr(cs, val) 420 struct zs_chanstate *cs; 421 u_char val; 422 { 423 *cs->cs_reg_csr = val; 424 ZS_DELAY(); 425 } 426 427 u_char zs_read_data(cs) 428 struct zs_chanstate *cs; 429 { 430 u_char val; 431 432 val = *cs->cs_reg_data; 433 ZS_DELAY(); 434 return val; 435 } 436 437 void zs_write_data(cs, val) 438 struct zs_chanstate *cs; 439 u_char val; 440 { 441 *cs->cs_reg_data = val; 442 ZS_DELAY(); 443 } 444 445 /**************************************************************** 446 * Console support functions (MVME specific!) 447 ****************************************************************/ 448 449 /* 450 * Polled input char. 451 */ 452 int 453 zs_getc(arg) 454 void *arg; 455 { 456 struct zs_chanstate *cs = arg; 457 int s, c, rr0, stat; 458 459 s = splhigh(); 460 top: 461 /* Wait for a character to arrive. */ 462 do { 463 rr0 = *cs->cs_reg_csr; 464 ZS_DELAY(); 465 } while ((rr0 & ZSRR0_RX_READY) == 0); 466 467 /* Read error register. */ 468 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 469 if (stat) { 470 zs_write_csr(cs, ZSM_RESET_ERR); 471 goto top; 472 } 473 474 /* Read character. */ 475 c = *cs->cs_reg_data; 476 ZS_DELAY(); 477 splx(s); 478 479 return (c); 480 } 481 482 /* 483 * Polled output char. 484 */ 485 void 486 zs_putc(arg, c) 487 void *arg; 488 int c; 489 { 490 struct zs_chanstate *cs = arg; 491 int s, rr0; 492 493 s = splhigh(); 494 /* Wait for transmitter to become ready. */ 495 do { 496 rr0 = *cs->cs_reg_csr; 497 ZS_DELAY(); 498 } while ((rr0 & ZSRR0_TX_READY) == 0); 499 500 *cs->cs_reg_data = c; 501 ZS_DELAY(); 502 splx(s); 503 } 504 505 /* 506 * Common parts of console init. 507 */ 508 void 509 zs_cnconfig(zsc_unit, channel, zs, pclk) 510 int zsc_unit, channel; 511 struct zsdevice *zs; 512 int pclk; 513 { 514 struct zs_chanstate *cs; 515 struct zschan *zc; 516 517 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 518 519 /* 520 * Pointer to channel state. Later, the console channel 521 * state is copied into the softc, and the console channel 522 * pointer adjusted to point to the new copy. 523 */ 524 zs_conschan = cs = &zs_conschan_store; 525 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 526 527 /* Setup temporary chanstate. */ 528 cs->cs_reg_csr = zc->zc_csr; 529 cs->cs_reg_data = zc->zc_data; 530 531 /* Initialize the pending registers. */ 532 bcopy(zs_init_reg, cs->cs_preg, 16); 533 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 534 cs->cs_preg[12] = ((pclk / 32) / 9600) - 1; 535 536 #if 0 537 /* XXX: Preserve BAUD rate from boot loader. */ 538 /* XXX: Also, why reset the chip here? -gwr */ 539 cs->cs_defspeed = zs_get_speed(cs); 540 #else 541 cs->cs_defspeed = 9600; /* XXX */ 542 #endif 543 544 /* Clear the master interrupt enable. */ 545 zs_write_reg(cs, 9, 0); 546 547 /* Reset the whole SCC chip. */ 548 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 549 550 /* Copy "pending" to "current" and H/W. */ 551 zs_loadchannelregs(cs); 552 } 553 554 /* 555 * Polled console input putchar. 556 */ 557 int 558 zsc_pcccngetc(dev) 559 dev_t dev; 560 { 561 struct zs_chanstate *cs = zs_conschan; 562 int c; 563 564 c = zs_getc(cs); 565 return (c); 566 } 567 568 /* 569 * Polled console output putchar. 570 */ 571 void 572 zsc_pcccnputc(dev, c) 573 dev_t dev; 574 int c; 575 { 576 struct zs_chanstate *cs = zs_conschan; 577 578 zs_putc(cs, c); 579 } 580 581 /* 582 * Handle user request to enter kernel debugger. 583 */ 584 void 585 zs_abort(cs) 586 struct zs_chanstate *cs; 587 { 588 int rr0; 589 590 /* Wait for end of break to avoid PROM abort. */ 591 /* XXX - Limit the wait? */ 592 do { 593 rr0 = *cs->cs_reg_csr; 594 ZS_DELAY(); 595 } while (rr0 & ZSRR0_BREAK); 596 597 mvme68k_abort("SERIAL LINE ABORT"); 598 } 599
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