zs.c revision 1.27
1 /* $NetBSD: zs.c,v 1.27 2001/05/31 18:46:08 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <mvme68k/dev/zsvar.h> 69 70 /* 71 * Some warts needed by z8530tty.c - 72 * The default parity REALLY needs to be the same as the PROM uses, 73 * or you can not see messages done with printf during boot-up... 74 */ 75 int zs_def_cflag = (CREAD | CS8 | HUPCL); 76 /* XXX Shouldn't hardcode the minor number... */ 77 int zs_major = 12; 78 79 /* Flags from zscnprobe() */ 80 static int zs_hwflags[NZSC][2]; 81 82 /* Default speed for each channel */ 83 static int zs_defspeed[NZSC][2] = { 84 { 9600, /* port 1 */ 85 9600 }, /* port 2 */ 86 { 9600, /* port 3 */ 87 9600 }, /* port 4 */ 88 }; 89 90 static struct zs_chanstate zs_conschan_store; 91 static struct zs_chanstate *zs_conschan; 92 93 u_char zs_init_reg[16] = { 94 0, /* 0: CMD (reset, etc.) */ 95 0, /* 1: No interrupts yet. */ 96 0x18 + ZSHARD_PRI, /* IVECT */ 97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 100 0, /* 6: TXSYNC/SYNCLO */ 101 0, /* 7: RXSYNC/SYNCHI */ 102 0, /* 8: alias for data port */ 103 ZSWR9_MASTER_IE, 104 0, /*10: Misc. TX/RX control bits */ 105 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 106 0, /*12: BAUDLO (default=9600) */ 107 0, /*13: BAUDHI (default=9600) */ 108 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 109 ZSWR15_BREAK_IE, 110 }; 111 112 113 /**************************************************************** 114 * Autoconfig 115 ****************************************************************/ 116 117 /* Definition of the driver for autoconfig. */ 118 static int zsc_print __P((void *, const char *name)); 119 int zs_getc __P((void *)); 120 void zs_putc __P((void *, int)); 121 122 #if 0 123 static int zs_get_speed __P((struct zs_chanstate *)); 124 #endif 125 126 extern struct cfdriver zsc_cd; 127 128 cons_decl(zsc_pcc); 129 130 131 /* 132 * Configure children of an SCC. 133 */ 134 void 135 zs_config(zsc, zs, vector, pclk) 136 struct zsc_softc *zsc; 137 struct zsdevice *zs; 138 int vector, pclk; 139 { 140 struct zsc_attach_args zsc_args; 141 volatile struct zschan *zc; 142 struct zs_chanstate *cs; 143 int zsc_unit, channel, s; 144 145 zsc_unit = zsc->zsc_dev.dv_unit; 146 printf(": Zilog 8530 SCC at vector 0x%x\n", vector); 147 148 /* 149 * Initialize software state for each channel. 150 */ 151 for (channel = 0; channel < 2; channel++) { 152 zsc_args.channel = channel; 153 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 154 cs = &zsc->zsc_cs_store[channel]; 155 zsc->zsc_cs[channel] = cs; 156 157 /* 158 * If we're the console, copy the channel state, and 159 * adjust the console channel pointer. 160 */ 161 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 162 bcopy(zs_conschan, cs, sizeof(struct zs_chanstate)); 163 zs_conschan = cs; 164 } else { 165 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 166 cs->cs_reg_csr = zc->zc_csr; 167 cs->cs_reg_data = zc->zc_data; 168 bcopy(zs_init_reg, cs->cs_creg, 16); 169 bcopy(zs_init_reg, cs->cs_preg, 16); 170 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 171 } 172 173 cs->cs_brg_clk = pclk / 16; 174 cs->cs_creg[2] = cs->cs_preg[2] = vector; 175 zs_set_speed(cs, cs->cs_defspeed); 176 cs->cs_creg[12] = cs->cs_preg[12]; 177 cs->cs_creg[13] = cs->cs_preg[13]; 178 cs->cs_defcflag = zs_def_cflag; 179 180 /* Make these correspond to cs_defcflag (-crtscts) */ 181 cs->cs_rr0_dcd = ZSRR0_DCD; 182 cs->cs_rr0_cts = 0; 183 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 184 cs->cs_wr5_rts = 0; 185 186 cs->cs_channel = channel; 187 cs->cs_private = NULL; 188 cs->cs_ops = &zsops_null; 189 190 /* 191 * Clear the master interrupt enable. 192 * The INTENA is common to both channels, 193 * so just do it on the A channel. 194 * Write the interrupt vector while we're at it. 195 */ 196 if (channel == 0) { 197 zs_write_reg(cs, 9, 0); 198 zs_write_reg(cs, 2, vector); 199 } 200 201 /* 202 * Look for a child driver for this channel. 203 * The child attach will setup the hardware. 204 */ 205 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 206 /* No sub-driver. Just reset it. */ 207 u_char reset = (channel == 0) ? 208 ZSWR9_A_RESET : ZSWR9_B_RESET; 209 s = splzs(); 210 zs_write_reg(cs, 9, reset); 211 splx(s); 212 } 213 } 214 215 /* 216 * Allocate a software interrupt cookie. 217 */ 218 zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL, 219 (void (*)(void *)) zsc_intr_soft, zsc); 220 #ifdef DEBUG 221 assert(zsc->zsc_softintr_cookie); 222 #endif 223 } 224 225 static int 226 zsc_print(aux, name) 227 void *aux; 228 const char *name; 229 { 230 struct zsc_attach_args *args = aux; 231 232 if (name != NULL) 233 printf("%s: ", name); 234 235 if (args->channel != -1) 236 printf(" channel %d", args->channel); 237 238 return UNCONF; 239 } 240 241 #if defined(MVME162) || defined(MVME172) 242 /* 243 * Our ZS chips each have their own interrupt vector. 244 */ 245 int 246 zshard_unshared(arg) 247 void *arg; 248 { 249 struct zsc_softc *zsc = arg; 250 int rval; 251 252 rval = zsc_intr_hard(zsc); 253 254 if (rval) { 255 if ((zsc->zsc_cs[0]->cs_softreq) || 256 (zsc->zsc_cs[1]->cs_softreq)) 257 softintr_schedule(zsc->zsc_softintr_cookie); 258 zsc->zsc_evcnt.ev_count++; 259 } 260 261 return (rval); 262 } 263 #endif 264 265 #ifdef MVME147 266 /* 267 * Our ZS chips all share a common, PCC-vectored interrupt, 268 * so we have to look at all of them on each interrupt. 269 */ 270 int 271 zshard_shared(arg) 272 void *arg; 273 { 274 struct zsc_softc *zsc; 275 int unit, rval; 276 277 rval = 0; 278 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 279 zsc = zsc_cd.cd_devs[unit]; 280 if (zsc != NULL && zsc_intr_hard(zsc)) { 281 if ((zsc->zsc_cs[0]->cs_softreq) || 282 (zsc->zsc_cs[1]->cs_softreq)) 283 softintr_schedule(zsc->zsc_softintr_cookie); 284 zsc->zsc_evcnt.ev_count++; 285 rval++; 286 } 287 } 288 return (rval); 289 } 290 #endif 291 292 293 #if 0 294 /* 295 * Compute the current baud rate given a ZSCC channel. 296 */ 297 static int 298 zs_get_speed(cs) 299 struct zs_chanstate *cs; 300 { 301 int tconst; 302 303 tconst = zs_read_reg(cs, 12); 304 tconst |= zs_read_reg(cs, 13) << 8; 305 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 306 } 307 #endif 308 309 /* 310 * MD functions for setting the baud rate and control modes. 311 */ 312 int 313 zs_set_speed(cs, bps) 314 struct zs_chanstate *cs; 315 int bps; /* bits per second */ 316 { 317 int tconst, real_bps; 318 319 if (bps == 0) 320 return (0); 321 322 #ifdef DIAGNOSTIC 323 if (cs->cs_brg_clk == 0) 324 panic("zs_set_speed"); 325 #endif 326 327 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 328 if (tconst < 0) 329 return (EINVAL); 330 331 /* Convert back to make sure we can do it. */ 332 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 333 334 /* Allow 2% tolerance WRT the required bps */ 335 if (((abs(real_bps - bps) * 1000) / bps) > 20) 336 return (EINVAL); 337 338 cs->cs_preg[12] = tconst; 339 cs->cs_preg[13] = tconst >> 8; 340 341 /* Caller will stuff the pending registers. */ 342 return (0); 343 } 344 345 int 346 zs_set_modes(cs, cflag) 347 struct zs_chanstate *cs; 348 int cflag; /* bits per second */ 349 { 350 int s; 351 352 /* 353 * Output hardware flow control on the chip is horrendous: 354 * if carrier detect drops, the receiver is disabled, and if 355 * CTS drops, the transmitter is stoped IN MID CHARACTER! 356 * Therefore, NEVER set the HFC bit, and instead use the 357 * status interrupt to detect CTS changes. 358 */ 359 s = splzs(); 360 cs->cs_rr0_pps = 0; 361 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 362 cs->cs_rr0_dcd = 0; 363 if ((cflag & MDMBUF) == 0) 364 cs->cs_rr0_pps = ZSRR0_DCD; 365 } else 366 cs->cs_rr0_dcd = ZSRR0_DCD; 367 if ((cflag & CRTSCTS) != 0) { 368 cs->cs_wr5_dtr = ZSWR5_DTR; 369 cs->cs_wr5_rts = ZSWR5_RTS; 370 cs->cs_rr0_cts = ZSRR0_CTS; 371 } else if ((cflag & MDMBUF) != 0) { 372 cs->cs_wr5_dtr = 0; 373 cs->cs_wr5_rts = ZSWR5_DTR; 374 cs->cs_rr0_cts = ZSRR0_DCD; 375 } else { 376 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 377 cs->cs_wr5_rts = 0; 378 cs->cs_rr0_cts = 0; 379 } 380 splx(s); 381 382 /* Caller will stuff the pending registers. */ 383 return (0); 384 } 385 386 387 /* 388 * Read or write the chip with suitable delays. 389 */ 390 391 u_char 392 zs_read_reg(cs, reg) 393 struct zs_chanstate *cs; 394 u_char reg; 395 { 396 u_char val; 397 398 *cs->cs_reg_csr = reg; 399 ZS_DELAY(); 400 val = *cs->cs_reg_csr; 401 ZS_DELAY(); 402 return val; 403 } 404 405 void 406 zs_write_reg(cs, reg, val) 407 struct zs_chanstate *cs; 408 u_char reg, val; 409 { 410 *cs->cs_reg_csr = reg; 411 ZS_DELAY(); 412 *cs->cs_reg_csr = val; 413 ZS_DELAY(); 414 } 415 416 u_char zs_read_csr(cs) 417 struct zs_chanstate *cs; 418 { 419 u_char val; 420 421 val = *cs->cs_reg_csr; 422 ZS_DELAY(); 423 return val; 424 } 425 426 void zs_write_csr(cs, val) 427 struct zs_chanstate *cs; 428 u_char val; 429 { 430 *cs->cs_reg_csr = val; 431 ZS_DELAY(); 432 } 433 434 u_char zs_read_data(cs) 435 struct zs_chanstate *cs; 436 { 437 u_char val; 438 439 val = *cs->cs_reg_data; 440 ZS_DELAY(); 441 return val; 442 } 443 444 void zs_write_data(cs, val) 445 struct zs_chanstate *cs; 446 u_char val; 447 { 448 *cs->cs_reg_data = val; 449 ZS_DELAY(); 450 } 451 452 /**************************************************************** 453 * Console support functions (MVME specific!) 454 ****************************************************************/ 455 456 /* 457 * Polled input char. 458 */ 459 int 460 zs_getc(arg) 461 void *arg; 462 { 463 struct zs_chanstate *cs = arg; 464 int s, c, rr0, stat; 465 466 s = splhigh(); 467 top: 468 /* Wait for a character to arrive. */ 469 do { 470 rr0 = *cs->cs_reg_csr; 471 ZS_DELAY(); 472 } while ((rr0 & ZSRR0_RX_READY) == 0); 473 474 /* Read error register. */ 475 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 476 if (stat) { 477 zs_write_csr(cs, ZSM_RESET_ERR); 478 goto top; 479 } 480 481 /* Read character. */ 482 c = *cs->cs_reg_data; 483 ZS_DELAY(); 484 splx(s); 485 486 return (c); 487 } 488 489 /* 490 * Polled output char. 491 */ 492 void 493 zs_putc(arg, c) 494 void *arg; 495 int c; 496 { 497 struct zs_chanstate *cs = arg; 498 int s, rr0; 499 500 s = splhigh(); 501 /* Wait for transmitter to become ready. */ 502 do { 503 rr0 = *cs->cs_reg_csr; 504 ZS_DELAY(); 505 } while ((rr0 & ZSRR0_TX_READY) == 0); 506 507 *cs->cs_reg_data = c; 508 ZS_DELAY(); 509 splx(s); 510 } 511 512 /* 513 * Common parts of console init. 514 */ 515 void 516 zs_cnconfig(zsc_unit, channel, zs, pclk) 517 int zsc_unit, channel; 518 struct zsdevice *zs; 519 int pclk; 520 { 521 struct zs_chanstate *cs; 522 struct zschan *zc; 523 524 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 525 526 /* 527 * Pointer to channel state. Later, the console channel 528 * state is copied into the softc, and the console channel 529 * pointer adjusted to point to the new copy. 530 */ 531 zs_conschan = cs = &zs_conschan_store; 532 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 533 534 /* Setup temporary chanstate. */ 535 cs->cs_brg_clk = pclk / 16; 536 cs->cs_reg_csr = zc->zc_csr; 537 cs->cs_reg_data = zc->zc_data; 538 539 /* Initialize the pending registers. */ 540 bcopy(zs_init_reg, cs->cs_preg, 16); 541 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 542 543 #if 0 544 /* XXX: Preserve BAUD rate from boot loader. */ 545 /* XXX: Also, why reset the chip here? -gwr */ 546 cs->cs_defspeed = zs_get_speed(cs); 547 #else 548 cs->cs_defspeed = 9600; /* XXX */ 549 #endif 550 zs_set_speed(cs, cs->cs_defspeed); 551 cs->cs_creg[12] = cs->cs_preg[12]; 552 cs->cs_creg[13] = cs->cs_preg[13]; 553 554 /* Clear the master interrupt enable. */ 555 zs_write_reg(cs, 9, 0); 556 557 /* Reset the whole SCC chip. */ 558 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 559 560 /* Copy "pending" to "current" and H/W. */ 561 zs_loadchannelregs(cs); 562 } 563 564 /* 565 * Polled console input putchar. 566 */ 567 int 568 zsc_pcccngetc(dev) 569 dev_t dev; 570 { 571 struct zs_chanstate *cs = zs_conschan; 572 int c; 573 574 c = zs_getc(cs); 575 return (c); 576 } 577 578 /* 579 * Polled console output putchar. 580 */ 581 void 582 zsc_pcccnputc(dev, c) 583 dev_t dev; 584 int c; 585 { 586 struct zs_chanstate *cs = zs_conschan; 587 588 zs_putc(cs, c); 589 } 590 591 /* 592 * Handle user request to enter kernel debugger. 593 */ 594 void 595 zs_abort(cs) 596 struct zs_chanstate *cs; 597 { 598 int rr0; 599 600 /* Wait for end of break to avoid PROM abort. */ 601 /* XXX - Limit the wait? */ 602 do { 603 rr0 = *cs->cs_reg_csr; 604 ZS_DELAY(); 605 } while (rr0 & ZSRR0_BREAK); 606 607 mvme68k_abort("SERIAL LINE ABORT"); 608 } 609
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