zs.c revision 1.30
1 /* $NetBSD: zs.c,v 1.30 2003/01/01 01:51:24 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <mvme68k/dev/zsvar.h> 69 70 /* 71 * Some warts needed by z8530tty.c - 72 * The default parity REALLY needs to be the same as the PROM uses, 73 * or you can not see messages done with printf during boot-up... 74 */ 75 int zs_def_cflag = (CREAD | CS8 | HUPCL); 76 77 /* Flags from zscnprobe() */ 78 static int zs_hwflags[NZSC][2]; 79 80 /* Default speed for each channel */ 81 static int zs_defspeed[NZSC][2] = { 82 { 9600, /* port 1 */ 83 9600 }, /* port 2 */ 84 { 9600, /* port 3 */ 85 9600 }, /* port 4 */ 86 }; 87 88 static struct zs_chanstate zs_conschan_store; 89 static struct zs_chanstate *zs_conschan; 90 91 u_char zs_init_reg[16] = { 92 0, /* 0: CMD (reset, etc.) */ 93 0, /* 1: No interrupts yet. */ 94 0x18 + ZSHARD_PRI, /* IVECT */ 95 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 96 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 97 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 98 0, /* 6: TXSYNC/SYNCLO */ 99 0, /* 7: RXSYNC/SYNCHI */ 100 0, /* 8: alias for data port */ 101 ZSWR9_MASTER_IE, 102 0, /*10: Misc. TX/RX control bits */ 103 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 104 0, /*12: BAUDLO (default=9600) */ 105 0, /*13: BAUDHI (default=9600) */ 106 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 107 ZSWR15_BREAK_IE, 108 }; 109 110 111 /**************************************************************** 112 * Autoconfig 113 ****************************************************************/ 114 115 /* Definition of the driver for autoconfig. */ 116 static int zsc_print __P((void *, const char *name)); 117 int zs_getc __P((void *)); 118 void zs_putc __P((void *, int)); 119 120 #if 0 121 static int zs_get_speed __P((struct zs_chanstate *)); 122 #endif 123 124 extern struct cfdriver zsc_cd; 125 126 cons_decl(zsc_pcc); 127 128 129 /* 130 * Configure children of an SCC. 131 */ 132 void 133 zs_config(zsc, zs, vector, pclk) 134 struct zsc_softc *zsc; 135 struct zsdevice *zs; 136 int vector, pclk; 137 { 138 struct zsc_attach_args zsc_args; 139 volatile struct zschan *zc; 140 struct zs_chanstate *cs; 141 int zsc_unit, channel, s; 142 143 zsc_unit = zsc->zsc_dev.dv_unit; 144 printf(": Zilog 8530 SCC at vector 0x%x\n", vector); 145 146 /* 147 * Initialize software state for each channel. 148 */ 149 for (channel = 0; channel < 2; channel++) { 150 zsc_args.channel = channel; 151 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 152 cs = &zsc->zsc_cs_store[channel]; 153 zsc->zsc_cs[channel] = cs; 154 155 /* 156 * If we're the console, copy the channel state, and 157 * adjust the console channel pointer. 158 */ 159 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 160 memcpy(cs, zs_conschan, sizeof(struct zs_chanstate)); 161 zs_conschan = cs; 162 } else { 163 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 164 cs->cs_reg_csr = zc->zc_csr; 165 cs->cs_reg_data = zc->zc_data; 166 memcpy(cs->cs_creg, zs_init_reg, 16); 167 memcpy(cs->cs_preg, zs_init_reg, 16); 168 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 169 } 170 171 cs->cs_brg_clk = pclk / 16; 172 cs->cs_creg[2] = cs->cs_preg[2] = vector; 173 zs_set_speed(cs, cs->cs_defspeed); 174 cs->cs_creg[12] = cs->cs_preg[12]; 175 cs->cs_creg[13] = cs->cs_preg[13]; 176 cs->cs_defcflag = zs_def_cflag; 177 178 /* Make these correspond to cs_defcflag (-crtscts) */ 179 cs->cs_rr0_dcd = ZSRR0_DCD; 180 cs->cs_rr0_cts = 0; 181 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 182 cs->cs_wr5_rts = 0; 183 184 cs->cs_channel = channel; 185 cs->cs_private = NULL; 186 cs->cs_ops = &zsops_null; 187 188 /* 189 * Clear the master interrupt enable. 190 * The INTENA is common to both channels, 191 * so just do it on the A channel. 192 * Write the interrupt vector while we're at it. 193 */ 194 if (channel == 0) { 195 zs_write_reg(cs, 9, 0); 196 zs_write_reg(cs, 2, vector); 197 } 198 199 /* 200 * Look for a child driver for this channel. 201 * The child attach will setup the hardware. 202 */ 203 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 204 /* No sub-driver. Just reset it. */ 205 u_char reset = (channel == 0) ? 206 ZSWR9_A_RESET : ZSWR9_B_RESET; 207 s = splzs(); 208 zs_write_reg(cs, 9, reset); 209 splx(s); 210 } 211 } 212 213 /* 214 * Allocate a software interrupt cookie. 215 */ 216 zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL, 217 (void (*)(void *)) zsc_intr_soft, zsc); 218 #ifdef DEBUG 219 assert(zsc->zsc_softintr_cookie); 220 #endif 221 } 222 223 static int 224 zsc_print(aux, name) 225 void *aux; 226 const char *name; 227 { 228 struct zsc_attach_args *args = aux; 229 230 if (name != NULL) 231 aprint_normal("%s: ", name); 232 233 if (args->channel != -1) 234 aprint_normal(" channel %d", args->channel); 235 236 return UNCONF; 237 } 238 239 #if defined(MVME162) || defined(MVME172) 240 /* 241 * Our ZS chips each have their own interrupt vector. 242 */ 243 int 244 zshard_unshared(arg) 245 void *arg; 246 { 247 struct zsc_softc *zsc = arg; 248 int rval; 249 250 rval = zsc_intr_hard(zsc); 251 252 if (rval) { 253 if ((zsc->zsc_cs[0]->cs_softreq) || 254 (zsc->zsc_cs[1]->cs_softreq)) 255 softintr_schedule(zsc->zsc_softintr_cookie); 256 zsc->zsc_evcnt.ev_count++; 257 } 258 259 return (rval); 260 } 261 #endif 262 263 #ifdef MVME147 264 /* 265 * Our ZS chips all share a common, PCC-vectored interrupt, 266 * so we have to look at all of them on each interrupt. 267 */ 268 int 269 zshard_shared(arg) 270 void *arg; 271 { 272 struct zsc_softc *zsc; 273 int unit, rval; 274 275 rval = 0; 276 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 277 zsc = zsc_cd.cd_devs[unit]; 278 if (zsc != NULL && zsc_intr_hard(zsc)) { 279 if ((zsc->zsc_cs[0]->cs_softreq) || 280 (zsc->zsc_cs[1]->cs_softreq)) 281 softintr_schedule(zsc->zsc_softintr_cookie); 282 zsc->zsc_evcnt.ev_count++; 283 rval++; 284 } 285 } 286 return (rval); 287 } 288 #endif 289 290 291 #if 0 292 /* 293 * Compute the current baud rate given a ZSCC channel. 294 */ 295 static int 296 zs_get_speed(cs) 297 struct zs_chanstate *cs; 298 { 299 int tconst; 300 301 tconst = zs_read_reg(cs, 12); 302 tconst |= zs_read_reg(cs, 13) << 8; 303 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 304 } 305 #endif 306 307 /* 308 * MD functions for setting the baud rate and control modes. 309 */ 310 int 311 zs_set_speed(cs, bps) 312 struct zs_chanstate *cs; 313 int bps; /* bits per second */ 314 { 315 int tconst, real_bps; 316 317 if (bps == 0) 318 return (0); 319 320 #ifdef DIAGNOSTIC 321 if (cs->cs_brg_clk == 0) 322 panic("zs_set_speed"); 323 #endif 324 325 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 326 if (tconst < 0) 327 return (EINVAL); 328 329 /* Convert back to make sure we can do it. */ 330 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 331 332 /* Allow 2% tolerance WRT the required bps */ 333 if (((abs(real_bps - bps) * 1000) / bps) > 20) 334 return (EINVAL); 335 336 cs->cs_preg[12] = tconst; 337 cs->cs_preg[13] = tconst >> 8; 338 339 /* Caller will stuff the pending registers. */ 340 return (0); 341 } 342 343 int 344 zs_set_modes(cs, cflag) 345 struct zs_chanstate *cs; 346 int cflag; /* bits per second */ 347 { 348 int s; 349 350 /* 351 * Output hardware flow control on the chip is horrendous: 352 * if carrier detect drops, the receiver is disabled, and if 353 * CTS drops, the transmitter is stoped IN MID CHARACTER! 354 * Therefore, NEVER set the HFC bit, and instead use the 355 * status interrupt to detect CTS changes. 356 */ 357 s = splzs(); 358 cs->cs_rr0_pps = 0; 359 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 360 cs->cs_rr0_dcd = 0; 361 if ((cflag & MDMBUF) == 0) 362 cs->cs_rr0_pps = ZSRR0_DCD; 363 } else 364 cs->cs_rr0_dcd = ZSRR0_DCD; 365 if ((cflag & CRTSCTS) != 0) { 366 cs->cs_wr5_dtr = ZSWR5_DTR; 367 cs->cs_wr5_rts = ZSWR5_RTS; 368 cs->cs_rr0_cts = ZSRR0_CTS; 369 } else if ((cflag & MDMBUF) != 0) { 370 cs->cs_wr5_dtr = 0; 371 cs->cs_wr5_rts = ZSWR5_DTR; 372 cs->cs_rr0_cts = ZSRR0_DCD; 373 } else { 374 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 375 cs->cs_wr5_rts = 0; 376 cs->cs_rr0_cts = 0; 377 } 378 splx(s); 379 380 /* Caller will stuff the pending registers. */ 381 return (0); 382 } 383 384 385 /* 386 * Read or write the chip with suitable delays. 387 */ 388 389 u_char 390 zs_read_reg(cs, reg) 391 struct zs_chanstate *cs; 392 u_char reg; 393 { 394 u_char val; 395 396 *cs->cs_reg_csr = reg; 397 ZS_DELAY(); 398 val = *cs->cs_reg_csr; 399 ZS_DELAY(); 400 return val; 401 } 402 403 void 404 zs_write_reg(cs, reg, val) 405 struct zs_chanstate *cs; 406 u_char reg, val; 407 { 408 *cs->cs_reg_csr = reg; 409 ZS_DELAY(); 410 *cs->cs_reg_csr = val; 411 ZS_DELAY(); 412 } 413 414 u_char zs_read_csr(cs) 415 struct zs_chanstate *cs; 416 { 417 u_char val; 418 419 val = *cs->cs_reg_csr; 420 ZS_DELAY(); 421 return val; 422 } 423 424 void zs_write_csr(cs, val) 425 struct zs_chanstate *cs; 426 u_char val; 427 { 428 *cs->cs_reg_csr = val; 429 ZS_DELAY(); 430 } 431 432 u_char zs_read_data(cs) 433 struct zs_chanstate *cs; 434 { 435 u_char val; 436 437 val = *cs->cs_reg_data; 438 ZS_DELAY(); 439 return val; 440 } 441 442 void zs_write_data(cs, val) 443 struct zs_chanstate *cs; 444 u_char val; 445 { 446 *cs->cs_reg_data = val; 447 ZS_DELAY(); 448 } 449 450 /**************************************************************** 451 * Console support functions (MVME specific!) 452 ****************************************************************/ 453 454 /* 455 * Polled input char. 456 */ 457 int 458 zs_getc(arg) 459 void *arg; 460 { 461 struct zs_chanstate *cs = arg; 462 int s, c, rr0, stat; 463 464 s = splhigh(); 465 top: 466 /* Wait for a character to arrive. */ 467 do { 468 rr0 = *cs->cs_reg_csr; 469 ZS_DELAY(); 470 } while ((rr0 & ZSRR0_RX_READY) == 0); 471 472 /* Read error register. */ 473 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 474 if (stat) { 475 zs_write_csr(cs, ZSM_RESET_ERR); 476 goto top; 477 } 478 479 /* Read character. */ 480 c = *cs->cs_reg_data; 481 ZS_DELAY(); 482 splx(s); 483 484 return (c); 485 } 486 487 /* 488 * Polled output char. 489 */ 490 void 491 zs_putc(arg, c) 492 void *arg; 493 int c; 494 { 495 struct zs_chanstate *cs = arg; 496 int s, rr0; 497 498 s = splhigh(); 499 /* Wait for transmitter to become ready. */ 500 do { 501 rr0 = *cs->cs_reg_csr; 502 ZS_DELAY(); 503 } while ((rr0 & ZSRR0_TX_READY) == 0); 504 505 *cs->cs_reg_data = c; 506 ZS_DELAY(); 507 splx(s); 508 } 509 510 /* 511 * Common parts of console init. 512 */ 513 void 514 zs_cnconfig(zsc_unit, channel, zs, pclk) 515 int zsc_unit, channel; 516 struct zsdevice *zs; 517 int pclk; 518 { 519 struct zs_chanstate *cs; 520 struct zschan *zc; 521 522 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 523 524 /* 525 * Pointer to channel state. Later, the console channel 526 * state is copied into the softc, and the console channel 527 * pointer adjusted to point to the new copy. 528 */ 529 zs_conschan = cs = &zs_conschan_store; 530 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 531 532 /* Setup temporary chanstate. */ 533 cs->cs_brg_clk = pclk / 16; 534 cs->cs_reg_csr = zc->zc_csr; 535 cs->cs_reg_data = zc->zc_data; 536 537 /* Initialize the pending registers. */ 538 memcpy(cs->cs_preg, zs_init_reg, 16); 539 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 540 541 #if 0 542 /* XXX: Preserve BAUD rate from boot loader. */ 543 /* XXX: Also, why reset the chip here? -gwr */ 544 cs->cs_defspeed = zs_get_speed(cs); 545 #else 546 cs->cs_defspeed = 9600; /* XXX */ 547 #endif 548 zs_set_speed(cs, cs->cs_defspeed); 549 cs->cs_creg[12] = cs->cs_preg[12]; 550 cs->cs_creg[13] = cs->cs_preg[13]; 551 552 /* Clear the master interrupt enable. */ 553 zs_write_reg(cs, 9, 0); 554 555 /* Reset the whole SCC chip. */ 556 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 557 558 /* Copy "pending" to "current" and H/W. */ 559 zs_loadchannelregs(cs); 560 } 561 562 /* 563 * Polled console input putchar. 564 */ 565 int 566 zsc_pcccngetc(dev) 567 dev_t dev; 568 { 569 struct zs_chanstate *cs = zs_conschan; 570 int c; 571 572 c = zs_getc(cs); 573 return (c); 574 } 575 576 /* 577 * Polled console output putchar. 578 */ 579 void 580 zsc_pcccnputc(dev, c) 581 dev_t dev; 582 int c; 583 { 584 struct zs_chanstate *cs = zs_conschan; 585 586 zs_putc(cs, c); 587 } 588 589 /* 590 * Handle user request to enter kernel debugger. 591 */ 592 void 593 zs_abort(cs) 594 struct zs_chanstate *cs; 595 { 596 int rr0; 597 598 /* Wait for end of break to avoid PROM abort. */ 599 /* XXX - Limit the wait? */ 600 do { 601 rr0 = *cs->cs_reg_csr; 602 ZS_DELAY(); 603 } while (rr0 & ZSRR0_BREAK); 604 605 mvme68k_abort("SERIAL LINE ABORT"); 606 } 607
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