zs.c revision 1.31
1 /* $NetBSD: zs.c,v 1.31 2003/01/28 12:35:33 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.ORG> 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <dev/cons.h> 61 #include <dev/ic/z8530reg.h> 62 #include <machine/z8530var.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <mvme68k/dev/zsvar.h> 69 70 /* 71 * Some warts needed by z8530tty.c - 72 * The default parity REALLY needs to be the same as the PROM uses, 73 * or you can not see messages done with printf during boot-up... 74 */ 75 int zs_def_cflag = (CREAD | CS8 | HUPCL); 76 77 /* Flags from zscnprobe() */ 78 static int zs_hwflags[NZSC][2]; 79 80 /* Default speed for each channel */ 81 static int zs_defspeed[NZSC][2] = { 82 { 9600, /* port 1 */ 83 9600 }, /* port 2 */ 84 { 9600, /* port 3 */ 85 9600 }, /* port 4 */ 86 }; 87 88 static struct zs_chanstate zs_conschan_store; 89 static struct zs_chanstate *zs_conschan; 90 91 u_char zs_init_reg[16] = { 92 0, /* 0: CMD (reset, etc.) */ 93 0, /* 1: No interrupts yet. */ 94 0x18 + ZSHARD_PRI, /* IVECT */ 95 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 96 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 97 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 98 0, /* 6: TXSYNC/SYNCLO */ 99 0, /* 7: RXSYNC/SYNCHI */ 100 0, /* 8: alias for data port */ 101 ZSWR9_MASTER_IE, 102 0, /*10: Misc. TX/RX control bits */ 103 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 104 0, /*12: BAUDLO (default=9600) */ 105 0, /*13: BAUDHI (default=9600) */ 106 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 107 ZSWR15_BREAK_IE, 108 }; 109 110 111 /**************************************************************** 112 * Autoconfig 113 ****************************************************************/ 114 115 /* Definition of the driver for autoconfig. */ 116 static int zsc_print __P((void *, const char *name)); 117 int zs_getc __P((void *)); 118 void zs_putc __P((void *, int)); 119 120 #if 0 121 static int zs_get_speed __P((struct zs_chanstate *)); 122 #endif 123 124 extern struct cfdriver zsc_cd; 125 126 cons_decl(zsc_pcc); 127 128 129 /* 130 * Configure children of an SCC. 131 */ 132 void 133 zs_config(zsc, zs, vector, pclk) 134 struct zsc_softc *zsc; 135 struct zsdevice *zs; 136 int vector, pclk; 137 { 138 struct zsc_attach_args zsc_args; 139 volatile struct zschan *zc; 140 struct zs_chanstate *cs; 141 int zsc_unit, channel, s; 142 143 zsc_unit = zsc->zsc_dev.dv_unit; 144 printf(": Zilog 8530 SCC at vector 0x%x\n", vector); 145 146 /* 147 * Initialize software state for each channel. 148 */ 149 for (channel = 0; channel < 2; channel++) { 150 zsc_args.channel = channel; 151 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 152 cs = &zsc->zsc_cs_store[channel]; 153 zsc->zsc_cs[channel] = cs; 154 simple_lock_init(&cs->cs_lock); 155 156 /* 157 * If we're the console, copy the channel state, and 158 * adjust the console channel pointer. 159 */ 160 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 161 memcpy(cs, zs_conschan, sizeof(struct zs_chanstate)); 162 zs_conschan = cs; 163 } else { 164 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 165 cs->cs_reg_csr = zc->zc_csr; 166 cs->cs_reg_data = zc->zc_data; 167 memcpy(cs->cs_creg, zs_init_reg, 16); 168 memcpy(cs->cs_preg, zs_init_reg, 16); 169 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 170 } 171 172 cs->cs_brg_clk = pclk / 16; 173 cs->cs_creg[2] = cs->cs_preg[2] = vector; 174 zs_set_speed(cs, cs->cs_defspeed); 175 cs->cs_creg[12] = cs->cs_preg[12]; 176 cs->cs_creg[13] = cs->cs_preg[13]; 177 cs->cs_defcflag = zs_def_cflag; 178 179 /* Make these correspond to cs_defcflag (-crtscts) */ 180 cs->cs_rr0_dcd = ZSRR0_DCD; 181 cs->cs_rr0_cts = 0; 182 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 183 cs->cs_wr5_rts = 0; 184 185 cs->cs_channel = channel; 186 cs->cs_private = NULL; 187 cs->cs_ops = &zsops_null; 188 189 /* 190 * Clear the master interrupt enable. 191 * The INTENA is common to both channels, 192 * so just do it on the A channel. 193 * Write the interrupt vector while we're at it. 194 */ 195 if (channel == 0) { 196 zs_write_reg(cs, 9, 0); 197 zs_write_reg(cs, 2, vector); 198 } 199 200 /* 201 * Look for a child driver for this channel. 202 * The child attach will setup the hardware. 203 */ 204 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 205 /* No sub-driver. Just reset it. */ 206 u_char reset = (channel == 0) ? 207 ZSWR9_A_RESET : ZSWR9_B_RESET; 208 s = splzs(); 209 zs_write_reg(cs, 9, reset); 210 splx(s); 211 } 212 } 213 214 /* 215 * Allocate a software interrupt cookie. 216 */ 217 zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL, 218 (void (*)(void *)) zsc_intr_soft, zsc); 219 #ifdef DEBUG 220 assert(zsc->zsc_softintr_cookie); 221 #endif 222 } 223 224 static int 225 zsc_print(aux, name) 226 void *aux; 227 const char *name; 228 { 229 struct zsc_attach_args *args = aux; 230 231 if (name != NULL) 232 aprint_normal("%s: ", name); 233 234 if (args->channel != -1) 235 aprint_normal(" channel %d", args->channel); 236 237 return UNCONF; 238 } 239 240 #if defined(MVME162) || defined(MVME172) 241 /* 242 * Our ZS chips each have their own interrupt vector. 243 */ 244 int 245 zshard_unshared(arg) 246 void *arg; 247 { 248 struct zsc_softc *zsc = arg; 249 int rval; 250 251 rval = zsc_intr_hard(zsc); 252 253 if (rval) { 254 if ((zsc->zsc_cs[0]->cs_softreq) || 255 (zsc->zsc_cs[1]->cs_softreq)) 256 softintr_schedule(zsc->zsc_softintr_cookie); 257 zsc->zsc_evcnt.ev_count++; 258 } 259 260 return (rval); 261 } 262 #endif 263 264 #ifdef MVME147 265 /* 266 * Our ZS chips all share a common, PCC-vectored interrupt, 267 * so we have to look at all of them on each interrupt. 268 */ 269 int 270 zshard_shared(arg) 271 void *arg; 272 { 273 struct zsc_softc *zsc; 274 int unit, rval; 275 276 rval = 0; 277 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 278 zsc = zsc_cd.cd_devs[unit]; 279 if (zsc != NULL && zsc_intr_hard(zsc)) { 280 if ((zsc->zsc_cs[0]->cs_softreq) || 281 (zsc->zsc_cs[1]->cs_softreq)) 282 softintr_schedule(zsc->zsc_softintr_cookie); 283 zsc->zsc_evcnt.ev_count++; 284 rval++; 285 } 286 } 287 return (rval); 288 } 289 #endif 290 291 292 #if 0 293 /* 294 * Compute the current baud rate given a ZSCC channel. 295 */ 296 static int 297 zs_get_speed(cs) 298 struct zs_chanstate *cs; 299 { 300 int tconst; 301 302 tconst = zs_read_reg(cs, 12); 303 tconst |= zs_read_reg(cs, 13) << 8; 304 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 305 } 306 #endif 307 308 /* 309 * MD functions for setting the baud rate and control modes. 310 */ 311 int 312 zs_set_speed(cs, bps) 313 struct zs_chanstate *cs; 314 int bps; /* bits per second */ 315 { 316 int tconst, real_bps; 317 318 if (bps == 0) 319 return (0); 320 321 #ifdef DIAGNOSTIC 322 if (cs->cs_brg_clk == 0) 323 panic("zs_set_speed"); 324 #endif 325 326 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 327 if (tconst < 0) 328 return (EINVAL); 329 330 /* Convert back to make sure we can do it. */ 331 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 332 333 /* Allow 2% tolerance WRT the required bps */ 334 if (((abs(real_bps - bps) * 1000) / bps) > 20) 335 return (EINVAL); 336 337 cs->cs_preg[12] = tconst; 338 cs->cs_preg[13] = tconst >> 8; 339 340 /* Caller will stuff the pending registers. */ 341 return (0); 342 } 343 344 int 345 zs_set_modes(cs, cflag) 346 struct zs_chanstate *cs; 347 int cflag; /* bits per second */ 348 { 349 int s; 350 351 /* 352 * Output hardware flow control on the chip is horrendous: 353 * if carrier detect drops, the receiver is disabled, and if 354 * CTS drops, the transmitter is stoped IN MID CHARACTER! 355 * Therefore, NEVER set the HFC bit, and instead use the 356 * status interrupt to detect CTS changes. 357 */ 358 s = splzs(); 359 cs->cs_rr0_pps = 0; 360 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 361 cs->cs_rr0_dcd = 0; 362 if ((cflag & MDMBUF) == 0) 363 cs->cs_rr0_pps = ZSRR0_DCD; 364 } else 365 cs->cs_rr0_dcd = ZSRR0_DCD; 366 if ((cflag & CRTSCTS) != 0) { 367 cs->cs_wr5_dtr = ZSWR5_DTR; 368 cs->cs_wr5_rts = ZSWR5_RTS; 369 cs->cs_rr0_cts = ZSRR0_CTS; 370 } else if ((cflag & MDMBUF) != 0) { 371 cs->cs_wr5_dtr = 0; 372 cs->cs_wr5_rts = ZSWR5_DTR; 373 cs->cs_rr0_cts = ZSRR0_DCD; 374 } else { 375 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 376 cs->cs_wr5_rts = 0; 377 cs->cs_rr0_cts = 0; 378 } 379 splx(s); 380 381 /* Caller will stuff the pending registers. */ 382 return (0); 383 } 384 385 386 /* 387 * Read or write the chip with suitable delays. 388 */ 389 390 u_char 391 zs_read_reg(cs, reg) 392 struct zs_chanstate *cs; 393 u_char reg; 394 { 395 u_char val; 396 397 *cs->cs_reg_csr = reg; 398 ZS_DELAY(); 399 val = *cs->cs_reg_csr; 400 ZS_DELAY(); 401 return val; 402 } 403 404 void 405 zs_write_reg(cs, reg, val) 406 struct zs_chanstate *cs; 407 u_char reg, val; 408 { 409 *cs->cs_reg_csr = reg; 410 ZS_DELAY(); 411 *cs->cs_reg_csr = val; 412 ZS_DELAY(); 413 } 414 415 u_char zs_read_csr(cs) 416 struct zs_chanstate *cs; 417 { 418 u_char val; 419 420 val = *cs->cs_reg_csr; 421 ZS_DELAY(); 422 return val; 423 } 424 425 void zs_write_csr(cs, val) 426 struct zs_chanstate *cs; 427 u_char val; 428 { 429 *cs->cs_reg_csr = val; 430 ZS_DELAY(); 431 } 432 433 u_char zs_read_data(cs) 434 struct zs_chanstate *cs; 435 { 436 u_char val; 437 438 val = *cs->cs_reg_data; 439 ZS_DELAY(); 440 return val; 441 } 442 443 void zs_write_data(cs, val) 444 struct zs_chanstate *cs; 445 u_char val; 446 { 447 *cs->cs_reg_data = val; 448 ZS_DELAY(); 449 } 450 451 /**************************************************************** 452 * Console support functions (MVME specific!) 453 ****************************************************************/ 454 455 /* 456 * Polled input char. 457 */ 458 int 459 zs_getc(arg) 460 void *arg; 461 { 462 struct zs_chanstate *cs = arg; 463 int s, c, rr0, stat; 464 465 s = splhigh(); 466 top: 467 /* Wait for a character to arrive. */ 468 do { 469 rr0 = *cs->cs_reg_csr; 470 ZS_DELAY(); 471 } while ((rr0 & ZSRR0_RX_READY) == 0); 472 473 /* Read error register. */ 474 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 475 if (stat) { 476 zs_write_csr(cs, ZSM_RESET_ERR); 477 goto top; 478 } 479 480 /* Read character. */ 481 c = *cs->cs_reg_data; 482 ZS_DELAY(); 483 splx(s); 484 485 return (c); 486 } 487 488 /* 489 * Polled output char. 490 */ 491 void 492 zs_putc(arg, c) 493 void *arg; 494 int c; 495 { 496 struct zs_chanstate *cs = arg; 497 int s, rr0; 498 499 s = splhigh(); 500 /* Wait for transmitter to become ready. */ 501 do { 502 rr0 = *cs->cs_reg_csr; 503 ZS_DELAY(); 504 } while ((rr0 & ZSRR0_TX_READY) == 0); 505 506 *cs->cs_reg_data = c; 507 ZS_DELAY(); 508 splx(s); 509 } 510 511 /* 512 * Common parts of console init. 513 */ 514 void 515 zs_cnconfig(zsc_unit, channel, zs, pclk) 516 int zsc_unit, channel; 517 struct zsdevice *zs; 518 int pclk; 519 { 520 struct zs_chanstate *cs; 521 struct zschan *zc; 522 523 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 524 525 /* 526 * Pointer to channel state. Later, the console channel 527 * state is copied into the softc, and the console channel 528 * pointer adjusted to point to the new copy. 529 */ 530 zs_conschan = cs = &zs_conschan_store; 531 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 532 533 /* Setup temporary chanstate. */ 534 cs->cs_brg_clk = pclk / 16; 535 cs->cs_reg_csr = zc->zc_csr; 536 cs->cs_reg_data = zc->zc_data; 537 538 /* Initialize the pending registers. */ 539 memcpy(cs->cs_preg, zs_init_reg, 16); 540 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 541 542 #if 0 543 /* XXX: Preserve BAUD rate from boot loader. */ 544 /* XXX: Also, why reset the chip here? -gwr */ 545 cs->cs_defspeed = zs_get_speed(cs); 546 #else 547 cs->cs_defspeed = 9600; /* XXX */ 548 #endif 549 zs_set_speed(cs, cs->cs_defspeed); 550 cs->cs_creg[12] = cs->cs_preg[12]; 551 cs->cs_creg[13] = cs->cs_preg[13]; 552 553 /* Clear the master interrupt enable. */ 554 zs_write_reg(cs, 9, 0); 555 556 /* Reset the whole SCC chip. */ 557 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 558 559 /* Copy "pending" to "current" and H/W. */ 560 zs_loadchannelregs(cs); 561 } 562 563 /* 564 * Polled console input putchar. 565 */ 566 int 567 zsc_pcccngetc(dev) 568 dev_t dev; 569 { 570 struct zs_chanstate *cs = zs_conschan; 571 int c; 572 573 c = zs_getc(cs); 574 return (c); 575 } 576 577 /* 578 * Polled console output putchar. 579 */ 580 void 581 zsc_pcccnputc(dev, c) 582 dev_t dev; 583 int c; 584 { 585 struct zs_chanstate *cs = zs_conschan; 586 587 zs_putc(cs, c); 588 } 589 590 /* 591 * Handle user request to enter kernel debugger. 592 */ 593 void 594 zs_abort(cs) 595 struct zs_chanstate *cs; 596 { 597 int rr0; 598 599 /* Wait for end of break to avoid PROM abort. */ 600 /* XXX - Limit the wait? */ 601 do { 602 rr0 = *cs->cs_reg_csr; 603 ZS_DELAY(); 604 } while (rr0 & ZSRR0_BREAK); 605 606 mvme68k_abort("SERIAL LINE ABORT"); 607 } 608
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