zs.c revision 1.39
1 /* $NetBSD: zs.c,v 1.39 2008/03/29 19:15:34 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej (at) NetBSD.org> 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.39 2008/03/29 19:15:34 tsutsui Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/conf.h> 54 #include <sys/device.h> 55 #include <sys/file.h> 56 #include <sys/ioctl.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> 59 #include <sys/tty.h> 60 #include <sys/time.h> 61 #include <sys/syslog.h> 62 #include <sys/cpu.h> 63 #include <sys/bus.h> 64 #include <sys/intr.h> 65 66 #include <dev/cons.h> 67 #include <dev/ic/z8530reg.h> 68 #include <machine/z8530var.h> 69 70 #include <mvme68k/dev/zsvar.h> 71 72 #include "ioconf.h" 73 74 /* 75 * Some warts needed by z8530tty.c - 76 * The default parity REALLY needs to be the same as the PROM uses, 77 * or you can not see messages done with printf during boot-up... 78 */ 79 int zs_def_cflag = (CREAD | CS8 | HUPCL); 80 81 /* Flags from zscnprobe() */ 82 static int zs_hwflags[NZSC][2]; 83 84 /* Default speed for each channel */ 85 static int zs_defspeed[NZSC][2] = { 86 { 9600, /* port 1 */ 87 9600 }, /* port 2 */ 88 { 9600, /* port 3 */ 89 9600 }, /* port 4 */ 90 }; 91 92 static struct zs_chanstate zs_conschan_store; 93 static struct zs_chanstate *zs_conschan; 94 95 uint8_t zs_init_reg[16] = { 96 0, /* 0: CMD (reset, etc.) */ 97 0, /* 1: No interrupts yet. */ 98 0x18 + ZSHARD_PRI, /* IVECT */ 99 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 100 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 101 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 102 0, /* 6: TXSYNC/SYNCLO */ 103 0, /* 7: RXSYNC/SYNCHI */ 104 0, /* 8: alias for data port */ 105 ZSWR9_MASTER_IE, 106 0, /*10: Misc. TX/RX control bits */ 107 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 108 0, /*12: BAUDLO (default=9600) */ 109 0, /*13: BAUDHI (default=9600) */ 110 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 111 ZSWR15_BREAK_IE, 112 }; 113 114 115 /**************************************************************** 116 * Autoconfig 117 ****************************************************************/ 118 119 /* Definition of the driver for autoconfig. */ 120 static int zsc_print(void *, const char *name); 121 int zs_getc(void *); 122 void zs_putc(void *, int); 123 124 #if 0 125 static int zs_get_speed(struct zs_chanstate *); 126 #endif 127 128 cons_decl(zsc_pcc); 129 130 131 /* 132 * Configure children of an SCC. 133 */ 134 void 135 zs_config(struct zsc_softc *zsc, struct zsdevice *zs, int vector, int pclk) 136 { 137 struct zsc_attach_args zsc_args; 138 volatile struct zschan *zc; 139 struct zs_chanstate *cs; 140 int zsc_unit, channel, s; 141 142 zsc_unit = device_unit(zsc->zsc_dev); 143 printf(": Zilog 8530 SCC at vector 0x%x\n", vector); 144 145 /* 146 * Initialize software state for each channel. 147 */ 148 for (channel = 0; channel < 2; channel++) { 149 zsc_args.channel = channel; 150 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 151 cs = &zsc->zsc_cs_store[channel]; 152 zsc->zsc_cs[channel] = cs; 153 zs_lock_init(cs); 154 155 /* 156 * If we're the console, copy the channel state, and 157 * adjust the console channel pointer. 158 */ 159 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 160 memcpy(cs, zs_conschan, sizeof(struct zs_chanstate)); 161 zs_conschan = cs; 162 } else { 163 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 164 cs->cs_reg_csr = zc->zc_csr; 165 cs->cs_reg_data = zc->zc_data; 166 memcpy(cs->cs_creg, zs_init_reg, 16); 167 memcpy(cs->cs_preg, zs_init_reg, 16); 168 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 169 } 170 171 cs->cs_brg_clk = pclk / 16; 172 cs->cs_creg[2] = cs->cs_preg[2] = vector; 173 zs_set_speed(cs, cs->cs_defspeed); 174 cs->cs_creg[12] = cs->cs_preg[12]; 175 cs->cs_creg[13] = cs->cs_preg[13]; 176 cs->cs_defcflag = zs_def_cflag; 177 178 /* Make these correspond to cs_defcflag (-crtscts) */ 179 cs->cs_rr0_dcd = ZSRR0_DCD; 180 cs->cs_rr0_cts = 0; 181 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 182 cs->cs_wr5_rts = 0; 183 184 cs->cs_channel = channel; 185 cs->cs_private = NULL; 186 cs->cs_ops = &zsops_null; 187 188 /* 189 * Clear the master interrupt enable. 190 * The INTENA is common to both channels, 191 * so just do it on the A channel. 192 * Write the interrupt vector while we're at it. 193 */ 194 if (channel == 0) { 195 zs_write_reg(cs, 9, 0); 196 zs_write_reg(cs, 2, vector); 197 } 198 199 /* 200 * Look for a child driver for this channel. 201 * The child attach will setup the hardware. 202 */ 203 if (!config_found(zsc->zsc_dev, (void *)&zsc_args, 204 zsc_print)) { 205 /* No sub-driver. Just reset it. */ 206 uint8_t reset = (channel == 0) ? 207 ZSWR9_A_RESET : ZSWR9_B_RESET; 208 s = splzs(); 209 zs_write_reg(cs, 9, reset); 210 splx(s); 211 } 212 } 213 214 /* 215 * Allocate a software interrupt cookie. 216 */ 217 zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL, 218 (void (*)(void *)) zsc_intr_soft, zsc); 219 #ifdef DEBUG 220 assert(zsc->zsc_softintr_cookie); 221 #endif 222 } 223 224 static int 225 zsc_print(void *aux, const char *name) 226 { 227 struct zsc_attach_args *args = aux; 228 229 if (name != NULL) 230 aprint_normal("%s: ", name); 231 232 if (args->channel != -1) 233 aprint_normal(" channel %d", args->channel); 234 235 return UNCONF; 236 } 237 238 #if defined(MVME162) || defined(MVME172) 239 /* 240 * Our ZS chips each have their own interrupt vector. 241 */ 242 int 243 zshard_unshared(void *arg) 244 { 245 struct zsc_softc *zsc = arg; 246 int rval; 247 248 rval = zsc_intr_hard(zsc); 249 250 if (rval) { 251 if ((zsc->zsc_cs[0]->cs_softreq) || 252 (zsc->zsc_cs[1]->cs_softreq)) 253 softint_schedule(zsc->zsc_softintr_cookie); 254 zsc->zsc_evcnt.ev_count++; 255 } 256 257 return rval; 258 } 259 #endif 260 261 #ifdef MVME147 262 /* 263 * Our ZS chips all share a common, PCC-vectored interrupt, 264 * so we have to look at all of them on each interrupt. 265 */ 266 int 267 zshard_shared(void *arg) 268 { 269 struct zsc_softc *zsc; 270 int unit, rval; 271 272 rval = 0; 273 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 274 zsc = device_private(zsc_cd.cd_devs[unit]); 275 if (zsc != NULL && zsc_intr_hard(zsc)) { 276 if ((zsc->zsc_cs[0]->cs_softreq) || 277 (zsc->zsc_cs[1]->cs_softreq)) 278 softint_schedule(zsc->zsc_softintr_cookie); 279 zsc->zsc_evcnt.ev_count++; 280 rval++; 281 } 282 } 283 return rval; 284 } 285 #endif 286 287 288 #if 0 289 /* 290 * Compute the current baud rate given a ZSCC channel. 291 */ 292 static int 293 zs_get_speed(struct zs_chanstate *cs) 294 { 295 int tconst; 296 297 tconst = zs_read_reg(cs, 12); 298 tconst |= zs_read_reg(cs, 13) << 8; 299 return TCONST_TO_BPS(cs->cs_brg_clk, tconst); 300 } 301 #endif 302 303 /* 304 * MD functions for setting the baud rate and control modes. 305 */ 306 int 307 zs_set_speed(struct zs_chanstate *cs, int bps) 308 { 309 int tconst, real_bps; 310 311 if (bps == 0) 312 return 0; 313 314 #ifdef DIAGNOSTIC 315 if (cs->cs_brg_clk == 0) 316 panic("zs_set_speed"); 317 #endif 318 319 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 320 if (tconst < 0) 321 return EINVAL; 322 323 /* Convert back to make sure we can do it. */ 324 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 325 326 /* Allow 2% tolerance WRT the required bps */ 327 if (((abs(real_bps - bps) * 1000) / bps) > 20) 328 return EINVAL; 329 330 cs->cs_preg[12] = tconst; 331 cs->cs_preg[13] = tconst >> 8; 332 333 /* Caller will stuff the pending registers. */ 334 return 0; 335 } 336 337 int 338 zs_set_modes(struct zs_chanstate *cs, int cflag) 339 { 340 int s; 341 342 /* 343 * Output hardware flow control on the chip is horrendous: 344 * if carrier detect drops, the receiver is disabled, and if 345 * CTS drops, the transmitter is stoped IN MID CHARACTER! 346 * Therefore, NEVER set the HFC bit, and instead use the 347 * status interrupt to detect CTS changes. 348 */ 349 s = splzs(); 350 cs->cs_rr0_pps = 0; 351 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 352 cs->cs_rr0_dcd = 0; 353 if ((cflag & MDMBUF) == 0) 354 cs->cs_rr0_pps = ZSRR0_DCD; 355 } else 356 cs->cs_rr0_dcd = ZSRR0_DCD; 357 if ((cflag & CRTSCTS) != 0) { 358 cs->cs_wr5_dtr = ZSWR5_DTR; 359 cs->cs_wr5_rts = ZSWR5_RTS; 360 cs->cs_rr0_cts = ZSRR0_CTS; 361 } else if ((cflag & MDMBUF) != 0) { 362 cs->cs_wr5_dtr = 0; 363 cs->cs_wr5_rts = ZSWR5_DTR; 364 cs->cs_rr0_cts = ZSRR0_DCD; 365 } else { 366 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 367 cs->cs_wr5_rts = 0; 368 cs->cs_rr0_cts = 0; 369 } 370 splx(s); 371 372 /* Caller will stuff the pending registers. */ 373 return 0; 374 } 375 376 377 /* 378 * Read or write the chip with suitable delays. 379 */ 380 381 uint8_t 382 zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 383 { 384 uint8_t val; 385 386 *cs->cs_reg_csr = reg; 387 ZS_DELAY(); 388 val = *cs->cs_reg_csr; 389 ZS_DELAY(); 390 return val; 391 } 392 393 void 394 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 395 { 396 397 *cs->cs_reg_csr = reg; 398 ZS_DELAY(); 399 *cs->cs_reg_csr = val; 400 ZS_DELAY(); 401 } 402 403 uint8_t 404 zs_read_csr(struct zs_chanstate *cs) 405 { 406 uint8_t val; 407 408 val = *cs->cs_reg_csr; 409 ZS_DELAY(); 410 return val; 411 } 412 413 void 414 zs_write_csr(struct zs_chanstate *cs, uint8_t val) 415 { 416 417 *cs->cs_reg_csr = val; 418 ZS_DELAY(); 419 } 420 421 uint8_t 422 zs_read_data(struct zs_chanstate *cs) 423 { 424 uint8_t val; 425 426 val = *cs->cs_reg_data; 427 ZS_DELAY(); 428 return val; 429 } 430 431 void 432 zs_write_data(struct zs_chanstate *cs, uint8_t val) 433 { 434 435 *cs->cs_reg_data = val; 436 ZS_DELAY(); 437 } 438 439 /**************************************************************** 440 * Console support functions (MVME specific!) 441 ****************************************************************/ 442 443 /* 444 * Polled input char. 445 */ 446 int 447 zs_getc(void *arg) 448 { 449 struct zs_chanstate *cs = arg; 450 int s, c, rr0, stat; 451 452 s = splhigh(); 453 top: 454 /* Wait for a character to arrive. */ 455 do { 456 rr0 = *cs->cs_reg_csr; 457 ZS_DELAY(); 458 } while ((rr0 & ZSRR0_RX_READY) == 0); 459 460 /* Read error register. */ 461 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 462 if (stat) { 463 zs_write_csr(cs, ZSM_RESET_ERR); 464 goto top; 465 } 466 467 /* Read character. */ 468 c = *cs->cs_reg_data; 469 ZS_DELAY(); 470 splx(s); 471 472 return c; 473 } 474 475 /* 476 * Polled output char. 477 */ 478 void 479 zs_putc(void *arg, int c) 480 { 481 struct zs_chanstate *cs = arg; 482 int s, rr0; 483 484 s = splhigh(); 485 /* Wait for transmitter to become ready. */ 486 do { 487 rr0 = *cs->cs_reg_csr; 488 ZS_DELAY(); 489 } while ((rr0 & ZSRR0_TX_READY) == 0); 490 491 *cs->cs_reg_data = c; 492 ZS_DELAY(); 493 splx(s); 494 } 495 496 /* 497 * Common parts of console init. 498 */ 499 void 500 zs_cnconfig(int zsc_unit, int channel, struct zsdevice *zs, int pclk) 501 { 502 struct zs_chanstate *cs; 503 struct zschan *zc; 504 505 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 506 507 /* 508 * Pointer to channel state. Later, the console channel 509 * state is copied into the softc, and the console channel 510 * pointer adjusted to point to the new copy. 511 */ 512 zs_conschan = cs = &zs_conschan_store; 513 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 514 515 /* Setup temporary chanstate. */ 516 cs->cs_brg_clk = pclk / 16; 517 cs->cs_reg_csr = zc->zc_csr; 518 cs->cs_reg_data = zc->zc_data; 519 520 /* Initialize the pending registers. */ 521 memcpy(cs->cs_preg, zs_init_reg, 16); 522 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 523 524 #if 0 525 /* XXX: Preserve BAUD rate from boot loader. */ 526 /* XXX: Also, why reset the chip here? -gwr */ 527 cs->cs_defspeed = zs_get_speed(cs); 528 #else 529 cs->cs_defspeed = 9600; /* XXX */ 530 #endif 531 zs_set_speed(cs, cs->cs_defspeed); 532 cs->cs_creg[12] = cs->cs_preg[12]; 533 cs->cs_creg[13] = cs->cs_preg[13]; 534 535 /* Clear the master interrupt enable. */ 536 zs_write_reg(cs, 9, 0); 537 538 /* Reset the whole SCC chip. */ 539 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 540 541 /* Copy "pending" to "current" and H/W. */ 542 zs_loadchannelregs(cs); 543 } 544 545 /* 546 * Polled console input putchar. 547 */ 548 int 549 zsc_pcccngetc(dev_t dev) 550 { 551 struct zs_chanstate *cs = zs_conschan; 552 int c; 553 554 c = zs_getc(cs); 555 return c; 556 } 557 558 /* 559 * Polled console output putchar. 560 */ 561 void 562 zsc_pcccnputc(dev_t dev, int c) 563 { 564 struct zs_chanstate *cs = zs_conschan; 565 566 zs_putc(cs, c); 567 } 568 569 /* 570 * Handle user request to enter kernel debugger. 571 */ 572 void 573 zs_abort(struct zs_chanstate *cs) 574 { 575 int rr0; 576 577 /* Wait for end of break to avoid PROM abort. */ 578 /* XXX - Limit the wait? */ 579 do { 580 rr0 = *cs->cs_reg_csr; 581 ZS_DELAY(); 582 } while (rr0 & ZSRR0_BREAK); 583 584 mvme68k_abort("SERIAL LINE ABORT"); 585 } 586
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