bus_space.h revision 1.10 1 1.10 perry /* $NetBSD: bus_space.h,v 1.10 2005/12/24 20:07:19 perry Exp $ */
2 1.2 scw
3 1.2 scw /*-
4 1.2 scw * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
5 1.2 scw * All rights reserved.
6 1.2 scw *
7 1.2 scw * This code is derived from software contributed to The NetBSD Foundation
8 1.2 scw * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.2 scw * NASA Ames Research Center.
10 1.2 scw *
11 1.2 scw * Redistribution and use in source and binary forms, with or without
12 1.2 scw * modification, are permitted provided that the following conditions
13 1.2 scw * are met:
14 1.2 scw * 1. Redistributions of source code must retain the above copyright
15 1.2 scw * notice, this list of conditions and the following disclaimer.
16 1.2 scw * 2. Redistributions in binary form must reproduce the above copyright
17 1.2 scw * notice, this list of conditions and the following disclaimer in the
18 1.2 scw * documentation and/or other materials provided with the distribution.
19 1.2 scw * 3. All advertising materials mentioning features or use of this software
20 1.2 scw * must display the following acknowledgement:
21 1.2 scw * This product includes software developed by the NetBSD
22 1.2 scw * Foundation, Inc. and its contributors.
23 1.2 scw * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.2 scw * contributors may be used to endorse or promote products derived
25 1.2 scw * from this software without specific prior written permission.
26 1.2 scw *
27 1.2 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.2 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.2 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.2 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.2 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.2 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.2 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.2 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.2 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.2 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.2 scw * POSSIBILITY OF SUCH DAMAGE.
38 1.2 scw */
39 1.2 scw
40 1.2 scw /*
41 1.2 scw * Copyright (C) 1997 Scott Reynolds. All rights reserved.
42 1.2 scw *
43 1.2 scw * Redistribution and use in source and binary forms, with or without
44 1.2 scw * modification, are permitted provided that the following conditions
45 1.2 scw * are met:
46 1.2 scw * 1. Redistributions of source code must retain the above copyright
47 1.2 scw * notice, this list of conditions and the following disclaimer.
48 1.2 scw * 2. Redistributions in binary form must reproduce the above copyright
49 1.2 scw * notice, this list of conditions and the following disclaimer in the
50 1.2 scw * documentation and/or other materials provided with the distribution.
51 1.2 scw * 3. The name of the author may not be used to endorse or promote products
52 1.2 scw * derived from this software without specific prior written permission
53 1.2 scw *
54 1.2 scw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
55 1.2 scw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
56 1.2 scw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
57 1.2 scw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
58 1.2 scw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
59 1.2 scw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 1.2 scw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 1.2 scw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 1.2 scw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
63 1.2 scw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 1.2 scw */
65 1.2 scw
66 1.2 scw /*
67 1.2 scw * Lifted from the Next68k port.
68 1.2 scw * Modified for mvme68k by Steve Woodford.
69 1.2 scw *
70 1.2 scw * TODO: Support for VMEbus...
71 1.2 scw * (Do any existing VME card drivers use bus_space_* ?)
72 1.2 scw */
73 1.2 scw
74 1.2 scw #ifndef _MVME68K_BUS_SPACE_H_
75 1.2 scw #define _MVME68K_BUS_SPACE_H_
76 1.6 scw
77 1.2 scw /*
78 1.2 scw * Addresses (in bus space).
79 1.2 scw */
80 1.2 scw typedef u_long bus_addr_t;
81 1.2 scw typedef u_long bus_size_t;
82 1.2 scw
83 1.2 scw /*
84 1.2 scw * Access methods for bus resources and address space.
85 1.2 scw */
86 1.6 scw struct mvme68k_bus_space_tag;
87 1.6 scw typedef struct mvme68k_bus_space_tag *bus_space_tag_t;
88 1.2 scw typedef u_long bus_space_handle_t;
89 1.2 scw
90 1.6 scw struct mvme68k_bus_space_tag {
91 1.6 scw void *bs_cookie;
92 1.6 scw int (*bs_map)(void *, bus_addr_t, bus_size_t,
93 1.6 scw int, bus_space_handle_t *);
94 1.6 scw void (*bs_unmap)(void *, bus_space_handle_t, bus_size_t);
95 1.6 scw int (*bs_peek_1)(void *, bus_space_handle_t,
96 1.6 scw bus_size_t, u_int8_t *);
97 1.6 scw int (*bs_peek_2)(void *, bus_space_handle_t,
98 1.6 scw bus_size_t, u_int16_t *);
99 1.6 scw int (*bs_peek_4)(void *, bus_space_handle_t,
100 1.6 scw bus_size_t, u_int32_t *);
101 1.6 scw #if 0
102 1.6 scw int (*bs_peek_8)(void *, bus_space_handle_t,
103 1.6 scw bus_size_t, u_int64_t *);
104 1.6 scw #endif
105 1.6 scw int (*bs_poke_1)(void *, bus_space_handle_t,
106 1.6 scw bus_size_t, u_int8_t);
107 1.6 scw int (*bs_poke_2)(void *, bus_space_handle_t,
108 1.6 scw bus_size_t, u_int16_t);
109 1.6 scw int (*bs_poke_4)(void *, bus_space_handle_t,
110 1.6 scw bus_size_t, u_int32_t);
111 1.6 scw #if 0
112 1.6 scw int (*bs_poke_8)(void *, bus_space_handle_t,
113 1.6 scw bus_size_t, u_int64_t);
114 1.6 scw #endif
115 1.6 scw };
116 1.2 scw
117 1.2 scw /*
118 1.6 scw * int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
119 1.6 scw * bus_size_t size, int flags,
120 1.6 scw * bus_space_handle_t *bshp);
121 1.5 scw *
122 1.5 scw * Map a region of bus space.
123 1.2 scw */
124 1.6 scw #define bus_space_map(tag, offset, size, flags, handlep) \
125 1.6 scw (*((tag)->bs_map))((tag)->bs_cookie, (offset), (size), (flags), (handlep))
126 1.2 scw
127 1.5 scw /*
128 1.5 scw * Possible values for the 'flags' parameter of bus_space_map()
129 1.5 scw */
130 1.2 scw #define BUS_SPACE_MAP_CACHEABLE 0x01
131 1.2 scw #define BUS_SPACE_MAP_LINEAR 0x02
132 1.4 drochner #define BUS_SPACE_MAP_PREFETCHABLE 0x04
133 1.5 scw
134 1.5 scw /*
135 1.6 scw * void bus_space_unmap(bus_space_tag_t t,
136 1.6 scw * bus_space_handle_t bsh, bus_size_t size);
137 1.5 scw *
138 1.5 scw * Unmap a region of bus space.
139 1.5 scw */
140 1.6 scw #define bus_space_unmap(tag, handle, size) \
141 1.6 scw (*((tag)->bs_unmap))((tag)->bs_cookie, (handle), (size))
142 1.5 scw
143 1.6 scw /*
144 1.6 scw * int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t h
145 1.6 scw * bus_addr_t offset, bus_size_t size, bus_space_handle_t *newh);
146 1.6 scw *
147 1.6 scw * Allocate a sub-region of an existing map
148 1.6 scw */
149 1.5 scw #define bus_space_subregion(t, h, o, s, hp) \
150 1.6 scw ((*(hp)=(h)+(o)), 0)
151 1.2 scw
152 1.2 scw /*
153 1.2 scw * Allocation and deallocation operations.
154 1.2 scw */
155 1.2 scw #define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \
156 1.2 scw (-1)
157 1.2 scw
158 1.2 scw #define bus_space_free(t, h, s)
159 1.2 scw
160 1.2 scw /*
161 1.6 scw * int bus_space_peek_N(bus_space_tag_t tag,
162 1.6 scw * bus_space_handle_t bsh, bus_size_t offset, u_intN_t *valuep);
163 1.6 scw *
164 1.6 scw * Cautiously read 1, 2, 4 or 8 byte quantity from bus space described
165 1.6 scw * by tag/handle/offset.
166 1.6 scw * If no hardware responds to the read access, the function returns a
167 1.6 scw * non-zero value. Otherwise the value read is placed in `valuep'.
168 1.6 scw */
169 1.6 scw #define bus_space_peek_1(t, h, o, vp) \
170 1.6 scw (*((t)->bs_peek_1))((t)->bs_cookie, (h), (o), (vp))
171 1.6 scw
172 1.6 scw #define bus_space_peek_2(t, h, o, vp) \
173 1.6 scw (*((t)->bs_peek_2))((t)->bs_cookie, (h), (o), (vp))
174 1.6 scw
175 1.6 scw #define bus_space_peek_4(t, h, o, vp) \
176 1.6 scw (*((t)->bs_peek_4))((t)->bs_cookie, (h), (o), (vp))
177 1.6 scw
178 1.6 scw #if 0 /* Cause a link error for bus_space_peek_8 */
179 1.6 scw #define bus_space_peek_8(t, h, o, vp) \
180 1.6 scw (*((t)->bs_peek_8))((t)->bs_cookie, (h), (o), (vp))
181 1.6 scw #endif
182 1.6 scw
183 1.6 scw /*
184 1.6 scw * int bus_space_poke_N(bus_space_tag_t tag,
185 1.6 scw * bus_space_handle_t bsh, bus_size_t offset, u_intN_t value);
186 1.6 scw *
187 1.6 scw * Cautiously write 1, 2, 4 or 8 byte quantity to bus space described
188 1.6 scw * by tag/handle/offset.
189 1.6 scw * If no hardware responds to the write access, the function returns a
190 1.6 scw * non-zero value.
191 1.6 scw */
192 1.6 scw #define bus_space_poke_1(t, h, o, v) \
193 1.6 scw (*((t)->bs_poke_1))((t)->bs_cookie, (h), (o), (v))
194 1.6 scw
195 1.6 scw #define bus_space_poke_2(t, h, o, v) \
196 1.6 scw (*((t)->bs_poke_2))((t)->bs_cookie, (h), (o), (v))
197 1.6 scw
198 1.6 scw #define bus_space_poke_4(t, h, o, v) \
199 1.6 scw (*((t)->bs_poke_4))((t)->bs_cookie, (h), (o), (v))
200 1.6 scw
201 1.6 scw #if 0 /* Cause a link error for bus_space_poke_8 */
202 1.6 scw #define bus_space_poke_8(t, h, o, v) \
203 1.6 scw (*((t)->bs_poke_8))((t)->bs_cookie, (h), (o), (v))
204 1.6 scw #endif
205 1.6 scw
206 1.6 scw /*
207 1.6 scw * u_intN_t bus_space_read_N(bus_space_tag_t tag,
208 1.6 scw * bus_space_handle_t bsh, bus_size_t offset);
209 1.2 scw *
210 1.2 scw * Read a 1, 2, 4, or 8 byte quantity from bus space
211 1.2 scw * described by tag/handle/offset.
212 1.2 scw */
213 1.8 scw #define bus_space_read_1(t,h,o) \
214 1.8 scw (*((volatile u_int8_t *)(intptr_t)((h) + (o))))
215 1.8 scw #define bus_space_read_2(t,h,o) \
216 1.8 scw (*((volatile u_int16_t *)(intptr_t)((h) + (o))))
217 1.8 scw #define bus_space_read_4(t,h,o) \
218 1.8 scw (*((volatile u_int32_t *)(intptr_t)((h) + (o))))
219 1.2 scw
220 1.2 scw /*
221 1.6 scw * void bus_space_read_multi_N(bus_space_tag_t tag,
222 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
223 1.6 scw * u_intN_t *addr, size_t count);
224 1.2 scw *
225 1.2 scw * Read `count' 1, 2, 4, or 8 byte quantities from bus space
226 1.2 scw * described by tag/handle/offset and copy into buffer provided.
227 1.2 scw */
228 1.2 scw
229 1.2 scw #define bus_space_read_multi_1(t, h, o, a, c) do { \
230 1.2 scw (void) t; \
231 1.10 perry __asm volatile (" \
232 1.7 scw movl %0,%%a0 ; \
233 1.7 scw movl %1,%%a1 ; \
234 1.7 scw movl %2,%%d0 ; \
235 1.7 scw 1: movb %%a0@,%%a1@+ ; \
236 1.7 scw subql #1,%%d0 ; \
237 1.2 scw jne 1b" : \
238 1.2 scw : \
239 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
240 1.2 scw "a0","a1","d0"); \
241 1.2 scw } while (0);
242 1.2 scw
243 1.2 scw #define bus_space_read_multi_2(t, h, o, a, c) do { \
244 1.2 scw (void) t; \
245 1.10 perry __asm volatile (" \
246 1.7 scw movl %0,%%a0 ; \
247 1.7 scw movl %1,%%a1 ; \
248 1.7 scw movl %2,%%d0 ; \
249 1.7 scw 1: movw %%a0@,%%a1@+ ; \
250 1.7 scw subql #1,%%d0 ; \
251 1.2 scw jne 1b" : \
252 1.2 scw : \
253 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
254 1.2 scw "a0","a1","d0"); \
255 1.2 scw } while (0);
256 1.2 scw
257 1.2 scw #define bus_space_read_multi_4(t, h, o, a, c) do { \
258 1.2 scw (void) t; \
259 1.10 perry __asm volatile (" \
260 1.7 scw movl %0,%%a0 ; \
261 1.7 scw movl %1,%%a1 ; \
262 1.7 scw movl %2,%%d0 ; \
263 1.7 scw 1: movl %%a0@,%%a1@+ ; \
264 1.7 scw subql #1,%%d0 ; \
265 1.2 scw jne 1b" : \
266 1.2 scw : \
267 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
268 1.2 scw "a0","a1","d0"); \
269 1.2 scw } while (0);
270 1.2 scw
271 1.2 scw #if 0 /* Cause a link error for bus_space_read_multi_8 */
272 1.2 scw #define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!!
273 1.2 scw #endif
274 1.2 scw
275 1.2 scw /*
276 1.6 scw * void bus_space_read_region_N(bus_space_tag_t tag,
277 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
278 1.6 scw * u_intN_t *addr, size_t count);
279 1.2 scw *
280 1.2 scw * Read `count' 1, 2, 4, or 8 byte quantities from bus space
281 1.2 scw * described by tag/handle and starting at `offset' and copy into
282 1.2 scw * buffer provided.
283 1.2 scw */
284 1.2 scw
285 1.2 scw #define bus_space_read_region_1(t, h, o, a, c) do { \
286 1.2 scw (void) t; \
287 1.10 perry __asm volatile (" \
288 1.7 scw movl %0,%%a0 ; \
289 1.7 scw movl %1,%%a1 ; \
290 1.7 scw movl %2,%%d0 ; \
291 1.7 scw 1: movb %%a0@+,%%a1@+ ; \
292 1.7 scw subql #1,%%d0 ; \
293 1.2 scw jne 1b" : \
294 1.2 scw : \
295 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
296 1.2 scw "a0","a1","d0"); \
297 1.2 scw } while (0);
298 1.2 scw
299 1.2 scw #define bus_space_read_region_2(t, h, o, a, c) do { \
300 1.2 scw (void) t; \
301 1.10 perry __asm volatile (" \
302 1.7 scw movl %0,%%a0 ; \
303 1.7 scw movl %1,%%a1 ; \
304 1.7 scw movl %2,%%d0 ; \
305 1.7 scw 1: movw %%a0@+,%%a1@+ ; \
306 1.7 scw subql #1,%%d0 ; \
307 1.2 scw jne 1b" : \
308 1.2 scw : \
309 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
310 1.2 scw "a0","a1","d0"); \
311 1.2 scw } while (0);
312 1.2 scw
313 1.2 scw #define bus_space_read_region_4(t, h, o, a, c) do { \
314 1.2 scw (void) t; \
315 1.10 perry __asm volatile (" \
316 1.7 scw movl %0,%%a0 ; \
317 1.7 scw movl %1,%%a1 ; \
318 1.7 scw movl %2,%%d0 ; \
319 1.7 scw 1: movl %%a0@+,%%a1@+ ; \
320 1.7 scw subql #1,%%d0 ; \
321 1.2 scw jne 1b" : \
322 1.2 scw : \
323 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
324 1.2 scw "a0","a1","d0"); \
325 1.2 scw } while (0);
326 1.2 scw
327 1.2 scw #if 0 /* Cause a link error for bus_space_read_region_8 */
328 1.2 scw #define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!!
329 1.2 scw #endif
330 1.2 scw
331 1.2 scw /*
332 1.6 scw * void bus_space_write_N(bus_space_tag_t tag,
333 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
334 1.6 scw * u_intN_t value);
335 1.2 scw *
336 1.2 scw * Write the 1, 2, 4, or 8 byte value `value' to bus space
337 1.2 scw * described by tag/handle/offset.
338 1.2 scw */
339 1.8 scw #define bus_space_write_1(t,h,o,v) \
340 1.8 scw do { \
341 1.8 scw *((volatile u_int8_t *)(intptr_t)((h) + (o))) = (v); \
342 1.8 scw } while (/*CONSTCOND*/0)
343 1.8 scw #define bus_space_write_2(t,h,o,v) \
344 1.8 scw do { \
345 1.8 scw *((volatile u_int16_t *)(intptr_t)((h) + (o))) = (v); \
346 1.8 scw } while (/*CONSTCOND*/0)
347 1.8 scw #define bus_space_write_4(t,h,o,v) \
348 1.8 scw do { \
349 1.8 scw *((volatile u_int32_t *)(intptr_t)((h) + (o))) = (v); \
350 1.8 scw } while (/*CONSTCOND*/0)
351 1.2 scw
352 1.2 scw /*
353 1.6 scw * void bus_space_write_multi_N(bus_space_tag_t tag,
354 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
355 1.6 scw * const u_intN_t *addr, size_t count);
356 1.2 scw *
357 1.2 scw * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
358 1.2 scw * provided to bus space described by tag/handle/offset.
359 1.2 scw */
360 1.2 scw
361 1.2 scw #define bus_space_write_multi_1(t, h, o, a, c) do { \
362 1.2 scw (void) t; \
363 1.10 perry __asm volatile (" \
364 1.7 scw movl %0,%%a0 ; \
365 1.7 scw movl %1,%%a1 ; \
366 1.7 scw movl %2,%%d0 ; \
367 1.7 scw 1: movb %%a1@+,%%a0@ ; \
368 1.7 scw subql #1,%%d0 ; \
369 1.2 scw jne 1b" : \
370 1.2 scw : \
371 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
372 1.2 scw "a0","a1","d0"); \
373 1.2 scw } while (0);
374 1.2 scw
375 1.2 scw #define bus_space_write_multi_2(t, h, o, a, c) do { \
376 1.2 scw (void) t; \
377 1.10 perry __asm volatile (" \
378 1.7 scw movl %0,%%a0 ; \
379 1.7 scw movl %1,%%a1 ; \
380 1.7 scw movl %2,%%d0 ; \
381 1.7 scw 1: movw %%a1@+,%%a0@ ; \
382 1.7 scw subql #1,%%d0 ; \
383 1.2 scw jne 1b" : \
384 1.2 scw : \
385 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
386 1.2 scw "a0","a1","d0"); \
387 1.2 scw } while (0);
388 1.2 scw
389 1.2 scw #define bus_space_write_multi_4(t, h, o, a, c) do { \
390 1.2 scw (void) t; \
391 1.10 perry __asm volatile (" \
392 1.7 scw movl %0,%%a0 ; \
393 1.7 scw movl %1,%%a1 ; \
394 1.7 scw movl %2,%%d0 ; \
395 1.7 scw 1: movl a1@+,%%a0@ ; \
396 1.7 scw subql #1,%%d0 ; \
397 1.2 scw jne 1b" : \
398 1.2 scw : \
399 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
400 1.2 scw "a0","a1","d0"); \
401 1.2 scw } while (0);
402 1.2 scw
403 1.2 scw #if 0 /* Cause a link error for bus_space_write_8 */
404 1.2 scw #define bus_space_write_multi_8(t, h, o, a, c) \
405 1.2 scw !!! bus_space_write_multi_8 unimplimented !!!
406 1.2 scw #endif
407 1.2 scw
408 1.2 scw /*
409 1.6 scw * void bus_space_write_region_N(bus_space_tag_t tag,
410 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
411 1.6 scw * const u_intN_t *addr, size_t count);
412 1.2 scw *
413 1.2 scw * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
414 1.2 scw * to bus space described by tag/handle starting at `offset'.
415 1.2 scw */
416 1.2 scw
417 1.2 scw #define bus_space_write_region_1(t, h, o, a, c) do { \
418 1.2 scw (void) t; \
419 1.10 perry __asm volatile (" \
420 1.7 scw movl %0,%%a0 ; \
421 1.7 scw movl %1,%%a1 ; \
422 1.7 scw movl %2,%%d0 ; \
423 1.7 scw 1: movb %%a1@+,%%a0@+ ; \
424 1.7 scw subql #1,%%d0 ; \
425 1.2 scw jne 1b" : \
426 1.2 scw : \
427 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
428 1.2 scw "a0","a1","d0"); \
429 1.2 scw } while (0);
430 1.2 scw
431 1.2 scw #define bus_space_write_region_2(t, h, o, a, c) do { \
432 1.2 scw (void) t; \
433 1.10 perry __asm volatile (" \
434 1.7 scw movl %0,%%a0 ; \
435 1.7 scw movl %1,%%a1 ; \
436 1.7 scw movl %2,%%d0 ; \
437 1.7 scw 1: movw %%a1@+,%%a0@+ ; \
438 1.7 scw subql #1,%%d0 ; \
439 1.2 scw jne 1b" : \
440 1.2 scw : \
441 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
442 1.2 scw "a0","a1","d0"); \
443 1.2 scw } while (0);
444 1.2 scw
445 1.2 scw #define bus_space_write_region_4(t, h, o, a, c) do { \
446 1.2 scw (void) t; \
447 1.10 perry __asm volatile (" \
448 1.7 scw movl %0,%%a0 ; \
449 1.7 scw movl %1,%%a1 ; \
450 1.7 scw movl %2,%%d0 ; \
451 1.7 scw 1: movl %%a1@+,%%a0@+ ; \
452 1.7 scw subql #1,%%d0 ; \
453 1.2 scw jne 1b" : \
454 1.2 scw : \
455 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
456 1.2 scw "a0","a1","d0"); \
457 1.2 scw } while (0);
458 1.2 scw
459 1.2 scw #if 0 /* Cause a link error for bus_space_write_region_8 */
460 1.2 scw #define bus_space_write_region_8 \
461 1.2 scw !!! bus_space_write_region_8 unimplemented !!!
462 1.2 scw #endif
463 1.2 scw
464 1.2 scw /*
465 1.6 scw * void bus_space_set_multi_N(bus_space_tag_t tag,
466 1.2 scw * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
467 1.6 scw * size_t count);
468 1.2 scw *
469 1.2 scw * Write the 1, 2, 4, or 8 byte value `val' to bus space described
470 1.2 scw * by tag/handle/offset `count' times.
471 1.2 scw */
472 1.2 scw
473 1.2 scw #define bus_space_set_multi_1(t, h, o, val, c) do { \
474 1.2 scw (void) t; \
475 1.10 perry __asm volatile (" \
476 1.7 scw movl %0,%%a0 ; \
477 1.7 scw movl %1,%%d1 ; \
478 1.7 scw movl %2,%%d0 ; \
479 1.7 scw 1: movb %%d1,%%a0@ ; \
480 1.7 scw subql #1,%%d0 ; \
481 1.2 scw jne 1b" : \
482 1.2 scw : \
483 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
484 1.2 scw "a0","d0","d1"); \
485 1.2 scw } while (0);
486 1.2 scw
487 1.2 scw #define bus_space_set_multi_2(t, h, o, val, c) do { \
488 1.2 scw (void) t; \
489 1.10 perry __asm volatile (" \
490 1.7 scw movl %0,%%a0 ; \
491 1.7 scw movl %1,%%d1 ; \
492 1.7 scw movl %2,%%d0 ; \
493 1.7 scw 1: movw %%d1,%%a0@ ; \
494 1.7 scw subql #1,%%d0 ; \
495 1.2 scw jne 1b" : \
496 1.2 scw : \
497 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
498 1.2 scw "a0","d0","d1"); \
499 1.2 scw } while (0);
500 1.2 scw
501 1.2 scw #define bus_space_set_multi_4(t, h, o, val, c) do { \
502 1.2 scw (void) t; \
503 1.10 perry __asm volatile (" \
504 1.7 scw movl %0,%%a0 ; \
505 1.7 scw movl %1,%%d1 ; \
506 1.7 scw movl %2,%%d0 ; \
507 1.7 scw 1: movl %%d1,%%a0@ ; \
508 1.7 scw subql #1,%%d0 ; \
509 1.2 scw jne 1b" : \
510 1.2 scw : \
511 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
512 1.2 scw "a0","d0","d1"); \
513 1.2 scw } while (0);
514 1.2 scw
515 1.2 scw #if 0 /* Cause a link error for bus_space_set_multi_8 */
516 1.2 scw #define bus_space_set_multi_8 \
517 1.2 scw !!! bus_space_set_multi_8 unimplemented !!!
518 1.2 scw #endif
519 1.2 scw
520 1.2 scw /*
521 1.6 scw * void bus_space_set_region_N(bus_space_tag_t tag,
522 1.2 scw * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
523 1.6 scw * size_t count);
524 1.2 scw *
525 1.2 scw * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
526 1.2 scw * by tag/handle starting at `offset'.
527 1.2 scw */
528 1.2 scw
529 1.2 scw #define bus_space_set_region_1(t, h, o, val, c) do { \
530 1.2 scw (void) t; \
531 1.10 perry __asm volatile (" \
532 1.7 scw movl %0,%%a0 ; \
533 1.7 scw movl %1,%%d1 ; \
534 1.7 scw movl %2,%%d0 ; \
535 1.7 scw 1: movb %%d1,%%a0@+ ; \
536 1.7 scw subql #1,%%d0 ; \
537 1.2 scw jne 1b" : \
538 1.2 scw : \
539 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
540 1.2 scw "a0","d0","d1"); \
541 1.2 scw } while (0);
542 1.2 scw
543 1.2 scw #define bus_space_set_region_2(t, h, o, val, c) do { \
544 1.2 scw (void) t; \
545 1.10 perry __asm volatile (" \
546 1.7 scw movl %0,%%a0 ; \
547 1.7 scw movl %1,%%d1 ; \
548 1.7 scw movl %2,%%d0 ; \
549 1.7 scw 1: movw %%d1,%%a0@+ ; \
550 1.7 scw subql #1,%%d0 ; \
551 1.2 scw jne 1b" : \
552 1.2 scw : \
553 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
554 1.2 scw "a0","d0","d1"); \
555 1.2 scw } while (0);
556 1.2 scw
557 1.2 scw #define bus_space_set_region_4(t, h, o, val, c) do { \
558 1.2 scw (void) t; \
559 1.10 perry __asm volatile (" \
560 1.7 scw movl %0,%%a0 ; \
561 1.7 scw movl %1,%%d1 ; \
562 1.7 scw movl %2,%%d0 ; \
563 1.7 scw 1: movl d1,%%a0@+ ; \
564 1.7 scw subql #1,%%d0 ; \
565 1.2 scw jne 1b" : \
566 1.2 scw : \
567 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
568 1.2 scw "a0","d0","d1"); \
569 1.2 scw } while (0);
570 1.2 scw
571 1.2 scw #if 0 /* Cause a link error for bus_space_set_region_8 */
572 1.2 scw #define bus_space_set_region_8 \
573 1.2 scw !!! bus_space_set_region_8 unimplemented !!!
574 1.2 scw #endif
575 1.2 scw
576 1.2 scw /*
577 1.6 scw * void bus_space_copy_N(bus_space_tag_t tag,
578 1.2 scw * bus_space_handle_t bsh1, bus_size_t off1,
579 1.2 scw * bus_space_handle_t bsh2, bus_size_t off2,
580 1.6 scw * size_t count);
581 1.2 scw *
582 1.2 scw * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
583 1.2 scw * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
584 1.2 scw */
585 1.2 scw
586 1.2 scw #define __MVME68K_copy_region_N(BYTES) \
587 1.10 perry static inline void __CONCAT(bus_space_copy_region_,BYTES) \
588 1.2 scw __P((bus_space_tag_t, \
589 1.2 scw bus_space_handle_t bsh1, bus_size_t off1, \
590 1.2 scw bus_space_handle_t bsh2, bus_size_t off2, \
591 1.2 scw bus_size_t count)); \
592 1.2 scw \
593 1.10 perry static inline void \
594 1.2 scw __CONCAT(bus_space_copy_region_,BYTES)(t, h1, o1, h2, o2, c) \
595 1.2 scw bus_space_tag_t t; \
596 1.2 scw bus_space_handle_t h1, h2; \
597 1.2 scw bus_size_t o1, o2, c; \
598 1.2 scw { \
599 1.2 scw bus_size_t o; \
600 1.2 scw \
601 1.2 scw if ((h1 + o1) >= (h2 + o2)) { \
602 1.2 scw /* src after dest: copy forward */ \
603 1.2 scw for (o = 0; c != 0; c--, o += BYTES) \
604 1.2 scw __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
605 1.2 scw __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
606 1.2 scw } else { \
607 1.2 scw /* dest after src: copy backwards */ \
608 1.2 scw for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
609 1.2 scw __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
610 1.2 scw __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
611 1.2 scw } \
612 1.2 scw }
613 1.2 scw __MVME68K_copy_region_N(1)
614 1.2 scw __MVME68K_copy_region_N(2)
615 1.2 scw __MVME68K_copy_region_N(4)
616 1.2 scw #if 0 /* Cause a link error for bus_space_copy_8 */
617 1.2 scw #define bus_space_copy_8 \
618 1.2 scw !!! bus_space_copy_8 unimplemented !!!
619 1.2 scw #endif
620 1.2 scw
621 1.2 scw #undef __MVME68K_copy_region_N
622 1.2 scw
623 1.2 scw /*
624 1.2 scw * Bus read/write barrier methods.
625 1.2 scw *
626 1.6 scw * void bus_space_barrier(bus_space_tag_t tag,
627 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
628 1.6 scw * bus_size_t len, int flags);
629 1.2 scw *
630 1.2 scw * Note: the 680x0 does not currently require barriers, but we must
631 1.2 scw * provide the flags to MI code.
632 1.2 scw */
633 1.2 scw #define bus_space_barrier(t, h, o, l, f) \
634 1.2 scw ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
635 1.2 scw #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
636 1.2 scw #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
637 1.3 drochner
638 1.3 drochner #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
639 1.6 scw
640 1.6 scw
641 1.6 scw #ifdef _MVME68K_BUS_SPACE_PRIVATE
642 1.6 scw extern int _bus_space_map(void *, bus_addr_t, bus_size_t,
643 1.6 scw int, bus_space_handle_t *);
644 1.6 scw extern void _bus_space_unmap(void *, bus_space_handle_t, bus_size_t);
645 1.6 scw extern int _bus_space_peek_1(void *, bus_space_handle_t,
646 1.6 scw bus_size_t, u_int8_t *);
647 1.6 scw extern int _bus_space_peek_2(void *, bus_space_handle_t,
648 1.6 scw bus_size_t, u_int16_t *);
649 1.6 scw extern int _bus_space_peek_4(void *, bus_space_handle_t,
650 1.6 scw bus_size_t, u_int32_t *);
651 1.6 scw extern int _bus_space_poke_1(void *, bus_space_handle_t, bus_size_t, u_int8_t);
652 1.6 scw extern int _bus_space_poke_2(void *, bus_space_handle_t, bus_size_t, u_int16_t);
653 1.6 scw extern int _bus_space_poke_4(void *, bus_space_handle_t, bus_size_t, u_int32_t);
654 1.6 scw #endif /* _MVME68K_BUS_SPACE_PRIVATE */
655 1.2 scw
656 1.2 scw #endif /* _MVME68K_BUS_SPACE_H_ */
657