bus_space.h revision 1.13.38.1 1 1.13.38.1 mrg /* $NetBSD: bus_space.h,v 1.13.38.1 2012/02/18 07:32:44 mrg Exp $ */
2 1.2 scw
3 1.2 scw /*-
4 1.2 scw * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
5 1.2 scw * All rights reserved.
6 1.2 scw *
7 1.2 scw * This code is derived from software contributed to The NetBSD Foundation
8 1.2 scw * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.2 scw * NASA Ames Research Center.
10 1.2 scw *
11 1.2 scw * Redistribution and use in source and binary forms, with or without
12 1.2 scw * modification, are permitted provided that the following conditions
13 1.2 scw * are met:
14 1.2 scw * 1. Redistributions of source code must retain the above copyright
15 1.2 scw * notice, this list of conditions and the following disclaimer.
16 1.2 scw * 2. Redistributions in binary form must reproduce the above copyright
17 1.2 scw * notice, this list of conditions and the following disclaimer in the
18 1.2 scw * documentation and/or other materials provided with the distribution.
19 1.2 scw *
20 1.2 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 1.2 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 1.2 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 1.2 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 1.2 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 1.2 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 1.2 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 1.2 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 1.2 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 1.2 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 1.2 scw * POSSIBILITY OF SUCH DAMAGE.
31 1.2 scw */
32 1.2 scw
33 1.2 scw /*
34 1.2 scw * Copyright (C) 1997 Scott Reynolds. All rights reserved.
35 1.2 scw *
36 1.2 scw * Redistribution and use in source and binary forms, with or without
37 1.2 scw * modification, are permitted provided that the following conditions
38 1.2 scw * are met:
39 1.2 scw * 1. Redistributions of source code must retain the above copyright
40 1.2 scw * notice, this list of conditions and the following disclaimer.
41 1.2 scw * 2. Redistributions in binary form must reproduce the above copyright
42 1.2 scw * notice, this list of conditions and the following disclaimer in the
43 1.2 scw * documentation and/or other materials provided with the distribution.
44 1.2 scw * 3. The name of the author may not be used to endorse or promote products
45 1.2 scw * derived from this software without specific prior written permission
46 1.2 scw *
47 1.2 scw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 1.2 scw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 1.2 scw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 1.2 scw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 1.2 scw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 1.2 scw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 1.2 scw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 1.2 scw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 1.2 scw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 1.2 scw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 1.2 scw */
58 1.2 scw
59 1.2 scw /*
60 1.2 scw * Lifted from the Next68k port.
61 1.2 scw * Modified for mvme68k by Steve Woodford.
62 1.2 scw *
63 1.2 scw * TODO: Support for VMEbus...
64 1.2 scw * (Do any existing VME card drivers use bus_space_* ?)
65 1.2 scw */
66 1.2 scw
67 1.2 scw #ifndef _MVME68K_BUS_SPACE_H_
68 1.2 scw #define _MVME68K_BUS_SPACE_H_
69 1.6 scw
70 1.2 scw /*
71 1.2 scw * Addresses (in bus space).
72 1.2 scw */
73 1.2 scw typedef u_long bus_addr_t;
74 1.2 scw typedef u_long bus_size_t;
75 1.2 scw
76 1.2 scw /*
77 1.2 scw * Access methods for bus resources and address space.
78 1.2 scw */
79 1.6 scw struct mvme68k_bus_space_tag;
80 1.6 scw typedef struct mvme68k_bus_space_tag *bus_space_tag_t;
81 1.2 scw typedef u_long bus_space_handle_t;
82 1.2 scw
83 1.6 scw struct mvme68k_bus_space_tag {
84 1.6 scw void *bs_cookie;
85 1.6 scw int (*bs_map)(void *, bus_addr_t, bus_size_t,
86 1.6 scw int, bus_space_handle_t *);
87 1.6 scw void (*bs_unmap)(void *, bus_space_handle_t, bus_size_t);
88 1.6 scw int (*bs_peek_1)(void *, bus_space_handle_t,
89 1.12 tsutsui bus_size_t, uint8_t *);
90 1.6 scw int (*bs_peek_2)(void *, bus_space_handle_t,
91 1.12 tsutsui bus_size_t, uint16_t *);
92 1.6 scw int (*bs_peek_4)(void *, bus_space_handle_t,
93 1.12 tsutsui bus_size_t, uint32_t *);
94 1.6 scw #if 0
95 1.6 scw int (*bs_peek_8)(void *, bus_space_handle_t,
96 1.12 tsutsui bus_size_t, uint64_t *);
97 1.6 scw #endif
98 1.6 scw int (*bs_poke_1)(void *, bus_space_handle_t,
99 1.12 tsutsui bus_size_t, uint8_t);
100 1.6 scw int (*bs_poke_2)(void *, bus_space_handle_t,
101 1.12 tsutsui bus_size_t, uint16_t);
102 1.6 scw int (*bs_poke_4)(void *, bus_space_handle_t,
103 1.12 tsutsui bus_size_t, uint32_t);
104 1.6 scw #if 0
105 1.6 scw int (*bs_poke_8)(void *, bus_space_handle_t,
106 1.12 tsutsui bus_size_t, uint64_t);
107 1.6 scw #endif
108 1.6 scw };
109 1.2 scw
110 1.2 scw /*
111 1.6 scw * int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
112 1.6 scw * bus_size_t size, int flags,
113 1.6 scw * bus_space_handle_t *bshp);
114 1.5 scw *
115 1.5 scw * Map a region of bus space.
116 1.2 scw */
117 1.6 scw #define bus_space_map(tag, offset, size, flags, handlep) \
118 1.6 scw (*((tag)->bs_map))((tag)->bs_cookie, (offset), (size), (flags), (handlep))
119 1.2 scw
120 1.5 scw /*
121 1.5 scw * Possible values for the 'flags' parameter of bus_space_map()
122 1.5 scw */
123 1.2 scw #define BUS_SPACE_MAP_CACHEABLE 0x01
124 1.2 scw #define BUS_SPACE_MAP_LINEAR 0x02
125 1.4 drochner #define BUS_SPACE_MAP_PREFETCHABLE 0x04
126 1.5 scw
127 1.5 scw /*
128 1.6 scw * void bus_space_unmap(bus_space_tag_t t,
129 1.6 scw * bus_space_handle_t bsh, bus_size_t size);
130 1.5 scw *
131 1.5 scw * Unmap a region of bus space.
132 1.5 scw */
133 1.6 scw #define bus_space_unmap(tag, handle, size) \
134 1.6 scw (*((tag)->bs_unmap))((tag)->bs_cookie, (handle), (size))
135 1.5 scw
136 1.6 scw /*
137 1.6 scw * int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t h
138 1.6 scw * bus_addr_t offset, bus_size_t size, bus_space_handle_t *newh);
139 1.6 scw *
140 1.6 scw * Allocate a sub-region of an existing map
141 1.6 scw */
142 1.5 scw #define bus_space_subregion(t, h, o, s, hp) \
143 1.6 scw ((*(hp)=(h)+(o)), 0)
144 1.2 scw
145 1.2 scw /*
146 1.2 scw * Allocation and deallocation operations.
147 1.2 scw */
148 1.2 scw #define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \
149 1.2 scw (-1)
150 1.2 scw
151 1.2 scw #define bus_space_free(t, h, s)
152 1.2 scw
153 1.2 scw /*
154 1.6 scw * int bus_space_peek_N(bus_space_tag_t tag,
155 1.12 tsutsui * bus_space_handle_t bsh, bus_size_t offset, uintN_t *valuep);
156 1.6 scw *
157 1.6 scw * Cautiously read 1, 2, 4 or 8 byte quantity from bus space described
158 1.6 scw * by tag/handle/offset.
159 1.6 scw * If no hardware responds to the read access, the function returns a
160 1.6 scw * non-zero value. Otherwise the value read is placed in `valuep'.
161 1.6 scw */
162 1.6 scw #define bus_space_peek_1(t, h, o, vp) \
163 1.6 scw (*((t)->bs_peek_1))((t)->bs_cookie, (h), (o), (vp))
164 1.6 scw
165 1.6 scw #define bus_space_peek_2(t, h, o, vp) \
166 1.6 scw (*((t)->bs_peek_2))((t)->bs_cookie, (h), (o), (vp))
167 1.6 scw
168 1.6 scw #define bus_space_peek_4(t, h, o, vp) \
169 1.6 scw (*((t)->bs_peek_4))((t)->bs_cookie, (h), (o), (vp))
170 1.6 scw
171 1.6 scw #if 0 /* Cause a link error for bus_space_peek_8 */
172 1.6 scw #define bus_space_peek_8(t, h, o, vp) \
173 1.6 scw (*((t)->bs_peek_8))((t)->bs_cookie, (h), (o), (vp))
174 1.6 scw #endif
175 1.6 scw
176 1.6 scw /*
177 1.6 scw * int bus_space_poke_N(bus_space_tag_t tag,
178 1.12 tsutsui * bus_space_handle_t bsh, bus_size_t offset, uintN_t value);
179 1.6 scw *
180 1.6 scw * Cautiously write 1, 2, 4 or 8 byte quantity to bus space described
181 1.6 scw * by tag/handle/offset.
182 1.6 scw * If no hardware responds to the write access, the function returns a
183 1.6 scw * non-zero value.
184 1.6 scw */
185 1.6 scw #define bus_space_poke_1(t, h, o, v) \
186 1.6 scw (*((t)->bs_poke_1))((t)->bs_cookie, (h), (o), (v))
187 1.6 scw
188 1.6 scw #define bus_space_poke_2(t, h, o, v) \
189 1.6 scw (*((t)->bs_poke_2))((t)->bs_cookie, (h), (o), (v))
190 1.6 scw
191 1.6 scw #define bus_space_poke_4(t, h, o, v) \
192 1.6 scw (*((t)->bs_poke_4))((t)->bs_cookie, (h), (o), (v))
193 1.6 scw
194 1.6 scw #if 0 /* Cause a link error for bus_space_poke_8 */
195 1.6 scw #define bus_space_poke_8(t, h, o, v) \
196 1.6 scw (*((t)->bs_poke_8))((t)->bs_cookie, (h), (o), (v))
197 1.6 scw #endif
198 1.6 scw
199 1.6 scw /*
200 1.12 tsutsui * uintN_t bus_space_read_N(bus_space_tag_t tag,
201 1.6 scw * bus_space_handle_t bsh, bus_size_t offset);
202 1.2 scw *
203 1.2 scw * Read a 1, 2, 4, or 8 byte quantity from bus space
204 1.2 scw * described by tag/handle/offset.
205 1.2 scw */
206 1.8 scw #define bus_space_read_1(t,h,o) \
207 1.12 tsutsui (*((volatile uint8_t *)(intptr_t)((h) + (o))))
208 1.8 scw #define bus_space_read_2(t,h,o) \
209 1.12 tsutsui (*((volatile uint16_t *)(intptr_t)((h) + (o))))
210 1.8 scw #define bus_space_read_4(t,h,o) \
211 1.12 tsutsui (*((volatile uint32_t *)(intptr_t)((h) + (o))))
212 1.2 scw
213 1.2 scw /*
214 1.6 scw * void bus_space_read_multi_N(bus_space_tag_t tag,
215 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
216 1.12 tsutsui * uintN_t *addr, size_t count);
217 1.2 scw *
218 1.2 scw * Read `count' 1, 2, 4, or 8 byte quantities from bus space
219 1.2 scw * described by tag/handle/offset and copy into buffer provided.
220 1.2 scw */
221 1.2 scw
222 1.2 scw #define bus_space_read_multi_1(t, h, o, a, c) do { \
223 1.2 scw (void) t; \
224 1.10 perry __asm volatile (" \
225 1.7 scw movl %0,%%a0 ; \
226 1.7 scw movl %1,%%a1 ; \
227 1.7 scw movl %2,%%d0 ; \
228 1.7 scw 1: movb %%a0@,%%a1@+ ; \
229 1.7 scw subql #1,%%d0 ; \
230 1.2 scw jne 1b" : \
231 1.2 scw : \
232 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
233 1.2 scw "a0","a1","d0"); \
234 1.2 scw } while (0);
235 1.2 scw
236 1.2 scw #define bus_space_read_multi_2(t, h, o, a, c) do { \
237 1.2 scw (void) t; \
238 1.10 perry __asm volatile (" \
239 1.7 scw movl %0,%%a0 ; \
240 1.7 scw movl %1,%%a1 ; \
241 1.7 scw movl %2,%%d0 ; \
242 1.7 scw 1: movw %%a0@,%%a1@+ ; \
243 1.7 scw subql #1,%%d0 ; \
244 1.2 scw jne 1b" : \
245 1.2 scw : \
246 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
247 1.2 scw "a0","a1","d0"); \
248 1.2 scw } while (0);
249 1.2 scw
250 1.2 scw #define bus_space_read_multi_4(t, h, o, a, c) do { \
251 1.2 scw (void) t; \
252 1.10 perry __asm volatile (" \
253 1.7 scw movl %0,%%a0 ; \
254 1.7 scw movl %1,%%a1 ; \
255 1.7 scw movl %2,%%d0 ; \
256 1.7 scw 1: movl %%a0@,%%a1@+ ; \
257 1.7 scw subql #1,%%d0 ; \
258 1.2 scw jne 1b" : \
259 1.2 scw : \
260 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
261 1.2 scw "a0","a1","d0"); \
262 1.2 scw } while (0);
263 1.2 scw
264 1.2 scw #if 0 /* Cause a link error for bus_space_read_multi_8 */
265 1.2 scw #define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!!
266 1.2 scw #endif
267 1.2 scw
268 1.2 scw /*
269 1.6 scw * void bus_space_read_region_N(bus_space_tag_t tag,
270 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
271 1.12 tsutsui * uintN_t *addr, size_t count);
272 1.2 scw *
273 1.2 scw * Read `count' 1, 2, 4, or 8 byte quantities from bus space
274 1.2 scw * described by tag/handle and starting at `offset' and copy into
275 1.2 scw * buffer provided.
276 1.2 scw */
277 1.2 scw
278 1.2 scw #define bus_space_read_region_1(t, h, o, a, c) do { \
279 1.2 scw (void) t; \
280 1.10 perry __asm volatile (" \
281 1.7 scw movl %0,%%a0 ; \
282 1.7 scw movl %1,%%a1 ; \
283 1.7 scw movl %2,%%d0 ; \
284 1.7 scw 1: movb %%a0@+,%%a1@+ ; \
285 1.7 scw subql #1,%%d0 ; \
286 1.2 scw jne 1b" : \
287 1.2 scw : \
288 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
289 1.2 scw "a0","a1","d0"); \
290 1.2 scw } while (0);
291 1.2 scw
292 1.2 scw #define bus_space_read_region_2(t, h, o, a, c) do { \
293 1.2 scw (void) t; \
294 1.10 perry __asm volatile (" \
295 1.7 scw movl %0,%%a0 ; \
296 1.7 scw movl %1,%%a1 ; \
297 1.7 scw movl %2,%%d0 ; \
298 1.7 scw 1: movw %%a0@+,%%a1@+ ; \
299 1.7 scw subql #1,%%d0 ; \
300 1.2 scw jne 1b" : \
301 1.2 scw : \
302 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
303 1.2 scw "a0","a1","d0"); \
304 1.2 scw } while (0);
305 1.2 scw
306 1.2 scw #define bus_space_read_region_4(t, h, o, a, c) do { \
307 1.2 scw (void) t; \
308 1.10 perry __asm volatile (" \
309 1.7 scw movl %0,%%a0 ; \
310 1.7 scw movl %1,%%a1 ; \
311 1.7 scw movl %2,%%d0 ; \
312 1.7 scw 1: movl %%a0@+,%%a1@+ ; \
313 1.7 scw subql #1,%%d0 ; \
314 1.2 scw jne 1b" : \
315 1.2 scw : \
316 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
317 1.2 scw "a0","a1","d0"); \
318 1.2 scw } while (0);
319 1.2 scw
320 1.2 scw #if 0 /* Cause a link error for bus_space_read_region_8 */
321 1.2 scw #define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!!
322 1.2 scw #endif
323 1.2 scw
324 1.2 scw /*
325 1.6 scw * void bus_space_write_N(bus_space_tag_t tag,
326 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
327 1.12 tsutsui * uintN_t value);
328 1.2 scw *
329 1.2 scw * Write the 1, 2, 4, or 8 byte value `value' to bus space
330 1.2 scw * described by tag/handle/offset.
331 1.2 scw */
332 1.8 scw #define bus_space_write_1(t,h,o,v) \
333 1.8 scw do { \
334 1.12 tsutsui *((volatile uint8_t *)(intptr_t)((h) + (o))) = (v); \
335 1.8 scw } while (/*CONSTCOND*/0)
336 1.8 scw #define bus_space_write_2(t,h,o,v) \
337 1.8 scw do { \
338 1.12 tsutsui *((volatile uint16_t *)(intptr_t)((h) + (o))) = (v); \
339 1.8 scw } while (/*CONSTCOND*/0)
340 1.8 scw #define bus_space_write_4(t,h,o,v) \
341 1.8 scw do { \
342 1.12 tsutsui *((volatile uint32_t *)(intptr_t)((h) + (o))) = (v); \
343 1.8 scw } while (/*CONSTCOND*/0)
344 1.2 scw
345 1.2 scw /*
346 1.6 scw * void bus_space_write_multi_N(bus_space_tag_t tag,
347 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
348 1.12 tsutsui * const uintN_t *addr, size_t count);
349 1.2 scw *
350 1.2 scw * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
351 1.2 scw * provided to bus space described by tag/handle/offset.
352 1.2 scw */
353 1.2 scw
354 1.2 scw #define bus_space_write_multi_1(t, h, o, a, c) do { \
355 1.2 scw (void) t; \
356 1.10 perry __asm volatile (" \
357 1.7 scw movl %0,%%a0 ; \
358 1.7 scw movl %1,%%a1 ; \
359 1.7 scw movl %2,%%d0 ; \
360 1.7 scw 1: movb %%a1@+,%%a0@ ; \
361 1.7 scw subql #1,%%d0 ; \
362 1.2 scw jne 1b" : \
363 1.2 scw : \
364 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
365 1.2 scw "a0","a1","d0"); \
366 1.2 scw } while (0);
367 1.2 scw
368 1.2 scw #define bus_space_write_multi_2(t, h, o, a, c) do { \
369 1.2 scw (void) t; \
370 1.10 perry __asm volatile (" \
371 1.7 scw movl %0,%%a0 ; \
372 1.7 scw movl %1,%%a1 ; \
373 1.7 scw movl %2,%%d0 ; \
374 1.7 scw 1: movw %%a1@+,%%a0@ ; \
375 1.7 scw subql #1,%%d0 ; \
376 1.2 scw jne 1b" : \
377 1.2 scw : \
378 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
379 1.2 scw "a0","a1","d0"); \
380 1.2 scw } while (0);
381 1.2 scw
382 1.2 scw #define bus_space_write_multi_4(t, h, o, a, c) do { \
383 1.2 scw (void) t; \
384 1.10 perry __asm volatile (" \
385 1.7 scw movl %0,%%a0 ; \
386 1.7 scw movl %1,%%a1 ; \
387 1.7 scw movl %2,%%d0 ; \
388 1.7 scw 1: movl a1@+,%%a0@ ; \
389 1.7 scw subql #1,%%d0 ; \
390 1.2 scw jne 1b" : \
391 1.2 scw : \
392 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
393 1.2 scw "a0","a1","d0"); \
394 1.2 scw } while (0);
395 1.2 scw
396 1.2 scw #if 0 /* Cause a link error for bus_space_write_8 */
397 1.2 scw #define bus_space_write_multi_8(t, h, o, a, c) \
398 1.2 scw !!! bus_space_write_multi_8 unimplimented !!!
399 1.2 scw #endif
400 1.2 scw
401 1.2 scw /*
402 1.6 scw * void bus_space_write_region_N(bus_space_tag_t tag,
403 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
404 1.12 tsutsui * const uintN_t *addr, size_t count);
405 1.2 scw *
406 1.2 scw * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
407 1.2 scw * to bus space described by tag/handle starting at `offset'.
408 1.2 scw */
409 1.2 scw
410 1.2 scw #define bus_space_write_region_1(t, h, o, a, c) do { \
411 1.2 scw (void) t; \
412 1.10 perry __asm volatile (" \
413 1.7 scw movl %0,%%a0 ; \
414 1.7 scw movl %1,%%a1 ; \
415 1.7 scw movl %2,%%d0 ; \
416 1.7 scw 1: movb %%a1@+,%%a0@+ ; \
417 1.7 scw subql #1,%%d0 ; \
418 1.2 scw jne 1b" : \
419 1.2 scw : \
420 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
421 1.2 scw "a0","a1","d0"); \
422 1.2 scw } while (0);
423 1.2 scw
424 1.2 scw #define bus_space_write_region_2(t, h, o, a, c) do { \
425 1.2 scw (void) t; \
426 1.10 perry __asm volatile (" \
427 1.7 scw movl %0,%%a0 ; \
428 1.7 scw movl %1,%%a1 ; \
429 1.7 scw movl %2,%%d0 ; \
430 1.7 scw 1: movw %%a1@+,%%a0@+ ; \
431 1.7 scw subql #1,%%d0 ; \
432 1.2 scw jne 1b" : \
433 1.2 scw : \
434 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
435 1.2 scw "a0","a1","d0"); \
436 1.2 scw } while (0);
437 1.2 scw
438 1.2 scw #define bus_space_write_region_4(t, h, o, a, c) do { \
439 1.2 scw (void) t; \
440 1.10 perry __asm volatile (" \
441 1.7 scw movl %0,%%a0 ; \
442 1.7 scw movl %1,%%a1 ; \
443 1.7 scw movl %2,%%d0 ; \
444 1.7 scw 1: movl %%a1@+,%%a0@+ ; \
445 1.7 scw subql #1,%%d0 ; \
446 1.2 scw jne 1b" : \
447 1.2 scw : \
448 1.2 scw "r" ((h) + (o)), "g" (a), "g" (c) : \
449 1.2 scw "a0","a1","d0"); \
450 1.2 scw } while (0);
451 1.2 scw
452 1.2 scw #if 0 /* Cause a link error for bus_space_write_region_8 */
453 1.2 scw #define bus_space_write_region_8 \
454 1.2 scw !!! bus_space_write_region_8 unimplemented !!!
455 1.2 scw #endif
456 1.2 scw
457 1.2 scw /*
458 1.6 scw * void bus_space_set_multi_N(bus_space_tag_t tag,
459 1.12 tsutsui * bus_space_handle_t bsh, bus_size_t offset, uintN_t val,
460 1.6 scw * size_t count);
461 1.2 scw *
462 1.2 scw * Write the 1, 2, 4, or 8 byte value `val' to bus space described
463 1.2 scw * by tag/handle/offset `count' times.
464 1.2 scw */
465 1.2 scw
466 1.2 scw #define bus_space_set_multi_1(t, h, o, val, c) do { \
467 1.2 scw (void) t; \
468 1.10 perry __asm volatile (" \
469 1.7 scw movl %0,%%a0 ; \
470 1.7 scw movl %1,%%d1 ; \
471 1.7 scw movl %2,%%d0 ; \
472 1.7 scw 1: movb %%d1,%%a0@ ; \
473 1.7 scw subql #1,%%d0 ; \
474 1.2 scw jne 1b" : \
475 1.2 scw : \
476 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
477 1.2 scw "a0","d0","d1"); \
478 1.2 scw } while (0);
479 1.2 scw
480 1.2 scw #define bus_space_set_multi_2(t, h, o, val, c) do { \
481 1.2 scw (void) t; \
482 1.10 perry __asm volatile (" \
483 1.7 scw movl %0,%%a0 ; \
484 1.7 scw movl %1,%%d1 ; \
485 1.7 scw movl %2,%%d0 ; \
486 1.7 scw 1: movw %%d1,%%a0@ ; \
487 1.7 scw subql #1,%%d0 ; \
488 1.2 scw jne 1b" : \
489 1.2 scw : \
490 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
491 1.2 scw "a0","d0","d1"); \
492 1.2 scw } while (0);
493 1.2 scw
494 1.2 scw #define bus_space_set_multi_4(t, h, o, val, c) do { \
495 1.2 scw (void) t; \
496 1.10 perry __asm volatile (" \
497 1.7 scw movl %0,%%a0 ; \
498 1.7 scw movl %1,%%d1 ; \
499 1.7 scw movl %2,%%d0 ; \
500 1.7 scw 1: movl %%d1,%%a0@ ; \
501 1.7 scw subql #1,%%d0 ; \
502 1.2 scw jne 1b" : \
503 1.2 scw : \
504 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
505 1.2 scw "a0","d0","d1"); \
506 1.2 scw } while (0);
507 1.2 scw
508 1.2 scw #if 0 /* Cause a link error for bus_space_set_multi_8 */
509 1.2 scw #define bus_space_set_multi_8 \
510 1.2 scw !!! bus_space_set_multi_8 unimplemented !!!
511 1.2 scw #endif
512 1.2 scw
513 1.2 scw /*
514 1.6 scw * void bus_space_set_region_N(bus_space_tag_t tag,
515 1.12 tsutsui * bus_space_handle_t bsh, bus_size_t offset, uintN_t val,
516 1.6 scw * size_t count);
517 1.2 scw *
518 1.2 scw * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
519 1.2 scw * by tag/handle starting at `offset'.
520 1.2 scw */
521 1.2 scw
522 1.2 scw #define bus_space_set_region_1(t, h, o, val, c) do { \
523 1.2 scw (void) t; \
524 1.10 perry __asm volatile (" \
525 1.7 scw movl %0,%%a0 ; \
526 1.7 scw movl %1,%%d1 ; \
527 1.7 scw movl %2,%%d0 ; \
528 1.7 scw 1: movb %%d1,%%a0@+ ; \
529 1.7 scw subql #1,%%d0 ; \
530 1.2 scw jne 1b" : \
531 1.2 scw : \
532 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
533 1.2 scw "a0","d0","d1"); \
534 1.2 scw } while (0);
535 1.2 scw
536 1.2 scw #define bus_space_set_region_2(t, h, o, val, c) do { \
537 1.2 scw (void) t; \
538 1.10 perry __asm volatile (" \
539 1.7 scw movl %0,%%a0 ; \
540 1.7 scw movl %1,%%d1 ; \
541 1.7 scw movl %2,%%d0 ; \
542 1.7 scw 1: movw %%d1,%%a0@+ ; \
543 1.7 scw subql #1,%%d0 ; \
544 1.2 scw jne 1b" : \
545 1.2 scw : \
546 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
547 1.2 scw "a0","d0","d1"); \
548 1.2 scw } while (0);
549 1.2 scw
550 1.2 scw #define bus_space_set_region_4(t, h, o, val, c) do { \
551 1.2 scw (void) t; \
552 1.10 perry __asm volatile (" \
553 1.7 scw movl %0,%%a0 ; \
554 1.7 scw movl %1,%%d1 ; \
555 1.7 scw movl %2,%%d0 ; \
556 1.7 scw 1: movl d1,%%a0@+ ; \
557 1.7 scw subql #1,%%d0 ; \
558 1.2 scw jne 1b" : \
559 1.2 scw : \
560 1.2 scw "r" ((h) + (o)), "g" (val), "g" (c) : \
561 1.2 scw "a0","d0","d1"); \
562 1.2 scw } while (0);
563 1.2 scw
564 1.2 scw #if 0 /* Cause a link error for bus_space_set_region_8 */
565 1.2 scw #define bus_space_set_region_8 \
566 1.2 scw !!! bus_space_set_region_8 unimplemented !!!
567 1.2 scw #endif
568 1.2 scw
569 1.2 scw /*
570 1.6 scw * void bus_space_copy_N(bus_space_tag_t tag,
571 1.2 scw * bus_space_handle_t bsh1, bus_size_t off1,
572 1.2 scw * bus_space_handle_t bsh2, bus_size_t off2,
573 1.6 scw * size_t count);
574 1.2 scw *
575 1.2 scw * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
576 1.2 scw * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
577 1.2 scw */
578 1.2 scw
579 1.2 scw #define __MVME68K_copy_region_N(BYTES) \
580 1.11 perry static __inline void __CONCAT(bus_space_copy_region_,BYTES) \
581 1.12 tsutsui (bus_space_tag_t, \
582 1.2 scw bus_space_handle_t bsh1, bus_size_t off1, \
583 1.2 scw bus_space_handle_t bsh2, bus_size_t off2, \
584 1.12 tsutsui bus_size_t count); \
585 1.2 scw \
586 1.11 perry static __inline void \
587 1.13.38.1 mrg __CONCAT(bus_space_copy_region_,BYTES)( \
588 1.13.38.1 mrg bus_space_tag_t t, \
589 1.13.38.1 mrg bus_space_handle_t h1, \
590 1.13.38.1 mrg bus_size_t o1, \
591 1.13.38.1 mrg bus_space_handle_t h2, \
592 1.13.38.1 mrg bus_size_t o2, \
593 1.13.38.1 mrg bus_size_t c) \
594 1.2 scw { \
595 1.2 scw bus_size_t o; \
596 1.2 scw \
597 1.2 scw if ((h1 + o1) >= (h2 + o2)) { \
598 1.2 scw /* src after dest: copy forward */ \
599 1.2 scw for (o = 0; c != 0; c--, o += BYTES) \
600 1.2 scw __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
601 1.2 scw __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
602 1.2 scw } else { \
603 1.2 scw /* dest after src: copy backwards */ \
604 1.2 scw for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
605 1.2 scw __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
606 1.2 scw __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
607 1.2 scw } \
608 1.2 scw }
609 1.2 scw __MVME68K_copy_region_N(1)
610 1.2 scw __MVME68K_copy_region_N(2)
611 1.2 scw __MVME68K_copy_region_N(4)
612 1.2 scw #if 0 /* Cause a link error for bus_space_copy_8 */
613 1.2 scw #define bus_space_copy_8 \
614 1.2 scw !!! bus_space_copy_8 unimplemented !!!
615 1.2 scw #endif
616 1.2 scw
617 1.2 scw #undef __MVME68K_copy_region_N
618 1.2 scw
619 1.2 scw /*
620 1.2 scw * Bus read/write barrier methods.
621 1.2 scw *
622 1.6 scw * void bus_space_barrier(bus_space_tag_t tag,
623 1.2 scw * bus_space_handle_t bsh, bus_size_t offset,
624 1.6 scw * bus_size_t len, int flags);
625 1.2 scw *
626 1.2 scw * Note: the 680x0 does not currently require barriers, but we must
627 1.2 scw * provide the flags to MI code.
628 1.2 scw */
629 1.2 scw #define bus_space_barrier(t, h, o, l, f) \
630 1.2 scw ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
631 1.2 scw #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
632 1.2 scw #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
633 1.3 drochner
634 1.3 drochner #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
635 1.6 scw
636 1.6 scw
637 1.6 scw #ifdef _MVME68K_BUS_SPACE_PRIVATE
638 1.6 scw extern int _bus_space_map(void *, bus_addr_t, bus_size_t,
639 1.6 scw int, bus_space_handle_t *);
640 1.6 scw extern void _bus_space_unmap(void *, bus_space_handle_t, bus_size_t);
641 1.6 scw extern int _bus_space_peek_1(void *, bus_space_handle_t,
642 1.12 tsutsui bus_size_t, uint8_t *);
643 1.6 scw extern int _bus_space_peek_2(void *, bus_space_handle_t,
644 1.12 tsutsui bus_size_t, uint16_t *);
645 1.6 scw extern int _bus_space_peek_4(void *, bus_space_handle_t,
646 1.12 tsutsui bus_size_t, uint32_t *);
647 1.12 tsutsui extern int _bus_space_poke_1(void *, bus_space_handle_t, bus_size_t, uint8_t);
648 1.12 tsutsui extern int _bus_space_poke_2(void *, bus_space_handle_t, bus_size_t, uint16_t);
649 1.12 tsutsui extern int _bus_space_poke_4(void *, bus_space_handle_t, bus_size_t, uint32_t);
650 1.6 scw #endif /* _MVME68K_BUS_SPACE_PRIVATE */
651 1.2 scw
652 1.2 scw #endif /* _MVME68K_BUS_SPACE_H_ */
653