intr.h revision 1.2
1 1.2 scw /* $NetBSD: intr.h,v 1.2 2000/03/18 22:33:05 scw Exp $ */ 2 1.2 scw 3 1.2 scw /*- 4 1.2 scw * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 1.2 scw * All rights reserved. 6 1.2 scw * 7 1.2 scw * This code is derived from software contributed to The NetBSD Foundation 8 1.2 scw * by Jason R. Thorpe and Steve C. Woodford. 9 1.2 scw * 10 1.2 scw * Redistribution and use in source and binary forms, with or without 11 1.2 scw * modification, are permitted provided that the following conditions 12 1.2 scw * are met: 13 1.2 scw * 1. Redistributions of source code must retain the above copyright 14 1.2 scw * notice, this list of conditions and the following disclaimer. 15 1.2 scw * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 scw * notice, this list of conditions and the following disclaimer in the 17 1.2 scw * documentation and/or other materials provided with the distribution. 18 1.2 scw * 3. All advertising materials mentioning features or use of this software 19 1.2 scw * must display the following acknowledgement: 20 1.2 scw * This product includes software developed by the NetBSD 21 1.2 scw * Foundation, Inc. and its contributors. 22 1.2 scw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2 scw * contributors may be used to endorse or promote products derived 24 1.2 scw * from this software without specific prior written permission. 25 1.2 scw * 26 1.2 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2 scw * POSSIBILITY OF SUCH DAMAGE. 37 1.2 scw */ 38 1.2 scw 39 1.2 scw #ifndef _MVME68K_INTR_H 40 1.2 scw #define _MVME68K_INTR_H 41 1.2 scw 42 1.2 scw #include <machine/psl.h> 43 1.2 scw 44 1.2 scw /* 45 1.2 scw * These are identical to the values used by hp300, but are not meaningful 46 1.2 scw * to mvme68k code at this time. 47 1.2 scw */ 48 1.2 scw #define IPL_NONE 0 /* disable only this interrupt */ 49 1.2 scw #define IPL_BIO 1 /* disable block I/O interrupts */ 50 1.2 scw #define IPL_NET 2 /* disable network interrupts */ 51 1.2 scw #define IPL_TTY 3 /* disable terminal interrupts */ 52 1.2 scw #define IPL_TTYNOBUF 4 /* IPL_TTY + higher ISR priority */ 53 1.2 scw #define IPL_CLOCK 5 /* disable clock interrupts */ 54 1.2 scw #define IPL_HIGH 6 /* disable all interrupts */ 55 1.2 scw 56 1.2 scw #ifdef _KERNEL 57 1.2 scw /* spl0 requires checking for software interrupts */ 58 1.2 scw 59 1.2 scw #define spllowersoftclock() spl1() 60 1.2 scw #define splsoftclock() splraise1() 61 1.2 scw #define splsoftnet() splraise1() 62 1.2 scw #define splbio() splraise2() 63 1.2 scw #define splnet() splraise3() 64 1.2 scw #define spltty() splraise3() 65 1.2 scw #define splimp() splraise3() 66 1.2 scw #define splserial() splraise4() 67 1.2 scw #define splclock() splraise5() 68 1.2 scw #define splstatclock() splraise5() 69 1.2 scw #define splvm() splraise5() 70 1.2 scw #define splhigh() spl7() 71 1.2 scw #define splsched() spl7() 72 1.2 scw 73 1.2 scw /* watch out for side effects */ 74 1.2 scw #define splx(s) (s & PSL_IPL ? _spl(s) : spl0()) 75 1.2 scw 76 1.2 scw 77 1.2 scw #define SIR_NET 0x1 78 1.2 scw #define SIR_CLOCK 0x2 79 1.2 scw 80 1.2 scw /* Following is from next68k/intr.h */ 81 1.2 scw #define siron(mask) \ 82 1.2 scw __asm __volatile ( "orb %1,%0" : "=m" (ssir) : "ir" (mask)) 83 1.2 scw #define siroff(mask) \ 84 1.2 scw __asm __volatile ( "andb %1,%0" : "=m" (ssir) : "ir" (~(mask))); 85 1.2 scw 86 1.2 scw #define setsoftint(x) siron(x) 87 1.2 scw #define setsoftnet() siron(SIR_NET) 88 1.2 scw #define setsoftclock() siron(SIR_CLOCK) 89 1.2 scw 90 1.2 scw 91 1.2 scw #ifndef _LOCORE 92 1.2 scw /* 93 1.2 scw * simulated software interrupt register 94 1.2 scw */ 95 1.2 scw extern volatile unsigned char ssir; 96 1.2 scw 97 1.2 scw extern void init_sir __P((void)); 98 1.2 scw extern unsigned long allocate_sir __P((void (*)(void *), void *)); 99 1.2 scw extern int spl0 __P((void)); 100 1.2 scw #endif /* !_LOCORE */ 101 1.2 scw #endif /* _KERNEL */ 102 1.2 scw 103 1.2 scw #endif /* _MVME68K_INTR_H */ 104
Indexes created Tue Sep 23 13:09:54 GMT 2025