intr.h revision 1.5.2.5
1 1.5.2.5 bouyer /* $NetBSD: intr.h,v 1.5.2.5 2001/04/21 17:54:08 bouyer Exp $ */ 2 1.5.2.2 bouyer 3 1.5.2.2 bouyer /*- 4 1.5.2.2 bouyer * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 1.5.2.2 bouyer * All rights reserved. 6 1.5.2.2 bouyer * 7 1.5.2.2 bouyer * This code is derived from software contributed to The NetBSD Foundation 8 1.5.2.2 bouyer * by Jason R. Thorpe and Steve C. Woodford. 9 1.5.2.2 bouyer * 10 1.5.2.2 bouyer * Redistribution and use in source and binary forms, with or without 11 1.5.2.2 bouyer * modification, are permitted provided that the following conditions 12 1.5.2.2 bouyer * are met: 13 1.5.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 14 1.5.2.2 bouyer * notice, this list of conditions and the following disclaimer. 15 1.5.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 16 1.5.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 17 1.5.2.2 bouyer * documentation and/or other materials provided with the distribution. 18 1.5.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 19 1.5.2.2 bouyer * must display the following acknowledgement: 20 1.5.2.2 bouyer * This product includes software developed by the NetBSD 21 1.5.2.2 bouyer * Foundation, Inc. and its contributors. 22 1.5.2.2 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.5.2.2 bouyer * contributors may be used to endorse or promote products derived 24 1.5.2.2 bouyer * from this software without specific prior written permission. 25 1.5.2.2 bouyer * 26 1.5.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.5.2.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.5.2.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.5.2.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.5.2.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.5.2.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.5.2.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.5.2.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.5.2.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.5.2.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.5.2.2 bouyer * POSSIBILITY OF SUCH DAMAGE. 37 1.5.2.2 bouyer */ 38 1.5.2.2 bouyer 39 1.5.2.2 bouyer #ifndef _MVME68K_INTR_H 40 1.5.2.2 bouyer #define _MVME68K_INTR_H 41 1.5.2.2 bouyer 42 1.5.2.2 bouyer #include <sys/device.h> 43 1.5.2.2 bouyer #include <sys/queue.h> 44 1.5.2.2 bouyer #include <machine/psl.h> 45 1.5.2.2 bouyer 46 1.5.2.2 bouyer /* 47 1.5.2.2 bouyer * These are identical to the values used by hp300, but are not meaningful 48 1.5.2.2 bouyer * to mvme68k code at this time. 49 1.5.2.2 bouyer */ 50 1.5.2.2 bouyer #define IPL_NONE 0 /* disable only this interrupt */ 51 1.5.2.2 bouyer #define IPL_BIO 1 /* disable block I/O interrupts */ 52 1.5.2.2 bouyer #define IPL_NET 2 /* disable network interrupts */ 53 1.5.2.2 bouyer #define IPL_TTY 3 /* disable terminal interrupts */ 54 1.5.2.2 bouyer #define IPL_TTYNOBUF 4 /* IPL_TTY + higher ISR priority */ 55 1.5.2.2 bouyer #define IPL_SERIAL 4 /* disable serial interrupts */ 56 1.5.2.2 bouyer #define IPL_CLOCK 5 /* disable clock interrupts */ 57 1.5.2.2 bouyer #define IPL_HIGH 6 /* disable all interrupts */ 58 1.5.2.2 bouyer 59 1.5.2.2 bouyer /* Copied from alpha/include/intr.h */ 60 1.5.2.2 bouyer #define IPL_SOFTSERIAL 0 /* serial software interrupts */ 61 1.5.2.2 bouyer #define IPL_SOFTNET 1 /* network software interrupts */ 62 1.5.2.2 bouyer #define IPL_SOFTCLOCK 2 /* clock software interrupts */ 63 1.5.2.2 bouyer #define IPL_SOFT 3 /* other software interrupts */ 64 1.5.2.2 bouyer #define IPL_NSOFT 4 65 1.5.2.2 bouyer 66 1.5.2.2 bouyer #define IPL_SOFTNAMES { \ 67 1.5.2.2 bouyer "serial", \ 68 1.5.2.2 bouyer "net", \ 69 1.5.2.2 bouyer "clock", \ 70 1.5.2.2 bouyer "misc", \ 71 1.5.2.2 bouyer } 72 1.5.2.2 bouyer 73 1.5.2.2 bouyer #ifdef _KERNEL 74 1.5.2.2 bouyer /* spl0 requires checking for software interrupts */ 75 1.5.2.2 bouyer 76 1.5.2.2 bouyer #define spllowersoftclock() spl1() 77 1.5.2.2 bouyer #define splsoft() splraise1() 78 1.5.2.2 bouyer #define splsoftclock() splsoft() 79 1.5.2.2 bouyer #define splsoftnet() splsoft() 80 1.5.2.2 bouyer #define splsoftserial() splsoft() 81 1.5.2.2 bouyer #define splbio() splraise2() 82 1.5.2.2 bouyer #define splnet() splraise3() 83 1.5.2.2 bouyer #define spltty() splraise3() 84 1.5.2.4 bouyer #define splvm() splraise3() 85 1.5.2.2 bouyer #define splserial() splraise4() 86 1.5.2.2 bouyer #define splclock() splraise5() 87 1.5.2.2 bouyer #define splstatclock() splraise5() 88 1.5.2.2 bouyer #define splhigh() spl7() 89 1.5.2.2 bouyer #define splsched() spl7() 90 1.5.2.2 bouyer #define spllock() spl7() 91 1.5.2.2 bouyer 92 1.5.2.2 bouyer #ifndef _LOCORE 93 1.5.2.3 bouyer 94 1.5.2.2 bouyer /* 95 1.5.2.2 bouyer * Simulated software interrupt register 96 1.5.2.2 bouyer * This is cleared to zero to indicate a soft interrupt is pending 97 1.5.2.2 bouyer * (Yes, it's a bit bizarre, but it allows the use of the m68k's `tas' 98 1.5.2.2 bouyer * instruction so we can avoid masking interrupts elsewhere.) 99 1.5.2.2 bouyer */ 100 1.5.2.2 bouyer extern volatile unsigned char ssir; 101 1.5.2.3 bouyer 102 1.5.2.3 bouyer extern void mvme68k_dossir(void); 103 1.5.2.3 bouyer 104 1.5.2.3 bouyer static __inline void 105 1.5.2.3 bouyer splx(int sr) 106 1.5.2.3 bouyer { 107 1.5.2.3 bouyer 108 1.5.2.3 bouyer if ((u_int16_t)sr < (u_int16_t)(PSL_IPL1|PSL_S) && ssir == 0) 109 1.5.2.3 bouyer mvme68k_dossir(); 110 1.5.2.3 bouyer else 111 1.5.2.3 bouyer __asm __volatile("movw %0,%%sr" : : "di" (sr)); 112 1.5.2.3 bouyer } 113 1.5.2.3 bouyer 114 1.5.2.3 bouyer static __inline int 115 1.5.2.3 bouyer spl0(void) 116 1.5.2.3 bouyer { 117 1.5.2.3 bouyer int sr; 118 1.5.2.3 bouyer 119 1.5.2.3 bouyer __asm __volatile("movw %%sr,%0" : "=d" (sr)); 120 1.5.2.3 bouyer 121 1.5.2.3 bouyer if (ssir == 0) 122 1.5.2.3 bouyer mvme68k_dossir(); 123 1.5.2.3 bouyer else 124 1.5.2.3 bouyer __asm __volatile("movw %0,%%sr" : : "i" (PSL_LOWIPL)); 125 1.5.2.3 bouyer 126 1.5.2.3 bouyer return sr; 127 1.5.2.3 bouyer } 128 1.5.2.3 bouyer 129 1.5.2.3 bouyer 130 1.5.2.2 bouyer #define setsoft(x) x = 0 131 1.5.2.2 bouyer 132 1.5.2.2 bouyer struct mvme68k_soft_intrhand { 133 1.5.2.2 bouyer LIST_ENTRY(mvme68k_soft_intrhand) sih_q; 134 1.5.2.2 bouyer struct mvme68k_soft_intr *sih_intrhead; 135 1.5.2.2 bouyer void (*sih_fn)(void *); 136 1.5.2.2 bouyer void *sih_arg; 137 1.5.2.2 bouyer volatile int sih_pending; 138 1.5.2.2 bouyer }; 139 1.5.2.2 bouyer 140 1.5.2.2 bouyer struct mvme68k_soft_intr { 141 1.5.2.2 bouyer LIST_HEAD(, mvme68k_soft_intrhand) msi_q; 142 1.5.2.2 bouyer struct evcnt msi_evcnt; 143 1.5.2.2 bouyer volatile unsigned char msi_ssir; 144 1.5.2.2 bouyer }; 145 1.5.2.2 bouyer 146 1.5.2.2 bouyer void *softintr_establish(int, void (*)(void *), void *); 147 1.5.2.2 bouyer void softintr_disestablish(void *); 148 1.5.2.2 bouyer void softintr_init(void); 149 1.5.2.2 bouyer void softintr_dispatch(void); 150 1.5.2.2 bouyer 151 1.5.2.2 bouyer #define softintr_schedule(arg) \ 152 1.5.2.2 bouyer do { \ 153 1.5.2.2 bouyer struct mvme68k_soft_intrhand *__sih = (arg); \ 154 1.5.2.2 bouyer __sih->sih_pending = 1; \ 155 1.5.2.2 bouyer setsoft(__sih->sih_intrhead->msi_ssir); \ 156 1.5.2.2 bouyer setsoft(ssir); \ 157 1.5.2.2 bouyer } while (0) 158 1.5.2.2 bouyer 159 1.5.2.2 bouyer /* XXX For legacy software interrupts */ 160 1.5.2.2 bouyer extern struct mvme68k_soft_intrhand *softnet_intrhand; 161 1.5.2.2 bouyer 162 1.5.2.2 bouyer #define setsoftnet() softintr_schedule(softnet_intrhand) 163 1.5.2.2 bouyer 164 1.5.2.2 bouyer #endif /* !_LOCORE */ 165 1.5.2.2 bouyer #endif /* _KERNEL */ 166 1.5.2.2 bouyer 167 1.5.2.2 bouyer #endif /* _MVME68K_INTR_H */ 168
Indexes created Wed Oct 22 00:09:40 GMT 2025