if_lereg.h revision 1.2.4.2
1 1.2.4.2 wiz /* $NetBSD: if_lereg.h,v 1.2.4.2 2001/09/18 18:15:52 wiz Exp $ */ 2 1.2.4.2 wiz 3 1.2.4.2 wiz /*- 4 1.2.4.2 wiz * Copyright (c) 1982, 1992, 1993 5 1.2.4.2 wiz * The Regents of the University of California. All rights reserved. 6 1.2.4.2 wiz * 7 1.2.4.2 wiz * Redistribution and use in source and binary forms, with or without 8 1.2.4.2 wiz * modification, are permitted provided that the following conditions 9 1.2.4.2 wiz * are met: 10 1.2.4.2 wiz * 1. Redistributions of source code must retain the above copyright 11 1.2.4.2 wiz * notice, this list of conditions and the following disclaimer. 12 1.2.4.2 wiz * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.4.2 wiz * notice, this list of conditions and the following disclaimer in the 14 1.2.4.2 wiz * documentation and/or other materials provided with the distribution. 15 1.2.4.2 wiz * 3. All advertising materials mentioning features or use of this software 16 1.2.4.2 wiz * must display the following acknowledgement: 17 1.2.4.2 wiz * This product includes software developed by the University of 18 1.2.4.2 wiz * California, Berkeley and its contributors. 19 1.2.4.2 wiz * 4. Neither the name of the University nor the names of its contributors 20 1.2.4.2 wiz * may be used to endorse or promote products derived from this software 21 1.2.4.2 wiz * without specific prior written permission. 22 1.2.4.2 wiz * 23 1.2.4.2 wiz * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 1.2.4.2 wiz * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 1.2.4.2 wiz * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 1.2.4.2 wiz * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 1.2.4.2 wiz * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 1.2.4.2 wiz * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 1.2.4.2 wiz * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 1.2.4.2 wiz * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 1.2.4.2 wiz * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 1.2.4.2 wiz * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 1.2.4.2 wiz * SUCH DAMAGE. 34 1.2.4.2 wiz * 35 1.2.4.2 wiz * @(#)if_lereg.h 8.2 (Berkeley) 10/30/93 36 1.2.4.2 wiz */ 37 1.2.4.2 wiz 38 1.2.4.2 wiz #define LEMTU 1518 39 1.2.4.2 wiz #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 40 1.2.4.2 wiz #define LERBUF 8 41 1.2.4.2 wiz #define LERBUFLOG2 3 42 1.2.4.2 wiz #define LE_RLEN (LERBUFLOG2 << 13) 43 1.2.4.2 wiz #define LETBUF 1 44 1.2.4.2 wiz #define LETBUFLOG2 0 45 1.2.4.2 wiz #define LE_TLEN (LETBUFLOG2 << 13) 46 1.2.4.2 wiz 47 1.2.4.2 wiz /* Local Area Network Controller for Ethernet (LANCE) registers */ 48 1.2.4.2 wiz struct lereg1 { 49 1.2.4.2 wiz volatile u_short ler1_rdp; /* register data port */ 50 1.2.4.2 wiz volatile u_short ler1_rap; /* register address port */ 51 1.2.4.2 wiz }; 52 1.2.4.2 wiz /* register addresses */ 53 1.2.4.2 wiz #define LE_CSR0 0 /* Control and status register */ 54 1.2.4.2 wiz #define LE_CSR1 1 /* low address of init block */ 55 1.2.4.2 wiz #define LE_CSR2 2 /* high address of init block */ 56 1.2.4.2 wiz #define LE_CSR3 3 /* Bus master and control */ 57 1.2.4.2 wiz 58 1.2.4.2 wiz /* Control and status register 0 (csr0) */ 59 1.2.4.2 wiz #define LE_C0_ERR 0x8000 /* error summary */ 60 1.2.4.2 wiz #define LE_C0_BABL 0x4000 /* transmitter timeout error */ 61 1.2.4.2 wiz #define LE_C0_CERR 0x2000 /* collision */ 62 1.2.4.2 wiz #define LE_C0_MISS 0x1000 /* missed a packet */ 63 1.2.4.2 wiz #define LE_C0_MERR 0x0800 /* memory error */ 64 1.2.4.2 wiz #define LE_C0_RINT 0x0400 /* receiver interrupt */ 65 1.2.4.2 wiz #define LE_C0_TINT 0x0200 /* transmitter interrupt */ 66 1.2.4.2 wiz #define LE_C0_IDON 0x0100 /* initialization done */ 67 1.2.4.2 wiz #define LE_C0_INTR 0x0080 /* interrupt condition */ 68 1.2.4.2 wiz #define LE_C0_INEA 0x0040 /* interrupt enable */ 69 1.2.4.2 wiz #define LE_C0_RXON 0x0020 /* receiver on */ 70 1.2.4.2 wiz #define LE_C0_TXON 0x0010 /* transmitter on */ 71 1.2.4.2 wiz #define LE_C0_TDMD 0x0008 /* transmit demand */ 72 1.2.4.2 wiz #define LE_C0_STOP 0x0004 /* disable all external activity */ 73 1.2.4.2 wiz #define LE_C0_STRT 0x0002 /* enable external activity */ 74 1.2.4.2 wiz #define LE_C0_INIT 0x0001 /* begin initialization */ 75 1.2.4.2 wiz 76 1.2.4.2 wiz #define LE_C0_BITS \ 77 1.2.4.2 wiz "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\ 78 1.2.4.2 wiz \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT" 79 1.2.4.2 wiz 80 1.2.4.2 wiz /* Control and status register 3 (csr3) */ 81 1.2.4.2 wiz #define LE_C3_BSWP 0x4 /* byte swap */ 82 1.2.4.2 wiz #define LE_C3_ACON 0x2 /* ALE control, eh? */ 83 1.2.4.2 wiz #define LE_C3_BCON 0x1 /* byte control */ 84 1.2.4.2 wiz /* 85 1.2.4.2 wiz * Current size is 13,758 bytes with 8 x 1518 receive buffers and 86 1.2.4.2 wiz * 1 x 1518 transmit buffer. 87 1.2.4.2 wiz */ 88 1.2.4.2 wiz struct lereg2 { 89 1.2.4.2 wiz /* initialization block */ 90 1.2.4.2 wiz volatile u_short ler2_mode; /* mode */ 91 1.2.4.2 wiz volatile u_char ler2_padr[6]; /* physical address */ 92 1.2.4.2 wiz #ifdef new_code 93 1.2.4.2 wiz volatile u_short ler2_ladrf[4]; /* logical address filter */ 94 1.2.4.2 wiz #else 95 1.2.4.2 wiz volatile u_long ler2_ladrf0; /* logical address filter */ 96 1.2.4.2 wiz volatile u_long ler2_ladrf1; /* logical address filter */ 97 1.2.4.2 wiz #endif 98 1.2.4.2 wiz volatile u_short ler2_rdra; /* receive descriptor addr */ 99 1.2.4.2 wiz volatile u_short ler2_rlen; /* rda high and ring size */ 100 1.2.4.2 wiz volatile u_short ler2_tdra; /* transmit descriptor addr */ 101 1.2.4.2 wiz volatile u_short ler2_tlen; /* tda high and ring size */ 102 1.2.4.2 wiz /* receive message descriptors. bits/hadr are byte order dependent. */ 103 1.2.4.2 wiz struct lermd { 104 1.2.4.2 wiz volatile u_short rmd0; /* low address of packet */ 105 1.2.4.2 wiz volatile u_char rmd1_bits; /* descriptor bits */ 106 1.2.4.2 wiz volatile u_char rmd1_hadr; /* high address of packet */ 107 1.2.4.2 wiz volatile short rmd2; /* buffer byte count */ 108 1.2.4.2 wiz volatile u_short rmd3; /* message byte count */ 109 1.2.4.2 wiz } ler2_rmd[LERBUF]; 110 1.2.4.2 wiz /* transmit message descriptors */ 111 1.2.4.2 wiz struct letmd { 112 1.2.4.2 wiz volatile u_short tmd0; /* low address of packet */ 113 1.2.4.2 wiz volatile u_char tmd1_bits; /* descriptor bits */ 114 1.2.4.2 wiz volatile u_char tmd1_hadr; /* high address of packet */ 115 1.2.4.2 wiz volatile short tmd2; /* buffer byte count */ 116 1.2.4.2 wiz volatile u_short tmd3; /* transmit error bits */ 117 1.2.4.2 wiz } ler2_tmd[LETBUF]; 118 1.2.4.2 wiz volatile char ler2_rbuf[LERBUF][LEMTU]; 119 1.2.4.2 wiz volatile char ler2_tbuf[LETBUF][LEMTU]; 120 1.2.4.2 wiz }; 121 1.2.4.2 wiz /* Initialzation block (mode) */ 122 1.2.4.2 wiz #define LE_MODE_PROM 0x8000 /* promiscuous mode */ 123 1.2.4.2 wiz /* 0x7f80 reserved, must be zero */ 124 1.2.4.2 wiz #define LE_MODE_INTL 0x0040 /* internal loopback */ 125 1.2.4.2 wiz #define LE_MODE_DRTY 0x0020 /* disable retry */ 126 1.2.4.2 wiz #define LE_MODE_COLL 0x0010 /* force a collision */ 127 1.2.4.2 wiz #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */ 128 1.2.4.2 wiz #define LE_MODE_LOOP 0x0004 /* loopback mode */ 129 1.2.4.2 wiz #define LE_MODE_DTX 0x0002 /* disable transmitter */ 130 1.2.4.2 wiz #define LE_MODE_DRX 0x0001 /* disable receiver */ 131 1.2.4.2 wiz #define LE_MODE_NORMAL 0 /* none of the above */ 132 1.2.4.2 wiz 133 1.2.4.2 wiz 134 1.2.4.2 wiz /* Receive message descriptor 1 (rmd1_bits) */ 135 1.2.4.2 wiz #define LE_R1_OWN 0x80 /* LANCE owns the packet */ 136 1.2.4.2 wiz #define LE_R1_ERR 0x40 /* error summary */ 137 1.2.4.2 wiz #define LE_R1_FRAM 0x20 /* framing error */ 138 1.2.4.2 wiz #define LE_R1_OFLO 0x10 /* overflow error */ 139 1.2.4.2 wiz #define LE_R1_CRC 0x08 /* CRC error */ 140 1.2.4.2 wiz #define LE_R1_BUFF 0x04 /* buffer error */ 141 1.2.4.2 wiz #define LE_R1_STP 0x02 /* start of packet */ 142 1.2.4.2 wiz #define LE_R1_ENP 0x01 /* end of packet */ 143 1.2.4.2 wiz 144 1.2.4.2 wiz #define LE_R1_BITS \ 145 1.2.4.2 wiz "\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP" 146 1.2.4.2 wiz 147 1.2.4.2 wiz /* Transmit message descriptor 1 (tmd1_bits) */ 148 1.2.4.2 wiz #define LE_T1_OWN 0x80 /* LANCE owns the packet */ 149 1.2.4.2 wiz #define LE_T1_ERR 0x40 /* error summary */ 150 1.2.4.2 wiz #define LE_T1_MORE 0x10 /* multiple collisions */ 151 1.2.4.2 wiz #define LE_T1_ONE 0x08 /* single collision */ 152 1.2.4.2 wiz #define LE_T1_DEF 0x04 /* defferred transmit */ 153 1.2.4.2 wiz #define LE_T1_STP 0x02 /* start of packet */ 154 1.2.4.2 wiz #define LE_T1_ENP 0x01 /* end of packet */ 155 1.2.4.2 wiz 156 1.2.4.2 wiz #define LE_T1_BITS \ 157 1.2.4.2 wiz "\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP" 158 1.2.4.2 wiz 159 1.2.4.2 wiz /* Transmit message descriptor 3 (tmd3) */ 160 1.2.4.2 wiz #define LE_T3_BUFF 0x8000 /* buffer error */ 161 1.2.4.2 wiz #define LE_T3_UFLO 0x4000 /* underflow error */ 162 1.2.4.2 wiz #define LE_T3_LCOL 0x1000 /* late collision */ 163 1.2.4.2 wiz #define LE_T3_LCAR 0x0800 /* loss of carrier */ 164 1.2.4.2 wiz #define LE_T3_RTRY 0x0400 /* retry error */ 165 1.2.4.2 wiz #define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */ 166 1.2.4.2 wiz 167 1.2.4.2 wiz #define LE_XMD2_ONES 0xf000 168 1.2.4.2 wiz 169 1.2.4.2 wiz #define LE_T3_BITS \ 170 1.2.4.2 wiz "\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY" 171 1.2.4.2 wiz 172 1.2.4.2 wiz 173 1.2.4.2 wiz #define LE_ADDR_LOW_MASK (0xffff) 174
Indexes created Tue Oct 21 12:09:54 GMT 2025