1 1.15 matt /* $NetBSD: intr.h,v 1.15 2011/06/17 23:36:17 matt Exp $ */ 2 1.1 scw 3 1.1 scw /*- 4 1.2 scw * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 1.1 scw * All rights reserved. 6 1.1 scw * 7 1.1 scw * This code is derived from software contributed to The NetBSD Foundation 8 1.1 scw * by Charles M. Hannum. 9 1.1 scw * 10 1.1 scw * Redistribution and use in source and binary forms, with or without 11 1.1 scw * modification, are permitted provided that the following conditions 12 1.1 scw * are met: 13 1.1 scw * 1. Redistributions of source code must retain the above copyright 14 1.1 scw * notice, this list of conditions and the following disclaimer. 15 1.1 scw * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 scw * notice, this list of conditions and the following disclaimer in the 17 1.1 scw * documentation and/or other materials provided with the distribution. 18 1.1 scw * 19 1.1 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 scw * POSSIBILITY OF SUCH DAMAGE. 30 1.1 scw */ 31 1.1 scw 32 1.1 scw #ifndef _MVMEPPC_INTR_H_ 33 1.1 scw #define _MVMEPPC_INTR_H_ 34 1.1 scw 35 1.1 scw #ifndef _LOCORE 36 1.1 scw 37 1.2 scw void enable_intr(void); 38 1.2 scw void disable_intr(void); 39 1.2 scw 40 1.2 scw extern vaddr_t mvmeppc_intr_reg; 41 1.1 scw 42 1.15 matt #define ICU_LEN 32 43 1.15 matt #define IRQ_SLAVE 2 44 1.15 matt #define LEGAL_HWIRQ_P(x) ((u_int)(x) < ICU_LEN && (x) != IRQ_SLAVE) 45 1.1 scw 46 1.1 scw #define MVMEPPC_INTR_REG 0xbffff000 47 1.15 matt #define INTR_VECTOR_REG 0xff0 48 1.1 scw 49 1.1 scw #endif /* !_LOCORE */ 50 1.1 scw 51 1.15 matt #include <powerpc/intr.h> 52 1.15 matt 53 1.1 scw #endif /* !_MVMEPPC_INTR_H_ */ 54