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intr.h revision 1.2.10.1
      1  1.2.10.1  gehenna /*	$NetBSD: intr.h,v 1.2.10.1 2002/07/16 12:52:47 gehenna Exp $	*/
      2       1.1      scw 
      3       1.1      scw /*-
      4       1.2      scw  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5       1.1      scw  * All rights reserved.
      6       1.1      scw  *
      7       1.1      scw  * This code is derived from software contributed to The NetBSD Foundation
      8       1.1      scw  * by Charles M. Hannum.
      9       1.1      scw  *
     10       1.1      scw  * Redistribution and use in source and binary forms, with or without
     11       1.1      scw  * modification, are permitted provided that the following conditions
     12       1.1      scw  * are met:
     13       1.1      scw  * 1. Redistributions of source code must retain the above copyright
     14       1.1      scw  *    notice, this list of conditions and the following disclaimer.
     15       1.1      scw  * 2. Redistributions in binary form must reproduce the above copyright
     16       1.1      scw  *    notice, this list of conditions and the following disclaimer in the
     17       1.1      scw  *    documentation and/or other materials provided with the distribution.
     18       1.1      scw  * 3. All advertising materials mentioning features or use of this software
     19       1.1      scw  *    must display the following acknowledgement:
     20       1.1      scw  *        This product includes software developed by the NetBSD
     21       1.1      scw  *        Foundation, Inc. and its contributors.
     22       1.1      scw  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23       1.1      scw  *    contributors may be used to endorse or promote products derived
     24       1.1      scw  *    from this software without specific prior written permission.
     25       1.1      scw  *
     26       1.1      scw  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27       1.1      scw  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28       1.1      scw  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29       1.1      scw  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30       1.1      scw  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31       1.1      scw  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32       1.1      scw  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33       1.1      scw  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34       1.1      scw  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35       1.1      scw  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36       1.1      scw  * POSSIBILITY OF SUCH DAMAGE.
     37       1.1      scw  */
     38       1.1      scw 
     39       1.1      scw #ifndef _MVMEPPC_INTR_H_
     40       1.1      scw #define _MVMEPPC_INTR_H_
     41       1.1      scw 
     42       1.1      scw /* Interrupt priority `levels'. */
     43       1.1      scw #define	IPL_NONE	9	/* nothing */
     44       1.1      scw #define	IPL_SOFTCLOCK	8	/* software clock interrupt */
     45       1.1      scw #define	IPL_SOFTNET	7	/* software network interrupt */
     46       1.1      scw #define	IPL_BIO		6	/* block I/O */
     47       1.1      scw #define	IPL_NET		5	/* network */
     48       1.1      scw #define	IPL_SOFTSERIAL	4	/* software serial interrupt */
     49       1.1      scw #define	IPL_TTY		3	/* terminal */
     50       1.1      scw #define	IPL_IMP		3	/* memory allocation */
     51       1.1      scw #define	IPL_AUDIO	2	/* audio */
     52       1.1      scw #define	IPL_CLOCK	1	/* clock */
     53       1.1      scw #define	IPL_HIGH	1	/* everything */
     54       1.1      scw #define	IPL_SERIAL	0	/* serial */
     55       1.1      scw #define	NIPL		10
     56       1.1      scw 
     57       1.1      scw /* Interrupt sharing types. */
     58       1.1      scw #define	IST_NONE	0	/* none */
     59       1.1      scw #define	IST_PULSE	1	/* pulsed */
     60       1.1      scw #define	IST_EDGE	2	/* edge-triggered */
     61       1.1      scw #define	IST_LEVEL	3	/* level-triggered */
     62       1.1      scw 
     63       1.1      scw #ifndef _LOCORE
     64       1.1      scw 
     65       1.1      scw /*
     66       1.1      scw  * Interrupt handler chains.  intr_establish() inserts a handler into
     67       1.1      scw  * the list.  The handler is called with its (single) argument.
     68       1.1      scw  */
     69       1.1      scw struct intrhand {
     70       1.1      scw 	int	(*ih_fun)(void *);
     71       1.1      scw 	void	*ih_arg;
     72       1.1      scw 	u_long	ih_count;
     73       1.1      scw 	struct	intrhand *ih_next;
     74       1.1      scw 	int	ih_level;
     75       1.1      scw 	int	ih_irq;
     76       1.1      scw };
     77       1.1      scw 
     78       1.2      scw void do_pending_int(void);
     79       1.2      scw 
     80       1.2      scw void ext_intr(void);
     81       1.2      scw void ext_intr_ivr(void);
     82       1.2      scw 
     83       1.2      scw void enable_intr(void);
     84       1.2      scw void disable_intr(void);
     85       1.2      scw 
     86       1.2      scw void *intr_establish(int, int, int, int (*)(void *), void *);
     87       1.2      scw void intr_disestablish(void *);
     88       1.1      scw 
     89  1.2.10.1  gehenna void softnet(int);
     90       1.1      scw void softserial(void);
     91       1.1      scw int isa_intr(void);
     92       1.1      scw void isa_intr_mask(int);
     93       1.1      scw void isa_intr_clr(int);
     94       1.1      scw void isa_setirqstat(int, int, int);
     95       1.1      scw 
     96       1.2      scw static __inline int splraise(int);
     97       1.2      scw static __inline void spllower(int);
     98       1.2      scw static __inline void set_sint(int);
     99       1.1      scw 
    100       1.1      scw extern volatile int cpl, ipending, astpending, tickspending;
    101       1.2      scw extern int imen;
    102       1.1      scw extern int imask[];
    103       1.1      scw extern long intrcnt[];
    104       1.2      scw extern unsigned intrcnt2[];
    105       1.2      scw extern struct intrhand *intrhand[];
    106       1.1      scw extern int intrtype[];
    107       1.2      scw extern vaddr_t mvmeppc_intr_reg;
    108       1.1      scw 
    109       1.1      scw /*
    110       1.2      scw  *  Reorder protection in the following inline functions is
    111       1.2      scw  * achieved with the "eieio" instruction which the assembler
    112       1.2      scw  * seems to detect and then doesn't move instructions past....
    113       1.1      scw  */
    114       1.1      scw static __inline int
    115       1.2      scw splraise(int newcpl)
    116       1.1      scw {
    117       1.1      scw 	int oldcpl;
    118       1.1      scw 
    119       1.1      scw 	__asm__ volatile("sync; eieio\n");	/* don't reorder.... */
    120       1.1      scw 	oldcpl = cpl;
    121       1.1      scw 	cpl = oldcpl | newcpl;
    122       1.1      scw 	__asm__ volatile("sync; eieio\n");	/* reorder protect */
    123       1.1      scw 	return(oldcpl);
    124       1.1      scw }
    125       1.1      scw 
    126       1.1      scw static __inline void
    127       1.2      scw spllower(int newcpl)
    128       1.1      scw {
    129       1.1      scw 
    130       1.1      scw 	__asm__ volatile("sync; eieio\n");	/* reorder protect */
    131       1.1      scw 	cpl = newcpl;
    132       1.1      scw 	if(ipending & ~newcpl)
    133       1.1      scw 		do_pending_int();
    134       1.1      scw 	__asm__ volatile("sync; eieio\n");	/* reorder protect */
    135       1.1      scw }
    136       1.1      scw 
    137       1.1      scw /* Following code should be implemented with lwarx/stwcx to avoid
    138       1.1      scw  * the disable/enable. i need to read the manual once more.... */
    139       1.1      scw static __inline void
    140       1.2      scw set_sint(int pending)
    141       1.1      scw {
    142       1.1      scw 	int	msrsave;
    143       1.1      scw 
    144       1.1      scw 	__asm__ ("mfmsr %0" : "=r"(msrsave));
    145       1.1      scw 	__asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE));
    146       1.1      scw 	ipending |= pending;
    147       1.1      scw 	__asm__ volatile ("mtmsr %0" :: "r"(msrsave));
    148       1.1      scw }
    149       1.1      scw 
    150       1.1      scw #define	ICU_LEN		32
    151       1.1      scw #define	IRQ_SLAVE	2
    152       1.1      scw #define	LEGAL_IRQ(x)	((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE)
    153       1.1      scw 
    154       1.1      scw #define	MVMEPPC_INTR_REG	0xbffff000
    155       1.1      scw #define	INTR_VECTOR_REG	0xff0
    156       1.1      scw 
    157       1.1      scw #define	SINT_CLOCK	0x20000000
    158       1.1      scw #define	SINT_NET	0x40000000
    159       1.1      scw #define	SINT_SERIAL	0x80000000
    160       1.1      scw #define	SPL_CLOCK	0x00000001
    161       1.1      scw #define	SINT_MASK	(SINT_CLOCK|SINT_NET|SINT_SERIAL)
    162       1.1      scw 
    163       1.1      scw #define	CNT_SINT_NET	29
    164       1.1      scw #define	CNT_SINT_CLOCK	30
    165       1.1      scw #define	CNT_SINT_SERIAL	31
    166       1.1      scw #define	CNT_CLOCK	0
    167       1.1      scw 
    168       1.1      scw #define splbio()	splraise(imask[IPL_BIO])
    169       1.1      scw #define splnet()	splraise(imask[IPL_NET])
    170       1.1      scw #define spltty()	splraise(imask[IPL_TTY])
    171       1.1      scw #define splclock()	splraise(imask[IPL_CLOCK])
    172       1.1      scw #define splvm()		splraise(imask[IPL_IMP])
    173       1.2      scw #define splaudio()	splraise(imask[IPL_AUDIO])
    174       1.1      scw #define	splserial()	splraise(imask[IPL_SERIAL])
    175       1.1      scw #define splstatclock()	splclock()
    176       1.1      scw #define	spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
    177       1.1      scw #define	splsoftclock()	splraise(imask[IPL_SOFTCLOCK])
    178       1.1      scw #define	splsoftnet()	splraise(imask[IPL_SOFTNET])
    179       1.1      scw #define	splsoftserial()	splraise(imask[IPL_SOFTSERIAL])
    180       1.1      scw 
    181       1.2      scw #define spllpt()	spltty()
    182       1.2      scw 
    183       1.1      scw #define	setsoftclock()	set_sint(SINT_CLOCK);
    184       1.1      scw #define	setsoftnet()	set_sint(SINT_NET);
    185       1.1      scw #define	setsoftserial()	set_sint(SINT_SERIAL);
    186       1.2      scw 
    187       1.2      scw #define	splhigh()	splraise(imask[IPL_HIGH])
    188       1.2      scw #define	splsched()	splhigh()
    189       1.2      scw #define	spllock()	splhigh()
    190       1.2      scw #define	splx(x)		spllower(x)
    191       1.2      scw #define	spl0()		spllower(0)
    192       1.1      scw 
    193       1.1      scw #endif /* !_LOCORE */
    194       1.1      scw 
    195       1.1      scw #endif /* !_MVMEPPC_INTR_H_ */
    196