intr.h revision 1.2.2.3
1 1.2.2.3 nathanw /* $NetBSD: intr.h,v 1.2.2.3 2002/04/01 07:41:28 nathanw Exp $ */ 2 1.2.2.2 nathanw 3 1.2.2.2 nathanw /*- 4 1.2.2.3 nathanw * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 1.2.2.2 nathanw * All rights reserved. 6 1.2.2.2 nathanw * 7 1.2.2.2 nathanw * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 nathanw * by Charles M. Hannum. 9 1.2.2.2 nathanw * 10 1.2.2.2 nathanw * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 nathanw * modification, are permitted provided that the following conditions 12 1.2.2.2 nathanw * are met: 13 1.2.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 nathanw * documentation and/or other materials provided with the distribution. 18 1.2.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 19 1.2.2.2 nathanw * must display the following acknowledgement: 20 1.2.2.2 nathanw * This product includes software developed by the NetBSD 21 1.2.2.2 nathanw * Foundation, Inc. and its contributors. 22 1.2.2.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2.2.2 nathanw * contributors may be used to endorse or promote products derived 24 1.2.2.2 nathanw * from this software without specific prior written permission. 25 1.2.2.2 nathanw * 26 1.2.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2.2.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 37 1.2.2.2 nathanw */ 38 1.2.2.2 nathanw 39 1.2.2.2 nathanw #ifndef _MVMEPPC_INTR_H_ 40 1.2.2.2 nathanw #define _MVMEPPC_INTR_H_ 41 1.2.2.2 nathanw 42 1.2.2.2 nathanw /* Interrupt priority `levels'. */ 43 1.2.2.2 nathanw #define IPL_NONE 9 /* nothing */ 44 1.2.2.2 nathanw #define IPL_SOFTCLOCK 8 /* software clock interrupt */ 45 1.2.2.2 nathanw #define IPL_SOFTNET 7 /* software network interrupt */ 46 1.2.2.2 nathanw #define IPL_BIO 6 /* block I/O */ 47 1.2.2.2 nathanw #define IPL_NET 5 /* network */ 48 1.2.2.2 nathanw #define IPL_SOFTSERIAL 4 /* software serial interrupt */ 49 1.2.2.2 nathanw #define IPL_TTY 3 /* terminal */ 50 1.2.2.2 nathanw #define IPL_IMP 3 /* memory allocation */ 51 1.2.2.2 nathanw #define IPL_AUDIO 2 /* audio */ 52 1.2.2.2 nathanw #define IPL_CLOCK 1 /* clock */ 53 1.2.2.2 nathanw #define IPL_HIGH 1 /* everything */ 54 1.2.2.2 nathanw #define IPL_SERIAL 0 /* serial */ 55 1.2.2.2 nathanw #define NIPL 10 56 1.2.2.2 nathanw 57 1.2.2.2 nathanw /* Interrupt sharing types. */ 58 1.2.2.2 nathanw #define IST_NONE 0 /* none */ 59 1.2.2.2 nathanw #define IST_PULSE 1 /* pulsed */ 60 1.2.2.2 nathanw #define IST_EDGE 2 /* edge-triggered */ 61 1.2.2.2 nathanw #define IST_LEVEL 3 /* level-triggered */ 62 1.2.2.2 nathanw 63 1.2.2.2 nathanw #ifndef _LOCORE 64 1.2.2.2 nathanw 65 1.2.2.2 nathanw /* 66 1.2.2.2 nathanw * Interrupt handler chains. intr_establish() inserts a handler into 67 1.2.2.2 nathanw * the list. The handler is called with its (single) argument. 68 1.2.2.2 nathanw */ 69 1.2.2.2 nathanw struct intrhand { 70 1.2.2.2 nathanw int (*ih_fun)(void *); 71 1.2.2.2 nathanw void *ih_arg; 72 1.2.2.2 nathanw u_long ih_count; 73 1.2.2.2 nathanw struct intrhand *ih_next; 74 1.2.2.2 nathanw int ih_level; 75 1.2.2.2 nathanw int ih_irq; 76 1.2.2.2 nathanw }; 77 1.2.2.2 nathanw 78 1.2.2.3 nathanw void setsoftclock(void); 79 1.2.2.3 nathanw void clearsoftclock(void); 80 1.2.2.3 nathanw int splsoftclock(void); 81 1.2.2.3 nathanw void setsoftnet(void); 82 1.2.2.3 nathanw void clearsoftnet(void); 83 1.2.2.3 nathanw int splsoftnet(void); 84 1.2.2.3 nathanw 85 1.2.2.3 nathanw void do_pending_int(void); 86 1.2.2.3 nathanw 87 1.2.2.3 nathanw void ext_intr(void); 88 1.2.2.3 nathanw void ext_intr_ivr(void); 89 1.2.2.3 nathanw 90 1.2.2.3 nathanw void enable_intr(void); 91 1.2.2.3 nathanw void disable_intr(void); 92 1.2.2.3 nathanw 93 1.2.2.3 nathanw void *intr_establish(int, int, int, int (*)(void *), void *); 94 1.2.2.3 nathanw void intr_disestablish(void *); 95 1.2.2.2 nathanw 96 1.2.2.3 nathanw void softnet(void); 97 1.2.2.2 nathanw void softserial(void); 98 1.2.2.2 nathanw int isa_intr(void); 99 1.2.2.2 nathanw void isa_intr_mask(int); 100 1.2.2.2 nathanw void isa_intr_clr(int); 101 1.2.2.2 nathanw void isa_setirqstat(int, int, int); 102 1.2.2.2 nathanw 103 1.2.2.3 nathanw static __inline int splraise(int); 104 1.2.2.3 nathanw static __inline void spllower(int); 105 1.2.2.3 nathanw static __inline void set_sint(int); 106 1.2.2.2 nathanw 107 1.2.2.2 nathanw extern volatile int cpl, ipending, astpending, tickspending; 108 1.2.2.3 nathanw extern int imen; 109 1.2.2.2 nathanw extern int imask[]; 110 1.2.2.2 nathanw extern long intrcnt[]; 111 1.2.2.3 nathanw extern unsigned intrcnt2[]; 112 1.2.2.2 nathanw extern struct intrhand *intrhand[]; 113 1.2.2.3 nathanw extern int intrtype[]; 114 1.2.2.3 nathanw extern vaddr_t mvmeppc_intr_reg; 115 1.2.2.2 nathanw 116 1.2.2.2 nathanw /* 117 1.2.2.3 nathanw * Reorder protection in the following inline functions is 118 1.2.2.3 nathanw * achieved with the "eieio" instruction which the assembler 119 1.2.2.3 nathanw * seems to detect and then doesn't move instructions past.... 120 1.2.2.2 nathanw */ 121 1.2.2.2 nathanw static __inline int 122 1.2.2.3 nathanw splraise(int newcpl) 123 1.2.2.2 nathanw { 124 1.2.2.2 nathanw int oldcpl; 125 1.2.2.2 nathanw 126 1.2.2.2 nathanw __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 127 1.2.2.2 nathanw oldcpl = cpl; 128 1.2.2.2 nathanw cpl = oldcpl | newcpl; 129 1.2.2.2 nathanw __asm__ volatile("sync; eieio\n"); /* reorder protect */ 130 1.2.2.2 nathanw return(oldcpl); 131 1.2.2.2 nathanw } 132 1.2.2.2 nathanw 133 1.2.2.2 nathanw static __inline void 134 1.2.2.3 nathanw spllower(int newcpl) 135 1.2.2.2 nathanw { 136 1.2.2.2 nathanw 137 1.2.2.2 nathanw __asm__ volatile("sync; eieio\n"); /* reorder protect */ 138 1.2.2.2 nathanw cpl = newcpl; 139 1.2.2.2 nathanw if(ipending & ~newcpl) 140 1.2.2.2 nathanw do_pending_int(); 141 1.2.2.2 nathanw __asm__ volatile("sync; eieio\n"); /* reorder protect */ 142 1.2.2.2 nathanw } 143 1.2.2.2 nathanw 144 1.2.2.2 nathanw /* Following code should be implemented with lwarx/stwcx to avoid 145 1.2.2.2 nathanw * the disable/enable. i need to read the manual once more.... */ 146 1.2.2.2 nathanw static __inline void 147 1.2.2.3 nathanw set_sint(int pending) 148 1.2.2.2 nathanw { 149 1.2.2.2 nathanw int msrsave; 150 1.2.2.2 nathanw 151 1.2.2.2 nathanw __asm__ ("mfmsr %0" : "=r"(msrsave)); 152 1.2.2.2 nathanw __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 153 1.2.2.2 nathanw ipending |= pending; 154 1.2.2.2 nathanw __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 155 1.2.2.2 nathanw } 156 1.2.2.2 nathanw 157 1.2.2.2 nathanw #define ICU_LEN 32 158 1.2.2.2 nathanw #define IRQ_SLAVE 2 159 1.2.2.2 nathanw #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE) 160 1.2.2.2 nathanw 161 1.2.2.2 nathanw #define MVMEPPC_INTR_REG 0xbffff000 162 1.2.2.2 nathanw #define INTR_VECTOR_REG 0xff0 163 1.2.2.2 nathanw 164 1.2.2.2 nathanw #define SINT_CLOCK 0x20000000 165 1.2.2.2 nathanw #define SINT_NET 0x40000000 166 1.2.2.2 nathanw #define SINT_SERIAL 0x80000000 167 1.2.2.2 nathanw #define SPL_CLOCK 0x00000001 168 1.2.2.2 nathanw #define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL) 169 1.2.2.2 nathanw 170 1.2.2.2 nathanw #define CNT_SINT_NET 29 171 1.2.2.2 nathanw #define CNT_SINT_CLOCK 30 172 1.2.2.2 nathanw #define CNT_SINT_SERIAL 31 173 1.2.2.2 nathanw #define CNT_CLOCK 0 174 1.2.2.2 nathanw 175 1.2.2.2 nathanw #define splbio() splraise(imask[IPL_BIO]) 176 1.2.2.2 nathanw #define splnet() splraise(imask[IPL_NET]) 177 1.2.2.2 nathanw #define spltty() splraise(imask[IPL_TTY]) 178 1.2.2.2 nathanw #define splclock() splraise(imask[IPL_CLOCK]) 179 1.2.2.2 nathanw #define splvm() splraise(imask[IPL_IMP]) 180 1.2.2.3 nathanw #define splaudio() splraise(imask[IPL_AUDIO]) 181 1.2.2.2 nathanw #define splserial() splraise(imask[IPL_SERIAL]) 182 1.2.2.2 nathanw #define splstatclock() splclock() 183 1.2.2.2 nathanw #define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 184 1.2.2.2 nathanw #define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 185 1.2.2.2 nathanw #define splsoftnet() splraise(imask[IPL_SOFTNET]) 186 1.2.2.2 nathanw #define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 187 1.2.2.2 nathanw 188 1.2.2.3 nathanw #define spllpt() spltty() 189 1.2.2.3 nathanw 190 1.2.2.2 nathanw #define setsoftclock() set_sint(SINT_CLOCK); 191 1.2.2.2 nathanw #define setsoftnet() set_sint(SINT_NET); 192 1.2.2.2 nathanw #define setsoftserial() set_sint(SINT_SERIAL); 193 1.2.2.3 nathanw 194 1.2.2.3 nathanw #define splhigh() splraise(imask[IPL_HIGH]) 195 1.2.2.3 nathanw #define splsched() splhigh() 196 1.2.2.3 nathanw #define spllock() splhigh() 197 1.2.2.3 nathanw #define splx(x) spllower(x) 198 1.2.2.3 nathanw #define spl0() spllower(0) 199 1.2.2.2 nathanw 200 1.2.2.2 nathanw #endif /* !_LOCORE */ 201 1.2.2.2 nathanw 202 1.2.2.2 nathanw #endif /* !_MVMEPPC_INTR_H_ */ 203
Indexes created Wed Oct 22 13:09:56 GMT 2025