pci_machdep.c revision 1.4 1 1.4 lukem /* $NetBSD: pci_machdep.c,v 1.4 2003/07/15 02:43:53 lukem Exp $ */
2 1.1 scw
3 1.1 scw /*
4 1.1 scw * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
5 1.1 scw * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
6 1.1 scw *
7 1.1 scw * Redistribution and use in source and binary forms, with or without
8 1.1 scw * modification, are permitted provided that the following conditions
9 1.1 scw * are met:
10 1.1 scw * 1. Redistributions of source code must retain the above copyright
11 1.1 scw * notice, this list of conditions and the following disclaimer.
12 1.1 scw * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 scw * notice, this list of conditions and the following disclaimer in the
14 1.1 scw * documentation and/or other materials provided with the distribution.
15 1.1 scw * 3. All advertising materials mentioning features or use of this software
16 1.1 scw * must display the following acknowledgement:
17 1.1 scw * This product includes software developed by Charles M. Hannum.
18 1.1 scw * 4. The name of the author may not be used to endorse or promote products
19 1.1 scw * derived from this software without specific prior written permission.
20 1.1 scw *
21 1.1 scw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.1 scw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.1 scw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.1 scw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.1 scw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.1 scw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.1 scw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.1 scw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.1 scw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.1 scw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.1 scw */
32 1.1 scw
33 1.1 scw /*
34 1.1 scw * Machine-specific functions for PCI autoconfiguration.
35 1.1 scw *
36 1.1 scw * On PCs, there are two methods of generating PCI configuration cycles.
37 1.1 scw * We try to detect the appropriate mechanism for this machine and set
38 1.1 scw * up a few function pointers to access the correct method directly.
39 1.1 scw */
40 1.4 lukem
41 1.4 lukem #include <sys/cdefs.h>
42 1.4 lukem __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.4 2003/07/15 02:43:53 lukem Exp $");
43 1.1 scw
44 1.1 scw #include <sys/types.h>
45 1.1 scw #include <sys/param.h>
46 1.1 scw #include <sys/time.h>
47 1.1 scw #include <sys/systm.h>
48 1.1 scw #include <sys/errno.h>
49 1.1 scw #include <sys/device.h>
50 1.1 scw
51 1.1 scw #include <uvm/uvm_extern.h>
52 1.1 scw
53 1.1 scw #define _POWERPC_BUS_DMA_PRIVATE
54 1.1 scw #include <machine/bus.h>
55 1.1 scw #include <machine/intr.h>
56 1.1 scw #include <machine/platform.h>
57 1.3 matt
58 1.3 matt #include <powerpc/pio.h>
59 1.1 scw
60 1.1 scw #include <dev/isa/isavar.h>
61 1.1 scw #include <dev/pci/pcivar.h>
62 1.1 scw #include <dev/pci/pcireg.h>
63 1.1 scw #include <dev/pci/pcidevs.h>
64 1.1 scw
65 1.1 scw #define PCI_MODE1_ENABLE 0x80000000UL
66 1.1 scw #define PCI_MODE1_ADDRESS_REG (MVMEPPC_KVA_BASE_IO + 0xcf8)
67 1.1 scw #define PCI_MODE1_DATA_REG (MVMEPPC_KVA_BASE_IO + 0xcfc)
68 1.1 scw
69 1.1 scw #define o2i(off) ((off)/sizeof(pcireg_t))
70 1.1 scw
71 1.1 scw void pci_intr_fixup(int, int, int *);
72 1.1 scw
73 1.1 scw #ifdef DEBUG
74 1.1 scw #define DPRF(x) printf x
75 1.1 scw #else
76 1.1 scw #define DPRF(x)
77 1.1 scw #endif
78 1.1 scw
79 1.1 scw /*
80 1.1 scw * PCI doesn't have any special needs; just use the generic versions
81 1.1 scw * of these functions.
82 1.1 scw */
83 1.1 scw struct powerpc_bus_dma_tag pci_bus_dma_tag = {
84 1.1 scw 0, /* _bounce_thresh */
85 1.1 scw _bus_dmamap_create,
86 1.1 scw _bus_dmamap_destroy,
87 1.1 scw _bus_dmamap_load,
88 1.1 scw _bus_dmamap_load_mbuf,
89 1.1 scw _bus_dmamap_load_uio,
90 1.1 scw _bus_dmamap_load_raw,
91 1.1 scw _bus_dmamap_unload,
92 1.1 scw NULL, /* _dmamap_sync */
93 1.1 scw _bus_dmamem_alloc,
94 1.1 scw _bus_dmamem_free,
95 1.1 scw _bus_dmamem_map,
96 1.1 scw _bus_dmamem_unmap,
97 1.1 scw _bus_dmamem_mmap,
98 1.1 scw };
99 1.1 scw
100 1.1 scw void
101 1.1 scw pci_attach_hook(struct device *parent, struct device *self,
102 1.1 scw struct pcibus_attach_args *pba)
103 1.1 scw {
104 1.1 scw
105 1.1 scw /* Nothing to do. */
106 1.1 scw }
107 1.1 scw
108 1.1 scw int
109 1.1 scw pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
110 1.1 scw {
111 1.1 scw
112 1.1 scw /*
113 1.1 scw * Bus number is irrelevant. Configuration Mechanism 1 is in
114 1.1 scw * use, can have devices 0-32 (i.e. the `normal' range).
115 1.1 scw */
116 1.1 scw return (32);
117 1.1 scw }
118 1.1 scw
119 1.1 scw pcitag_t
120 1.1 scw pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
121 1.1 scw {
122 1.1 scw pcitag_t tag;
123 1.1 scw
124 1.1 scw if (bus >= 256 || device >= 32 || function >= 8)
125 1.1 scw panic("pci_make_tag: bad request");
126 1.1 scw
127 1.1 scw tag = PCI_MODE1_ENABLE |
128 1.1 scw (bus << 16) | (device << 11) | (function << 8);
129 1.1 scw return tag;
130 1.1 scw }
131 1.1 scw
132 1.1 scw void
133 1.1 scw pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
134 1.1 scw {
135 1.1 scw
136 1.1 scw if (bp != NULL)
137 1.1 scw *bp = (tag >> 16) & 0xff;
138 1.1 scw if (dp != NULL)
139 1.1 scw *dp = (tag >> 11) & 0x1f;
140 1.1 scw if (fp != NULL)
141 1.1 scw *fp = (tag >> 8) & 0x7;
142 1.1 scw return;
143 1.1 scw }
144 1.1 scw
145 1.1 scw pcireg_t
146 1.1 scw pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
147 1.1 scw {
148 1.1 scw pcireg_t data;
149 1.1 scw
150 1.1 scw out32rb(PCI_MODE1_ADDRESS_REG, tag | reg);
151 1.1 scw data = in32rb(PCI_MODE1_DATA_REG);
152 1.1 scw out32rb(PCI_MODE1_ADDRESS_REG, 0);
153 1.1 scw return data;
154 1.1 scw }
155 1.1 scw
156 1.1 scw void
157 1.1 scw pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
158 1.1 scw {
159 1.1 scw
160 1.1 scw out32rb(PCI_MODE1_ADDRESS_REG, tag | reg);
161 1.1 scw out32rb(PCI_MODE1_DATA_REG, data);
162 1.1 scw out32rb(PCI_MODE1_ADDRESS_REG, 0);
163 1.1 scw }
164 1.1 scw
165 1.1 scw int
166 1.1 scw pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
167 1.1 scw {
168 1.1 scw int pin = pa->pa_intrpin;
169 1.1 scw int line = pa->pa_intrline;
170 1.1 scw
171 1.1 scw if (pin == 0) {
172 1.1 scw /* No IRQ used. */
173 1.1 scw goto bad;
174 1.1 scw }
175 1.1 scw
176 1.1 scw if (pin > 4) {
177 1.1 scw printf("pci_intr_map: bad interrupt pin %d\n", pin);
178 1.1 scw goto bad;
179 1.1 scw }
180 1.1 scw
181 1.1 scw /*
182 1.1 scw * Section 6.2.4, `Miscellaneous Functions', says that 255 means
183 1.1 scw * `unknown' or `no connection' on a PC. We assume that a device with
184 1.1 scw * `no connection' either doesn't have an interrupt (in which case the
185 1.1 scw * pin number should be 0, and would have been noticed above), or
186 1.1 scw * wasn't configured by the BIOS (in which case we punt, since there's
187 1.1 scw * no real way we can know how the interrupt lines are mapped in the
188 1.1 scw * hardware).
189 1.1 scw *
190 1.1 scw * XXX
191 1.1 scw * Since IRQ 0 is only used by the clock, and we can't actually be sure
192 1.1 scw * that the BIOS did its job, we also recognize that as meaning that
193 1.1 scw * the BIOS has not configured the device.
194 1.1 scw */
195 1.1 scw if (line == 0 || line == 255) {
196 1.1 scw printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
197 1.1 scw goto bad;
198 1.1 scw } else {
199 1.1 scw if (line >= ICU_LEN) {
200 1.1 scw printf("pci_intr_map: bad interrupt line %d\n", line);
201 1.1 scw goto bad;
202 1.1 scw }
203 1.1 scw if (line == IRQ_SLAVE) {
204 1.1 scw printf("pci_intr_map: changed line 2 to line 9\n");
205 1.1 scw line = 9;
206 1.1 scw }
207 1.1 scw }
208 1.1 scw
209 1.1 scw *ihp = line;
210 1.1 scw return 0;
211 1.1 scw
212 1.1 scw bad:
213 1.1 scw *ihp = -1;
214 1.1 scw return 1;
215 1.1 scw }
216 1.1 scw
217 1.1 scw const char *
218 1.1 scw pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
219 1.1 scw {
220 1.1 scw static char irqstr[8]; /* 4 + 2 + NULL + sanity */
221 1.1 scw
222 1.1 scw if (ih == 0 || ih >= ICU_LEN || ih == IRQ_SLAVE)
223 1.2 provos panic("pci_intr_string: bogus handle 0x%x", ih);
224 1.1 scw
225 1.1 scw sprintf(irqstr, "irq %d", ih);
226 1.1 scw return (irqstr);
227 1.1 scw
228 1.1 scw }
229 1.1 scw
230 1.1 scw const struct evcnt *
231 1.1 scw pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
232 1.1 scw {
233 1.1 scw
234 1.1 scw /* XXX for now, no evcnt parent reported */
235 1.1 scw return NULL;
236 1.1 scw }
237 1.1 scw
238 1.1 scw void *
239 1.1 scw pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
240 1.1 scw int (*func)(void *), void *arg)
241 1.1 scw {
242 1.1 scw
243 1.1 scw if (ih == 0 || ih >= ICU_LEN || ih == IRQ_SLAVE)
244 1.2 provos panic("pci_intr_establish: bogus handle 0x%x", ih);
245 1.1 scw
246 1.1 scw return isa_intr_establish(NULL, ih, IST_LEVEL, level, func, arg);
247 1.1 scw }
248 1.1 scw
249 1.1 scw void
250 1.1 scw pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
251 1.1 scw {
252 1.1 scw
253 1.1 scw isa_intr_disestablish(NULL, cookie);
254 1.1 scw }
255 1.1 scw
256 1.1 scw void
257 1.1 scw pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
258 1.1 scw int swiz, int *iline)
259 1.1 scw {
260 1.1 scw
261 1.1 scw (*platform->pci_intr_fixup)(bus, dev, iline);
262 1.1 scw }
263