srt0.S revision 1.1.122.1 1 1.1 scw /* $NetBSD: srt0.S,v 1.1.122.1 2008/06/02 13:22:27 mjf Exp $ */
2 1.1 scw
3 1.1 scw /*-
4 1.1 scw * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 1.1 scw * All rights reserved.
6 1.1 scw *
7 1.1 scw * This code is derived from software contributed to The NetBSD Foundation
8 1.1 scw * by Steve C. Woodford.
9 1.1 scw *
10 1.1 scw * Redistribution and use in source and binary forms, with or without
11 1.1 scw * modification, are permitted provided that the following conditions
12 1.1 scw * are met:
13 1.1 scw * 1. Redistributions of source code must retain the above copyright
14 1.1 scw * notice, this list of conditions and the following disclaimer.
15 1.1 scw * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 scw * notice, this list of conditions and the following disclaimer in the
17 1.1 scw * documentation and/or other materials provided with the distribution.
18 1.1 scw *
19 1.1 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 scw * POSSIBILITY OF SUCH DAMAGE.
30 1.1 scw */
31 1.1 scw
32 1.1 scw #include <machine/asm.h>
33 1.1 scw #include <machine/psl.h>
34 1.1 scw #include <powerpc/spr.h>
35 1.1 scw
36 1.1 scw #define STACK_SIZE 8192
37 1.1 scw
38 1.1 scw /*
39 1.1 scw * The main entry point when loaded by PPC-Bug.
40 1.1 scw *
41 1.1 scw * There are two possible entry conditions here:
42 1.1 scw *
43 1.1 scw * 1) We were booted in `PReP' mode, either from disk or the network.
44 1.1 scw * In this case, we have no control over the load address so we
45 1.1 scw * have to relocate ourselves to the appropriate place.
46 1.1 scw * The firmware passes us the following registers:
47 1.1 scw *
48 1.1 scw * r1 -> Temporary stack
49 1.1 scw * r3 -> Residual Data
50 1.1 scw * r4 -> The address we were loaded to
51 1.1 scw * r5 -> Zero
52 1.1 scw *
53 1.1 scw * 2) We were booted over the network in Non-PReP mode. In this case,
54 1.1 scw * the load address is usually set using PPC-Bug's "niot" command,
55 1.1 scw * but we won't depend on it so relocation may be required. The
56 1.1 scw * firmware passes us the following registers:
57 1.1 scw *
58 1.1 scw * r1 -> Temporary stack
59 1.1 scw * r3 -> CLUN of the network device we booted from
60 1.1 scw * r4 -> DLUN of the network device we booted from
61 1.1 scw * r5 -> Non-zero
62 1.1 scw * r6 -> Base address of network device
63 1.1 scw * r7 -> Execution address of loaded program
64 1.1 scw * r8 -> Address of IP-address data structure
65 1.1 scw * r9 -> Pointer to start of filename string
66 1.1 scw * r10 -> Pointer to end+1 of filename string
67 1.1 scw * r11 -> Pointer to start of argument string
68 1.1 scw * r12 -> Pointer to end+1 of argument string
69 1.1 scw *
70 1.1 scw * The obvious way to distinguish between the two boot modes is by
71 1.1 scw * checking the value of r5.
72 1.1 scw */
73 1.1 scw ENTRY(_start)
74 1.1 scw bl 1f
75 1.1 scw 1: xor r0,r0,r0
76 1.1 scw
77 1.1 scw /* First, switch off Instruction and Data caches. */
78 1.1 scw mfspr r13,SPR_HID0
79 1.1 scw LDCONST(r14, HID0_DCE|HID0_ICE)
80 1.1 scw andc r13,r13,r14
81 1.1 scw sync
82 1.1 scw mtspr SPR_HID0,r13
83 1.1 scw
84 1.1 scw
85 1.1 scw /*
86 1.1 scw * All registers now available. Let's see if we need to relocate
87 1.1 scw */
88 1.1 scw LDCONST(r13,_C_LABEL(_start)) /* Where we'd like to be */
89 1.1 scw LDCONST(r14,_C_LABEL(edata)) /* End of data section */
90 1.1 scw LDCONST(r15,0x3)
91 1.1 scw add r14,r14,r15
92 1.1 scw andc r14,r14,r15 /* Rounded up to the nearest 32-bits */
93 1.1 scw sub r15,r14,r13 /* Our size, in bytes */
94 1.1 scw mflr r16 /* Get address we were loaded to */
95 1.1 scw subi r16,r16,0x4 /* Correct for branch */
96 1.1 scw cmp cr0,r13,r16 /* Do we need to relocate? */
97 1.1 scw beq _ASM_LABEL(clrbss) /* No relocation necessary */
98 1.1 scw li r17,0x4
99 1.1 scw bgt 1f /* Relocate using forward copy? */
100 1.1 scw
101 1.1 scw /* Nope. Need to copy in reverse in case of overlap */
102 1.1 scw mr r13,r14 /* dest -> end */
103 1.1 scw add r16,r16,r15 /* src + size */
104 1.1 scw subi r17,r17,0x8 /* Increment is -4 */
105 1.1 scw
106 1.1 scw /*
107 1.1 scw * Do the relocation
108 1.1 scw * r13 -> dest
109 1.1 scw * r15 -> number of bytes
110 1.1 scw * r16 -> src
111 1.1 scw * r17 -> Increment (+4 or -4)
112 1.1 scw */
113 1.1 scw 1: srwi r15,r15,0x2 /* Convert length to 32-bit words */
114 1.1 scw mtctr r15 /* Save in counter register */
115 1.1 scw
116 1.1 scw 2: lwz r15,0(r16)
117 1.1 scw stw r15,0(r13)
118 1.1 scw add r16,r16,r17
119 1.1 scw add r13,r13,r17
120 1.1 scw bdnz 2b
121 1.1 scw
122 1.1 scw /* Now do an absolute jump to the relocated code */
123 1.1 scw LDCONST(r13,_ASM_LABEL(clrbss))
124 1.1 scw mtlr r13
125 1.1 scw blr
126 1.1 scw
127 1.1 scw ASENTRY(clrbss)
128 1.1 scw LDCONST(r13,_C_LABEL(edata)) /* End of the data section */
129 1.1 scw LDCONST(r14,_C_LABEL(end)) /* End of BSS */
130 1.1 scw LDCONST(r15,0x3)
131 1.1 scw add r14,r14,r15
132 1.1 scw andc r14,r14,r15 /* Round-up end of BSS to 32-bits */
133 1.1 scw sub r15,r14,r13 /* r15 == length of BSS */
134 1.1 scw srwi r15,r15,0x2
135 1.1 scw mtctr r15 /* CTR == # of 32-bit words in BSS */
136 1.1 scw 1: stw r0,0(r13) /* Clear BSS */
137 1.1 scw addi r13,r13,4
138 1.1 scw bdnz 1b
139 1.1 scw
140 1.1 scw /* Fix up our own stack */
141 1.1 scw LDCONST(r1,stack)
142 1.1 scw addi r1,r1,STACK_SIZE-0x10
143 1.1 scw LDCONST(r13,0x0f)
144 1.1 scw andc r1,r1,r13
145 1.1 scw
146 1.1 scw /*
147 1.1 scw * Copy the arguments passed in from Bug into bug_bootinfo
148 1.1 scw *
149 1.1 scw * See bugsyscalls.h for details.
150 1.1 scw */
151 1.1 scw LDCONST(r13,_C_LABEL(bug_bootinfo))
152 1.1 scw stw r5,0x00(r13)
153 1.1 scw stw r3,0x04(r13)
154 1.1 scw stw r4,0x08(r13)
155 1.1 scw stw r6,0x0c(r13)
156 1.1 scw stw r7,0x10(r13)
157 1.1 scw stw r8,0x14(r13)
158 1.1 scw stw r9,0x18(r13)
159 1.1 scw stw r10,0x1c(r13)
160 1.1 scw stw r11,0x20(r13)
161 1.1 scw stw r12,0x24(r13)
162 1.1 scw
163 1.1 scw mr r3,r13
164 1.1 scw bl _C_LABEL(main) /* void main(void) */
165 1.1 scw /* FALLTHROUGH */
166 1.1 scw
167 1.1 scw /*
168 1.1 scw * Return to the debugger, either because main() returned or via panic().
169 1.1 scw */
170 1.1 scw ENTRY(_rtt)
171 1.1 scw addi r10,0,0x0063
172 1.1 scw sc
173 1.1 scw 1: nop
174 1.1 scw b 1b
175 1.1 scw
176 1.1 scw /*
177 1.1 scw * C code runs on this stack.
178 1.1 scw */
179 1.1 scw .comm stack,STACK_SIZE,4
180 1.1 scw .comm errno,4,4
181 1.1 scw .comm debug,4,4
182