irqhandler.h revision 1.1 1 1.1 matt /* $NetBSD: irqhandler.h,v 1.1 2001/04/19 07:11:02 matt Exp $ */
2 1.1 matt
3 1.1 matt /*
4 1.1 matt * Copyright (c) 1994-1996 Mark Brinicombe.
5 1.1 matt * Copyright (c) 1994 Brini.
6 1.1 matt * All rights reserved.
7 1.1 matt *
8 1.1 matt * This code is derived from software written for Brini by Mark Brinicombe
9 1.1 matt *
10 1.1 matt * Redistribution and use in source and binary forms, with or without
11 1.1 matt * modification, are permitted provided that the following conditions
12 1.1 matt * are met:
13 1.1 matt * 1. Redistributions of source code must retain the above copyright
14 1.1 matt * notice, this list of conditions and the following disclaimer.
15 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 matt * notice, this list of conditions and the following disclaimer in the
17 1.1 matt * documentation and/or other materials provided with the distribution.
18 1.1 matt * 3. All advertising materials mentioning features or use of this software
19 1.1 matt * must display the following acknowledgement:
20 1.1 matt * This product includes software developed by Mark Brinicombe
21 1.1 matt * for the NetBSD Project.
22 1.1 matt * 4. The name of the company nor the name of the author may be used to
23 1.1 matt * endorse or promote products derived from this software without specific
24 1.1 matt * prior written permission.
25 1.1 matt *
26 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
27 1.1 matt * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28 1.1 matt * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 1.1 matt * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30 1.1 matt * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31 1.1 matt * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 1.1 matt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 1.1 matt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 1.1 matt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 1.1 matt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 1.1 matt * SUCH DAMAGE.
37 1.1 matt *
38 1.1 matt * IRQ related stuff (defines + structures)
39 1.1 matt *
40 1.1 matt * Created : 30/09/94
41 1.1 matt */
42 1.1 matt
43 1.1 matt #ifndef _ARM32_IRQHANDLER_H_
44 1.1 matt #define _ARM32_IRQHANDLER_H_
45 1.1 matt
46 1.1 matt #if defined(_KERNEL) && !defined(_LKM)
47 1.1 matt #include "opt_cputypes.h"
48 1.1 matt #endif
49 1.1 matt
50 1.1 matt #ifndef _LOCORE
51 1.1 matt #include <sys/types.h>
52 1.1 matt #endif /* _LOCORE */
53 1.1 matt
54 1.1 matt /* Define the IRQ bits */
55 1.1 matt
56 1.1 matt /*
57 1.1 matt * XXX this is really getting rather horrible.
58 1.1 matt * Shortly to be replaced with system specific interrupt tables and handling
59 1.1 matt */
60 1.1 matt
61 1.1 matt #if defined(RISCPC) || defined(CPU_ARM7500)
62 1.1 matt
63 1.1 matt #ifdef CPU_ARM7500
64 1.1 matt
65 1.1 matt /*#define IRQ_PRINTER 0x00*/
66 1.1 matt #define IRQ_RESERVED0 0x01
67 1.1 matt #define IRQ_BUTTON 0x02
68 1.1 matt #define IRQ_FLYBACK 0x03
69 1.1 matt #define IRQ_POR 0x04
70 1.1 matt #define IRQ_TIMER0 0x05
71 1.1 matt #define IRQ_TIMER1 0x06
72 1.1 matt
73 1.1 matt #define IRQ_DREQ3 0x08
74 1.1 matt /*#define IRQ_HD1 0x09*/
75 1.1 matt /*#define IRQ_HD IRQ_HD1*/
76 1.1 matt #define IRQ_DREQ2 0x0A
77 1.1 matt /*#define IRQ_FLOPPY 0x0C*/
78 1.1 matt /*#define IRQ_SERIAL 0x0D*/
79 1.1 matt #define IRQ_KBDTX 0x0E
80 1.1 matt #define IRQ_KBDRX 0x0F
81 1.1 matt
82 1.1 matt #define IRQ_IRQ3 0x10
83 1.1 matt #define IRQ_IRQ4 0x11
84 1.1 matt #define IRQ_IRQ5 0x12
85 1.1 matt #define IRQ_IRQ6 0x13
86 1.1 matt #define IRQ_IRQ7 0x14
87 1.1 matt #define IRQ_IRQ9 0x15
88 1.1 matt #define IRQ_IRQ10 0x16
89 1.1 matt #define IRQ_IRQ11 0x17
90 1.1 matt
91 1.1 matt #define IRQ_MSDRX 0x18
92 1.1 matt #define IRQ_MSDTX 0x19
93 1.1 matt #define IRQ_ATOD 0x1A
94 1.1 matt #define IRQ_CLOCK 0x1B
95 1.1 matt #define IRQ_PANIC 0x1C
96 1.1 matt #define IRQ_RESERVED2 0x1D
97 1.1 matt #define IRQ_RESERVED3 0x1E
98 1.1 matt
99 1.1 matt /*
100 1.1 matt * Note that Sound DMA IRQ is on the 31st vector.
101 1.1 matt * It's not part of the IRQD.
102 1.1 matt */
103 1.1 matt #define IRQ_SDMA 0x1F
104 1.1 matt
105 1.1 matt /* Several interrupts are different between the A7000 and RC7500 */
106 1.1 matt #ifdef RC7500
107 1.1 matt
108 1.1 matt #define IRQ_FIQDOWN 0x07
109 1.1 matt #define IRQ_ETHERNET 0x0B
110 1.1 matt #define IRQ_HD2 IRQ_IRQ11
111 1.1 matt
112 1.1 matt #else /* RC7500 */
113 1.1 matt
114 1.1 matt #define IRQ_RESERVED1 0x07
115 1.1 matt #define IRQ_EXTENDED 0x0B
116 1.1 matt #define IRQ_PODULE 0x0D
117 1.1 matt
118 1.1 matt #define IRQ_EXPCARD0 0x20
119 1.1 matt #define IRQ_EXPCARD1 0x21
120 1.1 matt #define IRQ_EXPCARD2 0x22
121 1.1 matt #define IRQ_EXPCARD3 0x23
122 1.1 matt #define IRQ_EXPCARD4 0x24
123 1.1 matt #define IRQ_EXPCARD5 0x25
124 1.1 matt #define IRQ_EXPCARD6 0x26
125 1.1 matt #define IRQ_EXPCARD7 0x27
126 1.1 matt
127 1.1 matt #endif /* RC7500 */
128 1.1 matt
129 1.1 matt #else /* CPU_ARM7500 */
130 1.1 matt
131 1.1 matt #ifdef RISCPC
132 1.1 matt /*#define IRQ_PRINTER 0x00*/
133 1.1 matt #define IRQ_RESERVED0 0x01
134 1.1 matt /*#define IRQ_FLOPPYIDX 0x02*/
135 1.1 matt #define IRQ_FLYBACK 0x03
136 1.1 matt #define IRQ_POR 0x04
137 1.1 matt #define IRQ_TIMER0 0x05
138 1.1 matt #define IRQ_TIMER1 0x06
139 1.1 matt #define IRQ_RESERVED1 0x07
140 1.1 matt
141 1.1 matt #define IRQ_RESERVED2 0x08
142 1.1 matt /*#define IRQ_HD 0x09*/
143 1.1 matt /*#define IRQ_SERIAL 0x0A*/
144 1.1 matt #define IRQ_EXTENDED 0x0B
145 1.1 matt /*#define IRQ_FLOPPY 0x0C*/
146 1.1 matt #define IRQ_PODULE 0x0D
147 1.1 matt #define IRQ_KBDTX 0x0E
148 1.1 matt #define IRQ_KBDRX 0x0F
149 1.1 matt
150 1.1 matt #define IRQ_DMACH0 0x10
151 1.1 matt #define IRQ_DMACH1 0x11
152 1.1 matt #define IRQ_DMACH2 0x12
153 1.1 matt #define IRQ_DMACH3 0x13
154 1.1 matt #define IRQ_DMASCH0 0x14
155 1.1 matt #define IRQ_DMASCH1 0x15
156 1.1 matt #define IRQ_RESERVED3 0x16
157 1.1 matt #define IRQ_RESERVED4 0x17
158 1.1 matt
159 1.1 matt #define IRQ_EXPCARD0 0x18
160 1.1 matt #define IRQ_EXPCARD1 0x19
161 1.1 matt #define IRQ_EXPCARD2 0x1A
162 1.1 matt #define IRQ_EXPCARD3 0x1B
163 1.1 matt #define IRQ_EXPCARD4 0x1C
164 1.1 matt #define IRQ_EXPCARD5 0x1D
165 1.1 matt #define IRQ_EXPCARD6 0x1E
166 1.1 matt #define IRQ_EXPCARD7 0x1F
167 1.1 matt #endif /* RISCPC */
168 1.1 matt
169 1.1 matt #endif /* CPU_ARM7500 */
170 1.1 matt
171 1.1 matt #endif /* RISPC || CPU_ARM7500 */
172 1.1 matt
173 1.1 matt #ifdef OFWGENCFG
174 1.1 matt /* These are just made up for now! -JJK */
175 1.1 matt #define IRQ_TIMER0 0
176 1.1 matt #endif
177 1.1 matt
178 1.1 matt /* XXX why is this in ARM7500? */
179 1.1 matt #ifdef SHARK
180 1.1 matt /*
181 1.1 matt * shark hardware requirements for IRQ's:
182 1.1 matt * IDE: 14 (hardwired)
183 1.1 matt * PCI: 5, 9, 10, 11, 15(mapped to UMIPCI inta, intb, intc, intd)
184 1.1 matt * UMIISA: 10, 11, 12
185 1.1 matt * SuperIO: 1, 3..12, 14, 15(all may be remapped. defaults as follows.)
186 1.1 matt * KBC: 1
187 1.1 matt * USI: 3 (UART with Slow Infrared support)
188 1.1 matt * UART: 4
189 1.1 matt * FLOPPY: 6 (not currently used on shark)
190 1.1 matt * PARALLEL: 7
191 1.1 matt * RTC: 8 (not used on shark: RTC in sequoia used)
192 1.1 matt * MOUSE: 12
193 1.1 matt * Sequoia: 8 (internal RTC hardwired to irq 8)
194 1.1 matt * Codec: 5, 7, 9, 10, 15 (irqe, connected to 15, has special status.)
195 1.1 matt * CS8900: 5, 10, 11, 12 (P.14 of datasheet sez only 1 used/time)
196 1.1 matt * FERR#: 13 (unconnected floating point error)
197 1.1 matt *
198 1.1 matt * total of 15 irqs:
199 1.1 matt * timer, ide, 2 umi = isa/pci, ethernet, 2 codec, kb, usi, uart, floppy,
200 1.1 matt * parallel, rtc, mouse, ferr (irq 13)
201 1.1 matt *
202 1.1 matt * eventually, need to read the OFW dev info tree, and allocate IRQs.
203 1.1 matt * hardcoded for now.
204 1.1 matt */
205 1.1 matt #define IRQ_TIMER0 0x00 /* hardwired to 8254 counter 0 in sequoia */
206 1.1 matt #define IRQ_KEYBOARD 0x01
207 1.1 matt #define IRQ_CASCADE 0x02 /* hardwired IRQ for second 8259 = IRQ_SLAVE */
208 1.1 matt #define IRQ_USI 0x03
209 1.1 matt #define IRQ_UART 0x04
210 1.1 matt #define IRQ_ETHERNET 0x05
211 1.1 matt #define IRQ_FLOPPY 0x06
212 1.1 matt #define IRQ_PARALLEL 0x07
213 1.1 matt
214 1.1 matt #define IRQ_RTC 0x08 /* hardwired to the sequoia RTC */
215 1.1 matt #define IRQ_CODEC1 0x09
216 1.1 matt #define IRQ_UMI1 0x0A /* isa or pci */
217 1.1 matt #define IRQ_UMI2 0x0B /* isa or pci */
218 1.1 matt
219 1.1 matt #define IRQ_MOUSE 0x0C
220 1.1 matt #define IRQ_FERR 0x0D /* FERR# pin on sequoia needs to be connected */
221 1.1 matt #define IRQ_IDE 0x0E /* hardwired to the IDE connector */
222 1.1 matt #define IRQ_CODEC2 0x0F /* special interrupt on codec */
223 1.1 matt
224 1.1 matt /* XXX should this go into isa_machdep.h. Somewhere else? */
225 1.1 matt /* Interrupt sharing types. */
226 1.1 matt #define IST_NONE 0 /* none */
227 1.1 matt #define IST_PULSE 1 /* pulsed */
228 1.1 matt #define IST_EDGE 2 /* edge-triggered */
229 1.1 matt #define IST_LEVEL 3 /* level-triggered */
230 1.1 matt
231 1.1 matt #endif /* SHARK */
232 1.1 matt
233 1.1 matt #define IRQ_VSYNC IRQ_FLYBACK /* Aliased */
234 1.1 matt #define IRQ_NETSLOT IRQ_EXTENDED
235 1.1 matt
236 1.1 matt #define IRQ_INSTRUCT -1
237 1.1 matt #define NIRQS 0x20
238 1.1 matt
239 1.1 matt #include <machine/intr.h>
240 1.1 matt
241 1.1 matt #ifndef _LOCORE
242 1.1 matt typedef struct irqhandler {
243 1.1 matt int (*ih_func) __P((void *arg));/* handler function */
244 1.1 matt void *ih_arg; /* Argument to handler */
245 1.1 matt int ih_level; /* Interrupt level */
246 1.1 matt int ih_num; /* Interrupt number (for accounting) */
247 1.1 matt const char *ih_name; /* Name of interrupt (for vmstat -i) */
248 1.1 matt u_int ih_flags; /* Interrupt flags */
249 1.1 matt u_int ih_maskaddr; /* mask address for expansion cards */
250 1.1 matt u_int ih_maskbits; /* interrupt bit for expansion cards */
251 1.1 matt struct irqhandler *ih_next; /* next handler */
252 1.1 matt } irqhandler_t;
253 1.1 matt
254 1.1 matt #ifdef _KERNEL
255 1.1 matt extern u_int irqmasks[IPL_LEVELS];
256 1.1 matt extern irqhandler_t *irqhandlers[NIRQS];
257 1.1 matt
258 1.1 matt void irq_init __P((void));
259 1.1 matt int irq_claim __P((int, irqhandler_t *));
260 1.1 matt int irq_release __P((int, irqhandler_t *));
261 1.1 matt void *intr_claim __P((int irq, int level, const char *name, int (*func) __P((void *)), void *arg));
262 1.1 matt int intr_release __P((void *ih));
263 1.1 matt void irq_setmasks __P((void));
264 1.1 matt void disable_irq __P((int));
265 1.1 matt void enable_irq __P((int));
266 1.1 matt #endif /* _KERNEL */
267 1.1 matt #endif /* _LOCORE */
268 1.1 matt
269 1.1 matt #define IRQ_FLAG_ACTIVE 0x00000001 /* This is the active handler in list */
270 1.1 matt
271 1.1 matt #ifndef _LOCORE
272 1.1 matt typedef struct fiqhandler {
273 1.1 matt void (*fh_func) __P((void));/* handler function */
274 1.1 matt u_int fh_size; /* Size of handler function */
275 1.1 matt u_int fh_mask; /* FIQ mask */
276 1.1 matt u_int fh_r8; /* FIQ mode r8 */
277 1.1 matt u_int fh_r9; /* FIQ mode r9 */
278 1.1 matt u_int fh_r10; /* FIQ mode r10 */
279 1.1 matt u_int fh_r11; /* FIQ mode r11 */
280 1.1 matt u_int fh_r12; /* FIQ mode r12 */
281 1.1 matt u_int fh_r13; /* FIQ mode r13 */
282 1.1 matt } fiqhandler_t;
283 1.1 matt
284 1.1 matt #ifdef _KERNEL
285 1.1 matt int fiq_claim __P((fiqhandler_t *));
286 1.1 matt int fiq_release __P((fiqhandler_t *));
287 1.1 matt #endif /* _KERNEL */
288 1.1 matt #endif /* _LOCORE */
289 1.1 matt
290 1.1 matt #endif /* _ARM32_IRQHANDLER_H_ */
291 1.1 matt
292 1.1 matt /* End of irqhandler.h */
293