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dmac_0266.h revision 1.4 
      1 /*	$NetBSD: dmac_0266.h,v 1.4 2005/12/24 20:07:20 perry Exp $	*/
      2 
      3 /*-
      4  * Copyright (C) 1999 Izumi Tsutsui.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 /* DMAC 266 register definition */
     30 
     31 struct dma_regs {
     32 	uint32_t	ctl;			/* Control Register	*/
     33 #define	 DC_CTL_RST	0x04			/* Soft Reset		*/
     34 #define	 DC_CTL_MOD	0x02			/* set transfer dir	*/
     35 #define	 DC_CTL_ENB	0x01			/* set Enable		*/
     36 
     37 	uint32_t	stat;			/* Status Register 	*/
     38 #define	 DC_ST_TCZ	0x10			/* Transfer Count Zero 	*/
     39 #define	 DC_ST_INT	0x08			/* Interrupt 		*/
     40 #define	 DC_ST_MOD	0x02			/* monitor transfer dir	*/
     41 #define	 DC_ST_ENB	0x01			/* monitor Enable	*/
     42 
     43 	uint32_t	tcnt;			/* transfer counter	*/
     44 	uint32_t	tag;			/* Tag Register 	*/
     45 	uint32_t	offset;			/* Offset Register 	*/
     46 	uint32_t	mapent;			/* Map entry Register 	*/
     47 };
     48 
     49 #define DMAC_WAIT	__asm volatile ("nop; nop; nop; nop; nop; nop")
     50 
     51 #define DMAC_SEG_SIZE	0x1000 /* 4kbyte per DMA segment */
     52 #define DMAC_SEG_OFFSET	0x0fff
     53 #define DMAC_SEG_SHIFT	12
     54