si.c revision 1.15
1 /* $NetBSD: si.c,v 1.15 2004/09/04 11:30:39 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-dependent parts of the Sony CXD1180 41 * controller. The machine-independent parts are in ncr5380sbc.c. 42 * Written by Izumi Tsutsui. 43 * 44 * This code is based on arch/vax/vsa/ncr.c and sun3/dev/si.c 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: si.c,v 1.15 2004/09/04 11:30:39 tsutsui Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/buf.h> 54 55 #include <machine/cpu.h> 56 #include <m68k/cacheops.h> 57 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsiconf.h> 60 61 #include <dev/ic/ncr5380reg.h> 62 #include <dev/ic/ncr5380var.h> 63 64 #include <news68k/dev/hbvar.h> 65 #include <news68k/dev/dmac_0266.h> 66 67 #include "ioconf.h" 68 69 #define MIN_DMA_LEN 128 70 #define DMAC_BASE 0xe0e80000 /* XXX */ 71 #define SI_REGSIZE 8 72 73 struct si_dma_handle { 74 int dh_flags; 75 #define SIDH_BUSY 0x01 76 #define SIDH_OUT 0x02 77 caddr_t dh_addr; 78 int dh_len; 79 }; 80 81 struct si_softc { 82 struct ncr5380_softc ncr_sc; 83 int sc_options; 84 volatile struct dma_regs *sc_regs; 85 struct si_dma_handle ncr_dma[SCI_OPENINGS]; 86 }; 87 88 void si_attach(struct device *, struct device *, void *); 89 int si_match(struct device *, struct cfdata *, void *); 90 int si_intr(int); 91 92 void si_dma_alloc(struct ncr5380_softc *); 93 void si_dma_free(struct ncr5380_softc *); 94 void si_dma_setup(struct ncr5380_softc *); 95 void si_dma_start(struct ncr5380_softc *); 96 void si_dma_poll(struct ncr5380_softc *); 97 void si_dma_eop(struct ncr5380_softc *); 98 void si_dma_stop(struct ncr5380_softc *); 99 100 CFATTACH_DECL(si, sizeof(struct si_softc), 101 si_match, si_attach, NULL, NULL); 102 103 /* 104 * Options for disconnect/reselect, DMA, and interrupts. 105 * By default, allow disconnect/reselect on targets 4-6. 106 * Those are normally tapes that really need it enabled. 107 * The options are taken from the config file. 108 */ 109 #define SI_NO_DISCONNECT 0x000ff 110 #define SI_NO_PARITY_CHK 0x0ff00 111 #define SI_FORCE_POLLING 0x10000 112 #define SI_DISABLE_DMA 0x20000 113 114 int si_options = 0x0f; 115 116 117 int 118 si_match(parent, cf, aux) 119 struct device *parent; 120 struct cfdata *cf; 121 void *aux; 122 { 123 struct hb_attach_args *ha = aux; 124 int addr; 125 126 if (strcmp(ha->ha_name, "si")) 127 return 0; 128 129 addr = IIOV(ha->ha_address); 130 131 if (badaddr((void *)addr, 1)) 132 return 0; 133 134 ha->ha_size = SI_REGSIZE; 135 136 return 1; 137 } 138 139 /* 140 * Card attach function 141 */ 142 143 void 144 si_attach(parent, self, aux) 145 struct device *parent, *self; 146 void *aux; 147 { 148 struct si_softc *sc = (struct si_softc *)self; 149 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 150 struct cfdata *cf = self->dv_cfdata; 151 struct hb_attach_args *ha = aux; 152 153 ncr_sc->sc_regt = ha->ha_bust; 154 if (bus_space_map(ncr_sc->sc_regt, (bus_addr_t)ha->ha_address, 155 ha->ha_size, 0, &ncr_sc->sc_regh) != 0) { 156 printf("can't map device space\n"); 157 return; 158 } 159 160 /* Get options from config flags if specified. */ 161 if (cf->cf_flags) 162 sc->sc_options = cf->cf_flags; 163 else 164 sc->sc_options = si_options; 165 166 printf(": options=0x%x\n", sc->sc_options); 167 168 ncr_sc->sc_no_disconnect = (sc->sc_options & SI_NO_DISCONNECT); 169 ncr_sc->sc_parity_disable = (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 170 if (sc->sc_options & SI_FORCE_POLLING) 171 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 172 173 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 174 ncr_sc->sc_dma_alloc = si_dma_alloc; 175 ncr_sc->sc_dma_free = si_dma_free; 176 ncr_sc->sc_dma_poll = si_dma_poll; 177 ncr_sc->sc_dma_setup = si_dma_setup; 178 ncr_sc->sc_dma_start = si_dma_start; 179 ncr_sc->sc_dma_eop = si_dma_eop; 180 ncr_sc->sc_dma_stop = si_dma_stop; 181 182 if (sc->sc_options & SI_DISABLE_DMA) 183 /* Override this function pointer. */ 184 ncr_sc->sc_dma_alloc = NULL; 185 186 ncr_sc->sci_r0 = 0; 187 ncr_sc->sci_r1 = 1; 188 ncr_sc->sci_r2 = 2; 189 ncr_sc->sci_r3 = 3; 190 ncr_sc->sci_r4 = 4; 191 ncr_sc->sci_r5 = 5; 192 ncr_sc->sci_r6 = 6; 193 ncr_sc->sci_r7 = 7; 194 195 ncr_sc->sc_rev = NCR_VARIANT_CXD1180; 196 197 ncr_sc->sc_pio_in = ncr5380_pio_in; 198 ncr_sc->sc_pio_out = ncr5380_pio_out; 199 200 ncr_sc->sc_adapter.adapt_minphys = minphys; 201 ncr_sc->sc_channel.chan_id = 7; 202 203 /* soft reset DMAC */ 204 sc->sc_regs = (void *)IIOV(DMAC_BASE); 205 sc->sc_regs->ctl = DC_CTL_RST; 206 207 ncr5380_attach(ncr_sc); 208 } 209 210 int 211 si_intr(unit) 212 int unit; 213 { 214 struct si_softc *sc; 215 216 if (unit >= si_cd.cd_ndevs) 217 return 0; 218 219 sc = si_cd.cd_devs[unit]; 220 (void)ncr5380_intr(&sc->ncr_sc); 221 222 return 0; 223 } 224 225 /* 226 * DMA routines for news1700 machines 227 */ 228 229 void 230 si_dma_alloc(ncr_sc) 231 struct ncr5380_softc *ncr_sc; 232 { 233 struct si_softc *sc = (struct si_softc *)ncr_sc; 234 struct sci_req *sr = ncr_sc->sc_current; 235 struct scsipi_xfer *xs = sr->sr_xs; 236 struct si_dma_handle *dh; 237 int xlen, i; 238 239 #ifdef DIAGNOSTIC 240 if (sr->sr_dma_hand != NULL) 241 panic("si_dma_alloc: already have DMA handle"); 242 #endif 243 244 /* Polled transfers shouldn't allocate a DMA handle. */ 245 if (sr->sr_flags & SR_IMMED) 246 return; 247 248 xlen = ncr_sc->sc_datalen; 249 250 /* Make sure our caller checked sc_min_dma_len. */ 251 if (xlen < MIN_DMA_LEN) 252 panic("si_dma_alloc: len=0x%x", xlen); 253 254 /* 255 * Find free DMA handle. Guaranteed to find one since we 256 * have as many DMA handles as the driver has processes. 257 * (instances?) 258 */ 259 for (i = 0; i < SCI_OPENINGS; i++) { 260 if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0) 261 goto found; 262 } 263 panic("si_dma_alloc(): no free DMA handles"); 264 found: 265 dh = &sc->ncr_dma[i]; 266 dh->dh_flags = SIDH_BUSY; 267 dh->dh_addr = ncr_sc->sc_dataptr; 268 dh->dh_len = xlen; 269 270 /* Remember dest buffer parameters */ 271 if (xs->xs_control & XS_CTL_DATA_OUT) 272 dh->dh_flags |= SIDH_OUT; 273 274 sr->sr_dma_hand = dh; 275 } 276 277 void 278 si_dma_free(ncr_sc) 279 struct ncr5380_softc *ncr_sc; 280 { 281 struct sci_req *sr = ncr_sc->sc_current; 282 struct si_dma_handle *dh = sr->sr_dma_hand; 283 284 if (dh->dh_flags & SIDH_BUSY) 285 dh->dh_flags = 0; 286 else 287 printf("si_dma_free: free'ing unused buffer\n"); 288 289 sr->sr_dma_hand = NULL; 290 } 291 292 void 293 si_dma_setup(ncr_sc) 294 struct ncr5380_softc *ncr_sc; 295 { 296 297 /* Do nothing here */ 298 } 299 300 void 301 si_dma_start(ncr_sc) 302 struct ncr5380_softc *ncr_sc; 303 { 304 struct si_softc *sc = (struct si_softc *)ncr_sc; 305 volatile struct dma_regs *dmac = sc->sc_regs; 306 struct sci_req *sr = ncr_sc->sc_current; 307 struct si_dma_handle *dh = sr->sr_dma_hand; 308 u_int addr, offset, rest; 309 long len; 310 int i; 311 312 /* 313 * Set the news68k-specific registers. 314 */ 315 316 /* reset DMAC */ 317 dmac->ctl = DC_CTL_RST; 318 dmac->ctl = 0; 319 320 addr = (u_int)dh->dh_addr; 321 offset = addr & DMAC_SEG_OFFSET; 322 len = (u_int)dh->dh_len; 323 324 /* set DMA transfer length and offset of first segment */ 325 dmac->tcnt = len; 326 dmac->offset = offset; 327 328 /* set first DMA segment address */ 329 dmac->tag = 0; 330 dmac->mapent = kvtop((caddr_t)addr) >> DMAC_SEG_SHIFT; 331 rest = DMAC_SEG_SIZE - offset; 332 addr += rest; 333 len -= rest; 334 335 /* set all the rest segments */ 336 for (i = 1; len > 0; i++) { 337 dmac->tag = i; 338 dmac->mapent = kvtop((caddr_t)addr) >> DMAC_SEG_SHIFT; 339 len -= DMAC_SEG_SIZE; 340 addr += DMAC_SEG_SIZE; 341 } 342 /* terminate TAG */ 343 dmac->tag = 0; 344 345 /* 346 * Now from the 5380-internal DMA registers. 347 */ 348 if (dh->dh_flags & SIDH_OUT) { 349 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 350 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 351 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 352 | SCI_MODE_DMA); 353 354 /* set Dir */ 355 dmac->ctl = 0; 356 357 /* start DMA */ 358 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 359 dmac->ctl = DC_CTL_ENB; 360 } else { 361 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 362 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 363 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 364 | SCI_MODE_DMA); 365 366 /* set Dir */ 367 dmac->ctl = DC_CTL_MOD; 368 369 /* start DMA */ 370 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 371 dmac->ctl = DC_CTL_MOD | DC_CTL_ENB; 372 } 373 ncr_sc->sc_state |= NCR_DOINGDMA; 374 } 375 376 /* 377 * When? 378 */ 379 void 380 si_dma_poll(ncr_sc) 381 struct ncr5380_softc *ncr_sc; 382 { 383 384 printf("si_dma_poll\n"); 385 } 386 387 /* 388 * news68k (probably) does not use the EOP signal. 389 */ 390 void 391 si_dma_eop(ncr_sc) 392 struct ncr5380_softc *ncr_sc; 393 { 394 395 printf("si_dma_eop\n"); 396 } 397 398 void 399 si_dma_stop(ncr_sc) 400 struct ncr5380_softc *ncr_sc; 401 { 402 struct si_softc *sc = (struct si_softc *)ncr_sc; 403 volatile struct dma_regs *dmac = sc->sc_regs; 404 struct sci_req *sr = ncr_sc->sc_current; 405 struct si_dma_handle *dh = sr->sr_dma_hand; 406 int resid, ntrans, i; 407 408 /* check DMAC interrupt status */ 409 if ((dmac->stat & DC_ST_INT) == 0) { 410 #ifdef DEBUG 411 printf("si_dma_stop: no DMA interrupt"); 412 #endif 413 return; /* XXX */ 414 } 415 416 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 417 #ifdef DEBUG 418 printf("si_dma_stop: dma not running\n"); 419 #endif 420 return; 421 } 422 ncr_sc->sc_state &= ~NCR_DOINGDMA; 423 424 /* OK, have either phase mis-match or end of DMA. */ 425 /* Set an impossible phase to prevent data movement? */ 426 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_INVALID); 427 428 /* Note that timeout may have set the error flag. */ 429 if (ncr_sc->sc_state & NCR_ABORTING) 430 goto out; 431 432 /* 433 * Sometimes the FIFO buffer isn't drained when the 434 * interrupt is posted. Just loop here and hope that 435 * it will drain soon. 436 */ 437 for (i = 0; i < 200000; i++) { /* 2 sec */ 438 resid = dmac->tcnt; 439 if (resid == 0) 440 break; 441 DELAY(10); 442 } 443 444 if (resid) 445 printf("si_dma_stop: resid=0x%x\n", resid); 446 447 ntrans = dh->dh_len - resid; 448 449 ncr_sc->sc_dataptr += ntrans; 450 ncr_sc->sc_datalen -= ntrans; 451 452 if ((dh->dh_flags & SIDH_OUT) == 0) { 453 PCIA(); 454 } 455 456 out: 457 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 458 ~(SCI_MODE_DMA)); 459 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 460 } 461
Indexes created Thu Sep 25 16:09:42 GMT 2025