si.c revision 1.24
1 /* $NetBSD: si.c,v 1.24 2008/06/17 17:31:51 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * This file contains the machine-dependent parts of the Sony CXD1180 34 * controller. The machine-independent parts are in ncr5380sbc.c. 35 * Written by Izumi Tsutsui. 36 * 37 * This code is based on arch/vax/vsa/ncr.c and sun3/dev/si.c 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: si.c,v 1.24 2008/06/17 17:31:51 tsutsui Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <machine/cpu.h> 49 #include <m68k/cacheops.h> 50 51 #include <dev/scsipi/scsipi_all.h> 52 #include <dev/scsipi/scsiconf.h> 53 54 #include <dev/ic/ncr5380reg.h> 55 #include <dev/ic/ncr5380var.h> 56 57 #include <news68k/dev/hbvar.h> 58 #include <news68k/dev/dmac_0266.h> 59 60 #include "ioconf.h" 61 62 #define MIN_DMA_LEN 128 63 #define DMAC_BASE 0xe0e80000 /* XXX */ 64 #define SI_REGSIZE 8 65 66 struct si_softc { 67 struct ncr5380_softc ncr_sc; 68 int sc_options; 69 struct dma_regs *sc_regs; 70 int sc_xlen; 71 }; 72 73 static int si_match(device_t, cfdata_t, void *); 74 static void si_attach(device_t, device_t, void *); 75 int si_intr(int); 76 77 static void si_dma_alloc(struct ncr5380_softc *); 78 static void si_dma_free(struct ncr5380_softc *); 79 static void si_dma_start(struct ncr5380_softc *); 80 static void si_dma_poll(struct ncr5380_softc *); 81 static void si_dma_eop(struct ncr5380_softc *); 82 static void si_dma_stop(struct ncr5380_softc *); 83 84 static void si_dma_done(struct si_softc *); 85 86 CFATTACH_DECL_NEW(si, sizeof(struct si_softc), 87 si_match, si_attach, NULL, NULL); 88 89 /* 90 * Options for disconnect/reselect, DMA, and interrupts. 91 * By default, allow disconnect/reselect on targets 4-6. 92 * Those are normally tapes that really need it enabled. 93 * The options are taken from the config file. 94 */ 95 #define SI_NO_DISCONNECT 0x000ff 96 #define SI_NO_PARITY_CHK 0x0ff00 97 #define SI_FORCE_POLLING 0x10000 98 #define SI_DISABLE_DMA 0x20000 99 100 int si_options = 0x00; 101 102 103 static int 104 si_match(device_t parent, cfdata_t cf, void *aux) 105 { 106 struct hb_attach_args *ha = aux; 107 int addr; 108 109 if (strcmp(ha->ha_name, "si")) 110 return 0; 111 112 addr = IIOV(ha->ha_address); 113 114 if (badaddr((void *)addr, 1)) 115 return 0; 116 117 ha->ha_size = SI_REGSIZE; 118 119 return 1; 120 } 121 122 /* 123 * Card attach function 124 */ 125 126 static void 127 si_attach(device_t parent, device_t self, void *aux) 128 { 129 struct si_softc *sc = device_private(self); 130 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 131 struct cfdata *cf = device_cfdata(self); 132 struct hb_attach_args *ha = aux; 133 134 ncr_sc->sc_dev = self; 135 ncr_sc->sc_regt = ha->ha_bust; 136 if (bus_space_map(ncr_sc->sc_regt, (bus_addr_t)ha->ha_address, 137 ha->ha_size, 0, &ncr_sc->sc_regh) != 0) { 138 aprint_error(": can't map device space\n"); 139 return; 140 } 141 142 /* Get options from config flags if specified. */ 143 if (cf->cf_flags) 144 sc->sc_options = cf->cf_flags; 145 else 146 sc->sc_options = si_options; 147 148 if (sc->sc_options != 0) 149 aprint_normal(": options=0x%x", sc->sc_options); 150 aprint_normal("\n"); 151 152 ncr_sc->sc_no_disconnect = (sc->sc_options & SI_NO_DISCONNECT); 153 ncr_sc->sc_parity_disable = (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 154 if (sc->sc_options & SI_FORCE_POLLING) 155 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 156 157 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 158 ncr_sc->sc_dma_alloc = si_dma_alloc; 159 ncr_sc->sc_dma_free = si_dma_free; 160 ncr_sc->sc_dma_poll = si_dma_poll; 161 ncr_sc->sc_dma_start = si_dma_start; 162 ncr_sc->sc_dma_eop = si_dma_eop; 163 ncr_sc->sc_dma_stop = si_dma_stop; 164 165 if (sc->sc_options & SI_DISABLE_DMA) 166 /* Override this function pointer. */ 167 ncr_sc->sc_dma_alloc = NULL; 168 169 ncr_sc->sci_r0 = 0; 170 ncr_sc->sci_r1 = 1; 171 ncr_sc->sci_r2 = 2; 172 ncr_sc->sci_r3 = 3; 173 ncr_sc->sci_r4 = 4; 174 ncr_sc->sci_r5 = 5; 175 ncr_sc->sci_r6 = 6; 176 ncr_sc->sci_r7 = 7; 177 178 ncr_sc->sc_rev = NCR_VARIANT_CXD1180; 179 180 ncr_sc->sc_pio_in = ncr5380_pio_in; 181 ncr_sc->sc_pio_out = ncr5380_pio_out; 182 183 ncr_sc->sc_adapter.adapt_minphys = minphys; 184 ncr_sc->sc_channel.chan_id = 7; 185 186 /* soft reset DMAC */ 187 sc->sc_regs = (void *)IIOV(DMAC_BASE); 188 sc->sc_regs->ctl = DC_CTL_RST; 189 190 ncr5380_attach(ncr_sc); 191 } 192 193 int 194 si_intr(int unit) 195 { 196 struct si_softc *sc; 197 198 if (unit >= si_cd.cd_ndevs) 199 return 0; 200 201 sc = device_lookup_private(&si_cd, unit); /* XXX */ 202 (void)ncr5380_intr(&sc->ncr_sc); 203 204 return 0; 205 } 206 207 /* 208 * DMA routines for news1700 machines 209 */ 210 static void 211 si_dma_alloc(struct ncr5380_softc *ncr_sc) 212 { 213 struct sci_req *sr = ncr_sc->sc_current; 214 215 #ifdef DIAGNOSTIC 216 if (sr->sr_dma_hand != NULL) 217 panic("%s: DMA already in use", __func__); 218 #endif 219 220 /* 221 * On news68k, SCSI has its own DMAC so no need allocate it. 222 * Just mark that DMA is available. 223 */ 224 sr->sr_dma_hand = (void *)-1; 225 } 226 227 static void 228 si_dma_free(struct ncr5380_softc *ncr_sc) 229 { 230 struct sci_req *sr = ncr_sc->sc_current; 231 232 #ifdef DIAGNOSTIC 233 if (sr->sr_dma_hand == NULL) 234 panic("%s: DMA not in use", __func__); 235 #endif 236 237 sr->sr_dma_hand = NULL; 238 } 239 240 241 static void 242 si_dma_start(struct ncr5380_softc *ncr_sc) 243 { 244 struct si_softc *sc = (struct si_softc *)ncr_sc; 245 struct dma_regs *dmac = sc->sc_regs; 246 struct sci_req *sr = ncr_sc->sc_current; 247 u_int addr, offset, rest; 248 long len; 249 int i; 250 251 /* reset DMAC */ 252 dmac->ctl = DC_CTL_RST; 253 dmac->ctl = 0; 254 255 addr = (u_int)ncr_sc->sc_dataptr; 256 offset = addr & DMAC_SEG_OFFSET; 257 len = sc->sc_xlen = ncr_sc->sc_datalen; 258 259 /* set DMA transfer length */ 260 dmac->tcnt = (uint32_t)len; 261 262 /* set offset of first segment */ 263 dmac->offset = offset; 264 265 /* set first DMA segment address */ 266 dmac->tag = 0; 267 dmac->mapent = kvtop((void *)addr) >> DMAC_SEG_SHIFT; 268 rest = DMAC_SEG_SIZE - offset; 269 addr += rest; 270 len -= rest; 271 272 /* set all the rest segments */ 273 for (i = 1; len > 0; i++) { 274 dmac->tag = i; 275 dmac->mapent = kvtop((void *)addr) >> DMAC_SEG_SHIFT; 276 len -= DMAC_SEG_SIZE; 277 addr += DMAC_SEG_SIZE; 278 } 279 /* terminate TAG */ 280 dmac->tag = 0; 281 282 if (sr->sr_xs->xs_control & XS_CTL_DATA_OUT) { 283 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 284 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 285 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 286 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 287 288 /* set Dir */ 289 dmac->ctl = 0; 290 291 /* start DMA */ 292 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 293 dmac->ctl = DC_CTL_ENB; 294 } else { 295 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 296 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 297 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 298 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 299 300 /* set Dir */ 301 dmac->ctl = DC_CTL_MOD; 302 303 /* start DMA */ 304 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 305 dmac->ctl = DC_CTL_MOD | DC_CTL_ENB; 306 } 307 ncr_sc->sc_state |= NCR_DOINGDMA; 308 } 309 310 /* 311 * When? 312 */ 313 static void 314 si_dma_poll(struct ncr5380_softc *ncr_sc) 315 { 316 struct si_softc *sc = (struct si_softc *)ncr_sc; 317 struct dma_regs *dmac = sc->sc_regs; 318 int i; 319 320 #define POLL_TIMEOUT 100000 321 322 /* check DMAC interrupt status */ 323 for (i = 0; i < POLL_TIMEOUT; i++) { 324 if ((dmac->stat & DC_ST_INT) != 0) 325 break; 326 delay(10); 327 } 328 329 if (i == POLL_TIMEOUT) 330 printf("%s: DMA polling timeout\n", 331 device_xname(ncr_sc->sc_dev)); 332 333 si_dma_done(sc); 334 } 335 336 /* 337 * news68k (probably) does not use the EOP signal. 338 */ 339 static void 340 si_dma_eop(struct ncr5380_softc *ncr_sc) 341 { 342 343 printf("si_dma_eop\n"); 344 } 345 346 static void 347 si_dma_stop(struct ncr5380_softc *ncr_sc) 348 { 349 struct si_softc *sc = (struct si_softc *)ncr_sc; 350 struct dma_regs *dmac = sc->sc_regs; 351 352 /* check DMAC interrupt status */ 353 if ((dmac->stat & DC_ST_INT) == 0) { 354 #ifdef DEBUG 355 printf("%s: no DMA interrupt\n", __func__); 356 #endif 357 return; /* XXX */ 358 } 359 360 si_dma_done(sc); 361 } 362 363 static void 364 si_dma_done(struct si_softc *sc) 365 { 366 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 367 struct dma_regs *dmac = sc->sc_regs; 368 struct sci_req *sr = ncr_sc->sc_current; 369 int resid, ntrans; 370 371 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 372 #ifdef DEBUG 373 printf("%s: dma not running\n", __func__); 374 #endif 375 return; 376 } 377 ncr_sc->sc_state &= ~NCR_DOINGDMA; 378 379 /* stop DMAC */ 380 resid = dmac->tcnt; 381 dmac->ctl &= ~DC_CTL_ENB; 382 383 /* OK, have either phase mis-match or end of DMA. */ 384 /* Set an impossible phase to prevent data movement? */ 385 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_INVALID); 386 387 /* Note that timeout may have set the error flag. */ 388 if (ncr_sc->sc_state & NCR_ABORTING) 389 goto out; 390 391 #ifdef DEBUG 392 if (resid) 393 printf("%s: datalen = 0x%x, resid = 0x%x\n", 394 __func__, sc->sc_xlen, resid); 395 #endif 396 397 ntrans = sc->sc_xlen - resid; 398 399 ncr_sc->sc_dataptr += ntrans; 400 ncr_sc->sc_datalen -= ntrans; 401 402 if (sr->sr_xs->xs_control & XS_CTL_DATA_IN) { 403 /* flush data cache */ 404 PCIA(); 405 } 406 407 out: 408 /* reset DMAC */ 409 dmac->ctl = DC_CTL_RST; 410 dmac->ctl = 0; 411 412 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 413 ~(SCI_MODE_DMA | SCI_MODE_DMA_IE)); 414 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 415 } 416
Indexes created Fri Sep 26 20:09:58 GMT 2025