si.c revision 1.9
1 /* $NetBSD: si.c,v 1.9 2002/10/02 04:40:08 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-dependent parts of the Sony CXD1180 41 * controller. The machine-independent parts are in ncr5380sbc.c. 42 * Written by Izumi Tsutsui. 43 * 44 * This code is based on arch/vax/vsa/ncr.c and sun3/dev/si.c 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/buf.h> 51 52 #include <machine/cpu.h> 53 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsiconf.h> 56 57 #include <dev/ic/ncr5380reg.h> 58 #include <dev/ic/ncr5380var.h> 59 60 #include <news68k/dev/hbvar.h> 61 #include <news68k/dev/dmac_0266.h> 62 63 #define MIN_DMA_LEN 128 64 #define DMAC_BASE 0xe0e80000 /* XXX */ 65 66 struct si_dma_handle { 67 int dh_flags; 68 #define SIDH_BUSY 0x01 69 #define SIDH_OUT 0x02 70 caddr_t dh_addr; 71 int dh_len; 72 }; 73 74 struct si_softc { 75 struct ncr5380_softc ncr_sc; 76 int sc_options; 77 volatile struct dma_regs *sc_regs; 78 struct si_dma_handle ncr_dma[SCI_OPENINGS]; 79 }; 80 81 void si_attach __P((struct device *, struct device *, void *)); 82 int si_match __P((struct device *, struct cfdata *, void *)); 83 int si_intr __P((int)); 84 85 void si_dma_alloc __P((struct ncr5380_softc *)); 86 void si_dma_free __P((struct ncr5380_softc *)); 87 void si_dma_setup __P((struct ncr5380_softc *)); 88 void si_dma_start __P((struct ncr5380_softc *)); 89 void si_dma_poll __P((struct ncr5380_softc *)); 90 void si_dma_eop __P((struct ncr5380_softc *)); 91 void si_dma_stop __P((struct ncr5380_softc *)); 92 93 CFATTACH_DECL(si, sizeof(struct si_softc), 94 si_match, si_attach, NULL, NULL); 95 96 /* 97 * Options for disconnect/reselect, DMA, and interrupts. 98 * By default, allow disconnect/reselect on targets 4-6. 99 * Those are normally tapes that really need it enabled. 100 * The options are taken from the config file. 101 */ 102 #define SI_NO_DISCONNECT 0x000ff 103 #define SI_NO_PARITY_CHK 0x0ff00 104 #define SI_FORCE_POLLING 0x10000 105 #define SI_DISABLE_DMA 0x20000 106 107 int si_options = 0x0f; 108 109 110 int 111 si_match(parent, cf, aux) 112 struct device *parent; 113 struct cfdata *cf; 114 void *aux; 115 { 116 struct hb_attach_args *ha = aux; 117 int addr; 118 119 if (strcmp(ha->ha_name, "si")) 120 return 0; 121 122 addr = IIOV(ha->ha_address); 123 124 if (badaddr((void *)addr, 1)) 125 return 0; 126 127 return 1; 128 } 129 130 /* 131 * Card attach function 132 */ 133 134 void 135 si_attach(parent, self, aux) 136 struct device *parent, *self; 137 void *aux; 138 { 139 struct si_softc *sc = (struct si_softc *)self; 140 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 141 struct cfdata *cf = self->dv_cfdata; 142 struct hb_attach_args *ha = aux; 143 u_char *addr; 144 145 /* Get options from config flags if specified. */ 146 if (cf->cf_flags) 147 sc->sc_options = cf->cf_flags; 148 else 149 sc->sc_options = si_options; 150 151 printf(": options=0x%x\n", sc->sc_options); 152 153 ncr_sc->sc_no_disconnect = (sc->sc_options & SI_NO_DISCONNECT); 154 ncr_sc->sc_parity_disable = (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 155 if (sc->sc_options & SI_FORCE_POLLING) 156 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 157 158 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 159 ncr_sc->sc_dma_alloc = si_dma_alloc; 160 ncr_sc->sc_dma_free = si_dma_free; 161 ncr_sc->sc_dma_poll = si_dma_poll; 162 ncr_sc->sc_dma_setup = si_dma_setup; 163 ncr_sc->sc_dma_start = si_dma_start; 164 ncr_sc->sc_dma_eop = si_dma_eop; 165 ncr_sc->sc_dma_stop = si_dma_stop; 166 167 if (sc->sc_options & SI_DISABLE_DMA) 168 /* Override this function pointer. */ 169 ncr_sc->sc_dma_alloc = NULL; 170 171 addr = (u_char *)IIOV(ha->ha_address); 172 ncr_sc->sci_r0 = addr + 0; 173 ncr_sc->sci_r1 = addr + 1; 174 ncr_sc->sci_r2 = addr + 2; 175 ncr_sc->sci_r3 = addr + 3; 176 ncr_sc->sci_r4 = addr + 4; 177 ncr_sc->sci_r5 = addr + 5; 178 ncr_sc->sci_r6 = addr + 6; 179 ncr_sc->sci_r7 = addr + 7; 180 181 ncr_sc->sc_rev = NCR_VARIANT_CXD1180; 182 183 ncr_sc->sc_pio_in = ncr5380_pio_in; 184 ncr_sc->sc_pio_out = ncr5380_pio_out; 185 186 ncr_sc->sc_adapter.adapt_minphys = minphys; 187 ncr_sc->sc_channel.chan_id = 7; 188 189 /* soft reset DMAC */ 190 sc->sc_regs = (void *)IIOV(DMAC_BASE); 191 sc->sc_regs->ctl = DC_CTL_RST; 192 193 ncr5380_attach(ncr_sc); 194 } 195 196 int 197 si_intr(unit) 198 int unit; 199 { 200 struct si_softc *sc; 201 extern struct cfdriver si_cd; 202 203 if (unit >= si_cd.cd_ndevs) 204 return 0; 205 206 sc = si_cd.cd_devs[unit]; 207 (void)ncr5380_intr(&sc->ncr_sc); 208 209 return 0; 210 } 211 212 /* 213 * DMA routines for news1700 machines 214 */ 215 216 void 217 si_dma_alloc(ncr_sc) 218 struct ncr5380_softc *ncr_sc; 219 { 220 struct si_softc *sc = (struct si_softc *)ncr_sc; 221 struct sci_req *sr = ncr_sc->sc_current; 222 struct scsipi_xfer *xs = sr->sr_xs; 223 struct si_dma_handle *dh; 224 int xlen, i; 225 226 #ifdef DIAGNOSTIC 227 if (sr->sr_dma_hand != NULL) 228 panic("si_dma_alloc: already have DMA handle"); 229 #endif 230 231 /* Polled transfers shouldn't allocate a DMA handle. */ 232 if (sr->sr_flags & SR_IMMED) 233 return; 234 235 xlen = ncr_sc->sc_datalen; 236 237 /* Make sure our caller checked sc_min_dma_len. */ 238 if (xlen < MIN_DMA_LEN) 239 panic("si_dma_alloc: len=0x%x", xlen); 240 241 /* 242 * Find free DMA handle. Guaranteed to find one since we 243 * have as many DMA handles as the driver has processes. 244 * (instances?) 245 */ 246 for (i = 0; i < SCI_OPENINGS; i++) { 247 if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0) 248 goto found; 249 } 250 panic("si_dma_alloc(): no free DMA handles"); 251 found: 252 dh = &sc->ncr_dma[i]; 253 dh->dh_flags = SIDH_BUSY; 254 dh->dh_addr = ncr_sc->sc_dataptr; 255 dh->dh_len = xlen; 256 257 /* Remember dest buffer parameters */ 258 if (xs->xs_control & XS_CTL_DATA_OUT) 259 dh->dh_flags |= SIDH_OUT; 260 261 sr->sr_dma_hand = dh; 262 } 263 264 void 265 si_dma_free(ncr_sc) 266 struct ncr5380_softc *ncr_sc; 267 { 268 struct sci_req *sr = ncr_sc->sc_current; 269 struct si_dma_handle *dh = sr->sr_dma_hand; 270 271 if (dh->dh_flags & SIDH_BUSY) 272 dh->dh_flags = 0; 273 else 274 printf("si_dma_free: free'ing unused buffer\n"); 275 276 sr->sr_dma_hand = NULL; 277 } 278 279 void 280 si_dma_setup(ncr_sc) 281 struct ncr5380_softc *ncr_sc; 282 { 283 /* Do nothing here */ 284 } 285 286 void 287 si_dma_start(ncr_sc) 288 struct ncr5380_softc *ncr_sc; 289 { 290 struct si_softc *sc = (struct si_softc *)ncr_sc; 291 volatile struct dma_regs *dmac = sc->sc_regs; 292 struct sci_req *sr = ncr_sc->sc_current; 293 struct si_dma_handle *dh = sr->sr_dma_hand; 294 u_int addr, offset, rest; 295 long len; 296 int i; 297 298 /* 299 * Set the news68k-specific registers. 300 */ 301 302 /* reset DMAC */ 303 dmac->ctl = DC_CTL_RST; 304 dmac->ctl = 0; 305 306 addr = (u_int)dh->dh_addr; 307 offset = addr & DMAC_SEG_OFFSET; 308 len = (u_int)dh->dh_len; 309 310 /* set DMA transfer length and offset of first segment */ 311 dmac->tcnt = len; 312 dmac->offset = offset; 313 314 /* set first DMA segment address */ 315 dmac->tag = 0; 316 dmac->mapent = kvtop((caddr_t)addr) >> DMAC_SEG_SHIFT; 317 rest = DMAC_SEG_SIZE - offset; 318 addr += rest; 319 len -= rest; 320 321 /* set all the rest segments */ 322 for (i = 1; len > 0; i++) { 323 dmac->tag = i; 324 dmac->mapent = kvtop((caddr_t)addr) >> DMAC_SEG_SHIFT; 325 len -= DMAC_SEG_SIZE; 326 addr += DMAC_SEG_SIZE; 327 } 328 /* terminate TAG */ 329 dmac->tag = 0; 330 331 /* 332 * Now from the 5380-internal DMA registers. 333 */ 334 if (dh->dh_flags & SIDH_OUT) { 335 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 336 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 337 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 338 | SCI_MODE_DMA); 339 340 /* set Dir */ 341 dmac->ctl = 0; 342 343 /* start DMA */ 344 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 345 dmac->ctl = DC_CTL_ENB; 346 } else { 347 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 348 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 349 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 350 | SCI_MODE_DMA); 351 352 /* set Dir */ 353 dmac->ctl = DC_CTL_MOD; 354 355 /* start DMA */ 356 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 357 dmac->ctl = DC_CTL_MOD | DC_CTL_ENB; 358 } 359 ncr_sc->sc_state |= NCR_DOINGDMA; 360 } 361 362 /* 363 * When? 364 */ 365 void 366 si_dma_poll(ncr_sc) 367 struct ncr5380_softc *ncr_sc; 368 { 369 printf("si_dma_poll\n"); 370 } 371 372 /* 373 * news68k (probabry) does not use the EOP signal. 374 */ 375 void 376 si_dma_eop(ncr_sc) 377 struct ncr5380_softc *ncr_sc; 378 { 379 printf("si_dma_eop\n"); 380 } 381 382 void 383 si_dma_stop(ncr_sc) 384 struct ncr5380_softc *ncr_sc; 385 { 386 struct si_softc *sc = (struct si_softc *)ncr_sc; 387 volatile struct dma_regs *dmac = sc->sc_regs; 388 struct sci_req *sr = ncr_sc->sc_current; 389 struct si_dma_handle *dh = sr->sr_dma_hand; 390 int resid, ntrans, i; 391 392 /* check DMAC interrupt status */ 393 if ((dmac->stat & DC_ST_INT) == 0) { 394 #ifdef DEBUG 395 printf("si_dma_stop: no DMA interrupt"); 396 #endif 397 return; /* XXX */ 398 } 399 400 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 401 #ifdef DEBUG 402 printf("si_dma_stop: dma not running\n"); 403 #endif 404 return; 405 } 406 ncr_sc->sc_state &= ~NCR_DOINGDMA; 407 408 /* OK, have either phase mis-match or end of DMA. */ 409 /* Set an impossible phase to prevent data movement? */ 410 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_INVALID); 411 412 /* Note that timeout may have set the error flag. */ 413 if (ncr_sc->sc_state & NCR_ABORTING) 414 goto out; 415 416 /* 417 * Sometimes the FIFO buffer isn't drained when the 418 * interrupt is posted. Just loop here and hope that 419 * it will drain soon. 420 */ 421 for (i = 0; i < 200000; i++) { /* 2 sec */ 422 resid = dmac->tcnt; 423 if (resid == 0) 424 break; 425 DELAY(10); 426 } 427 428 if (resid) 429 printf("si_dma_stop: resid=0x%x\n", resid); 430 431 ntrans = dh->dh_len - resid; 432 433 ncr_sc->sc_dataptr += ntrans; 434 ncr_sc->sc_datalen -= ntrans; 435 436 if ((dh->dh_flags & SIDH_OUT) == 0) { 437 PCIA(); 438 } 439 440 out: 441 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 442 ~(SCI_MODE_DMA)); 443 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 444 } 445
Indexes created Thu Sep 25 08:09:54 GMT 2025