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zs.c revision 1.6.8.6
      1  1.6.8.6  thorpej /*	$NetBSD: zs.c,v 1.6.8.6 2003/01/15 18:22:28 thorpej Exp $	*/
      2  1.6.8.2  nathanw 
      3  1.6.8.2  nathanw /*-
      4  1.6.8.2  nathanw  * Copyright (c) 1996 The NetBSD Foundation, Inc.
      5  1.6.8.2  nathanw  * All rights reserved.
      6  1.6.8.2  nathanw  *
      7  1.6.8.2  nathanw  * This code is derived from software contributed to The NetBSD Foundation
      8  1.6.8.2  nathanw  * by Gordon W. Ross.
      9  1.6.8.2  nathanw  *
     10  1.6.8.2  nathanw  * Redistribution and use in source and binary forms, with or without
     11  1.6.8.2  nathanw  * modification, are permitted provided that the following conditions
     12  1.6.8.2  nathanw  * are met:
     13  1.6.8.2  nathanw  * 1. Redistributions of source code must retain the above copyright
     14  1.6.8.2  nathanw  *    notice, this list of conditions and the following disclaimer.
     15  1.6.8.2  nathanw  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.6.8.2  nathanw  *    notice, this list of conditions and the following disclaimer in the
     17  1.6.8.2  nathanw  *    documentation and/or other materials provided with the distribution.
     18  1.6.8.2  nathanw  * 3. All advertising materials mentioning features or use of this software
     19  1.6.8.2  nathanw  *    must display the following acknowledgement:
     20  1.6.8.2  nathanw  *        This product includes software developed by the NetBSD
     21  1.6.8.2  nathanw  *        Foundation, Inc. and its contributors.
     22  1.6.8.2  nathanw  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.6.8.2  nathanw  *    contributors may be used to endorse or promote products derived
     24  1.6.8.2  nathanw  *    from this software without specific prior written permission.
     25  1.6.8.2  nathanw  *
     26  1.6.8.2  nathanw  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.6.8.2  nathanw  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.6.8.2  nathanw  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.6.8.2  nathanw  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.6.8.2  nathanw  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.6.8.2  nathanw  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.6.8.2  nathanw  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.6.8.2  nathanw  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.6.8.2  nathanw  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.6.8.2  nathanw  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.6.8.2  nathanw  * POSSIBILITY OF SUCH DAMAGE.
     37  1.6.8.2  nathanw  */
     38  1.6.8.2  nathanw 
     39  1.6.8.2  nathanw /*
     40  1.6.8.2  nathanw  * Zilog Z8530 Dual UART driver (machine-dependent part)
     41  1.6.8.2  nathanw  *
     42  1.6.8.2  nathanw  * Runs two serial lines per chip using slave drivers.
     43  1.6.8.2  nathanw  * Plain tty/async lines use the zs_async slave.
     44  1.6.8.2  nathanw  */
     45  1.6.8.2  nathanw 
     46  1.6.8.2  nathanw /*
     47  1.6.8.2  nathanw  * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c
     48  1.6.8.2  nathanw  */
     49  1.6.8.2  nathanw 
     50  1.6.8.2  nathanw #include "opt_ddb.h"
     51  1.6.8.2  nathanw 
     52  1.6.8.2  nathanw #include <sys/param.h>
     53  1.6.8.2  nathanw #include <sys/systm.h>
     54  1.6.8.2  nathanw #include <sys/conf.h>
     55  1.6.8.2  nathanw #include <sys/device.h>
     56  1.6.8.2  nathanw #include <sys/tty.h>
     57  1.6.8.2  nathanw 
     58  1.6.8.2  nathanw #include <machine/cpu.h>
     59  1.6.8.2  nathanw #include <machine/z8530var.h>
     60  1.6.8.2  nathanw 
     61  1.6.8.2  nathanw #include <dev/cons.h>
     62  1.6.8.2  nathanw #include <dev/ic/z8530reg.h>
     63  1.6.8.2  nathanw 
     64  1.6.8.2  nathanw #include <news68k/dev/hbvar.h>
     65  1.6.8.2  nathanw 
     66  1.6.8.4  thorpej int  zs_getc(void *);
     67  1.6.8.4  thorpej void zs_putc(void *, int);
     68  1.6.8.2  nathanw 
     69  1.6.8.2  nathanw /*
     70  1.6.8.2  nathanw  * Some warts needed by z8530tty.c -
     71  1.6.8.2  nathanw  * The default parity REALLY needs to be the same as the PROM uses,
     72  1.6.8.2  nathanw  * or you can not see messages done with printf during boot-up...
     73  1.6.8.2  nathanw  */
     74  1.6.8.2  nathanw int zs_def_cflag = (CREAD | CS8 | HUPCL);
     75  1.6.8.2  nathanw 
     76  1.6.8.2  nathanw /*
     77  1.6.8.2  nathanw  * The news68k machines use three different clocks for the ZS chips.
     78  1.6.8.2  nathanw  */
     79  1.6.8.2  nathanw #define NPCLK	3
     80  1.6.8.2  nathanw #define PCLK0	(9600 * 416)	/*  news1700: 3.9936MHz */
     81  1.6.8.2  nathanw #define PCLK1	(9600 * 512)	/*  news1200: 4.9152MHz */
     82  1.6.8.2  nathanw #define PCLK2	(9600 * 384)	/*  external: 3.6864MHz */
     83  1.6.8.2  nathanw 
     84  1.6.8.2  nathanw static const u_int pclk[NPCLK] = {
     85  1.6.8.2  nathanw 	PCLK0,
     86  1.6.8.2  nathanw 	PCLK1,
     87  1.6.8.2  nathanw 	PCLK2,
     88  1.6.8.2  nathanw };
     89  1.6.8.2  nathanw 
     90  1.6.8.2  nathanw /*
     91  1.6.8.2  nathanw  * Define interrupt levels.
     92  1.6.8.2  nathanw  */
     93  1.6.8.2  nathanw #define ZSHARD_PRI 5
     94  1.6.8.2  nathanw #define ZS_IVECT 64
     95  1.6.8.2  nathanw 
     96  1.6.8.2  nathanw #define ZS_DELAY() /* delay(2) */
     97  1.6.8.2  nathanw 
     98  1.6.8.2  nathanw /* The layout of this is hardware-dependent (padding, order). */
     99  1.6.8.2  nathanw struct zschan {
    100  1.6.8.2  nathanw 	volatile u_char	zc_csr;		/* ctrl,status, and indirect access */
    101  1.6.8.2  nathanw 	volatile u_char	zc_data;	/* data */
    102  1.6.8.2  nathanw };
    103  1.6.8.2  nathanw struct zsdevice {
    104  1.6.8.2  nathanw 	/* Yes, they are backwards. */
    105  1.6.8.2  nathanw 	struct	zschan zs_chan_b;
    106  1.6.8.2  nathanw 	struct	zschan zs_chan_a;
    107  1.6.8.2  nathanw };
    108  1.6.8.2  nathanw 
    109  1.6.8.2  nathanw static u_char zs_sir;
    110  1.6.8.2  nathanw 
    111  1.6.8.2  nathanw /* Default speed for all channels */
    112  1.6.8.2  nathanw static int zs_defspeed = 9600;
    113  1.6.8.2  nathanw 
    114  1.6.8.2  nathanw /* console status from cninit */
    115  1.6.8.2  nathanw static struct zs_chanstate zs_conschan_store;
    116  1.6.8.2  nathanw static struct zs_chanstate *zs_conschan;
    117  1.6.8.2  nathanw static struct zschan *zc_cons;
    118  1.6.8.2  nathanw 
    119  1.6.8.2  nathanw static u_char zs_init_reg[16] = {
    120  1.6.8.2  nathanw 	0,	/* 0: CMD (reset, etc.) */
    121  1.6.8.2  nathanw 	0,	/* 1: No interrupts yet. */
    122  1.6.8.2  nathanw 	ZS_IVECT,	/* IVECT */
    123  1.6.8.2  nathanw 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
    124  1.6.8.2  nathanw 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
    125  1.6.8.2  nathanw 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
    126  1.6.8.2  nathanw 	0,	/* 6: TXSYNC/SYNCLO */
    127  1.6.8.2  nathanw 	0,	/* 7: RXSYNC/SYNCHI */
    128  1.6.8.2  nathanw 	0,	/* 8: alias for data port */
    129  1.6.8.2  nathanw 	ZSWR9_MASTER_IE,
    130  1.6.8.2  nathanw 	0,	/*10: Misc. TX/RX control bits */
    131  1.6.8.2  nathanw 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
    132  1.6.8.2  nathanw 	BPS_TO_TCONST((PCLK0/16), 9600), /*12: BAUDLO (default=9600) */
    133  1.6.8.2  nathanw 	0,			/*13: BAUDHI (default=9600) */
    134  1.6.8.2  nathanw 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
    135  1.6.8.2  nathanw 	ZSWR15_BREAK_IE,
    136  1.6.8.2  nathanw };
    137  1.6.8.2  nathanw 
    138  1.6.8.2  nathanw 
    139  1.6.8.2  nathanw /****************************************************************
    140  1.6.8.2  nathanw  * Autoconfig
    141  1.6.8.2  nathanw  ****************************************************************/
    142  1.6.8.2  nathanw 
    143  1.6.8.2  nathanw /* Definition of the driver for autoconfig. */
    144  1.6.8.4  thorpej static int  zs_match(struct device *, struct cfdata *, void *);
    145  1.6.8.4  thorpej static void zs_attach(struct device *, struct device *, void *);
    146  1.6.8.4  thorpej static int  zs_print(void *, const char *name);
    147  1.6.8.2  nathanw 
    148  1.6.8.3  nathanw CFATTACH_DECL(zsc, sizeof(struct zsc_softc),
    149  1.6.8.3  nathanw     zs_match, zs_attach, NULL, NULL);
    150  1.6.8.2  nathanw 
    151  1.6.8.2  nathanw extern struct cfdriver zsc_cd;
    152  1.6.8.2  nathanw 
    153  1.6.8.4  thorpej static int zshard(void *);
    154  1.6.8.4  thorpej void zssoft(void *);
    155  1.6.8.2  nathanw #if 0
    156  1.6.8.4  thorpej static int zs_get_speed(struct zs_chanstate *);
    157  1.6.8.2  nathanw #endif
    158  1.6.8.2  nathanw 
    159  1.6.8.2  nathanw /*
    160  1.6.8.2  nathanw  * Is the zs chip present?
    161  1.6.8.2  nathanw  */
    162  1.6.8.2  nathanw static int
    163  1.6.8.2  nathanw zs_match(parent, cf, aux)
    164  1.6.8.2  nathanw 	struct device *parent;
    165  1.6.8.2  nathanw 	struct cfdata *cf;
    166  1.6.8.2  nathanw 	void *aux;
    167  1.6.8.2  nathanw {
    168  1.6.8.2  nathanw 	struct hb_attach_args *ha = aux;
    169  1.6.8.2  nathanw 	u_int addr;
    170  1.6.8.2  nathanw 
    171  1.6.8.2  nathanw 	if (strcmp(ha->ha_name, "zsc"))
    172  1.6.8.2  nathanw 		return 0;
    173  1.6.8.2  nathanw 
    174  1.6.8.2  nathanw 	/* XXX no default address */
    175  1.6.8.6  thorpej 	if (ha->ha_address == (u_int)-1)
    176  1.6.8.2  nathanw 		return 0;
    177  1.6.8.2  nathanw 
    178  1.6.8.2  nathanw 	addr = IIOV(ha->ha_address);
    179  1.6.8.2  nathanw 	/* This returns -1 on a fault (bus error). */
    180  1.6.8.2  nathanw 	if (badaddr((void *)addr, 1))
    181  1.6.8.2  nathanw 		return 0;
    182  1.6.8.2  nathanw 
    183  1.6.8.2  nathanw 	return 1;
    184  1.6.8.2  nathanw }
    185  1.6.8.2  nathanw 
    186  1.6.8.2  nathanw /*
    187  1.6.8.2  nathanw  * Attach a found zs.
    188  1.6.8.2  nathanw  */
    189  1.6.8.2  nathanw static void
    190  1.6.8.2  nathanw zs_attach(parent, self, aux)
    191  1.6.8.2  nathanw 	struct device *parent;
    192  1.6.8.2  nathanw 	struct device *self;
    193  1.6.8.2  nathanw 	void *aux;
    194  1.6.8.2  nathanw {
    195  1.6.8.2  nathanw 	struct zsc_softc *zsc = (void *) self;
    196  1.6.8.2  nathanw 	struct cfdata *cf = self->dv_cfdata;
    197  1.6.8.2  nathanw 	struct hb_attach_args *ha = aux;
    198  1.6.8.2  nathanw 	struct zsc_attach_args zsc_args;
    199  1.6.8.2  nathanw 	struct zsdevice *zs;
    200  1.6.8.2  nathanw 	struct zschan *zc;
    201  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    202  1.6.8.2  nathanw 	int s, channel, clk;
    203  1.6.8.2  nathanw 
    204  1.6.8.2  nathanw 	zs = (void *)IIOV(ha->ha_address);
    205  1.6.8.2  nathanw 
    206  1.6.8.2  nathanw 	clk = cf->cf_flags;
    207  1.6.8.2  nathanw 	if (clk < 0 || clk >= NPCLK)
    208  1.6.8.2  nathanw 		clk = 0;
    209  1.6.8.2  nathanw 
    210  1.6.8.2  nathanw 	printf("\n");
    211  1.6.8.2  nathanw 
    212  1.6.8.2  nathanw 	/*
    213  1.6.8.2  nathanw 	 * Initialize software state for each channel.
    214  1.6.8.2  nathanw 	 */
    215  1.6.8.2  nathanw 	for (channel = 0; channel < 2; channel++) {
    216  1.6.8.2  nathanw 		zsc_args.channel = channel;
    217  1.6.8.2  nathanw 		cs = &zsc->zsc_cs_store[channel];
    218  1.6.8.2  nathanw 		zsc->zsc_cs[channel] = cs;
    219  1.6.8.2  nathanw 		zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b;
    220  1.6.8.2  nathanw 
    221  1.6.8.2  nathanw 		if (ha->ha_vect != -1)
    222  1.6.8.2  nathanw 			zs_init_reg[2] = ha->ha_vect;
    223  1.6.8.2  nathanw 
    224  1.6.8.2  nathanw 		if (zc == zc_cons) {
    225  1.6.8.2  nathanw 			memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
    226  1.6.8.2  nathanw 			zs_conschan = cs;
    227  1.6.8.2  nathanw 			zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
    228  1.6.8.2  nathanw 		} else {
    229  1.6.8.2  nathanw 			cs->cs_reg_csr  = &zc->zc_csr;
    230  1.6.8.2  nathanw 			cs->cs_reg_data = &zc->zc_data;
    231  1.6.8.2  nathanw 			memcpy(cs->cs_creg, zs_init_reg, 16);
    232  1.6.8.2  nathanw 			memcpy(cs->cs_preg, zs_init_reg, 16);
    233  1.6.8.2  nathanw 			cs->cs_defspeed = zs_defspeed;
    234  1.6.8.2  nathanw 			zsc_args.hwflags = 0;
    235  1.6.8.2  nathanw 		}
    236  1.6.8.2  nathanw 
    237  1.6.8.2  nathanw 		cs->cs_defcflag = zs_def_cflag;
    238  1.6.8.2  nathanw 
    239  1.6.8.2  nathanw 		cs->cs_channel = channel;
    240  1.6.8.2  nathanw 		cs->cs_private = NULL;
    241  1.6.8.2  nathanw 		cs->cs_ops = &zsops_null;
    242  1.6.8.2  nathanw 		cs->cs_brg_clk = pclk[clk] / 16;
    243  1.6.8.2  nathanw 
    244  1.6.8.2  nathanw 		/* Make these correspond to cs_defcflag (-crtscts) */
    245  1.6.8.2  nathanw 		cs->cs_rr0_dcd = ZSRR0_DCD;
    246  1.6.8.2  nathanw 		cs->cs_rr0_cts = 0;
    247  1.6.8.2  nathanw 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
    248  1.6.8.2  nathanw 		cs->cs_wr5_rts = 0;
    249  1.6.8.2  nathanw 
    250  1.6.8.2  nathanw 		/*
    251  1.6.8.2  nathanw 		 * Clear the master interrupt enable.
    252  1.6.8.2  nathanw 		 * The INTENA is common to both channels,
    253  1.6.8.2  nathanw 		 * so just do it on the A channel.
    254  1.6.8.2  nathanw 		 */
    255  1.6.8.2  nathanw 		if (channel == 0) {
    256  1.6.8.2  nathanw 			s = splhigh();
    257  1.6.8.2  nathanw 			zs_write_reg(cs, 9, 0);
    258  1.6.8.2  nathanw 			splx(s);
    259  1.6.8.2  nathanw 		}
    260  1.6.8.2  nathanw 
    261  1.6.8.2  nathanw 		/*
    262  1.6.8.2  nathanw 		 * Look for a child driver for this channel.
    263  1.6.8.2  nathanw 		 * The child attach will setup the hardware.
    264  1.6.8.2  nathanw 		 */
    265  1.6.8.2  nathanw 		if (!config_found(self, (void *)&zsc_args, zs_print)) {
    266  1.6.8.2  nathanw 			/* No sub-driver.  Just reset it. */
    267  1.6.8.2  nathanw 			u_char reset = (channel == 0) ?
    268  1.6.8.2  nathanw 				ZSWR9_A_RESET : ZSWR9_B_RESET;
    269  1.6.8.2  nathanw 			s = splhigh();
    270  1.6.8.2  nathanw 			zs_write_reg(cs,  9, reset);
    271  1.6.8.2  nathanw 			splx(s);
    272  1.6.8.2  nathanw 		}
    273  1.6.8.2  nathanw 	}
    274  1.6.8.2  nathanw 
    275  1.6.8.2  nathanw 	/*
    276  1.6.8.2  nathanw 	 * Now safe to install interrupt handlers.
    277  1.6.8.2  nathanw 	 */
    278  1.6.8.2  nathanw 	hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc);
    279  1.6.8.2  nathanw 
    280  1.6.8.2  nathanw 	/*
    281  1.6.8.2  nathanw 	 * Set the master interrupt enable and interrupt vector.
    282  1.6.8.2  nathanw 	 * (common to both channels, do it on A)
    283  1.6.8.2  nathanw 	 */
    284  1.6.8.2  nathanw 	cs = zsc->zsc_cs[0];
    285  1.6.8.2  nathanw 	s = splhigh();
    286  1.6.8.2  nathanw 	/* interrupt vector */
    287  1.6.8.2  nathanw 	zs_write_reg(cs, 2, zs_init_reg[2]);
    288  1.6.8.2  nathanw 	/* master interrupt control (enable) */
    289  1.6.8.2  nathanw 	zs_write_reg(cs, 9, zs_init_reg[9]);
    290  1.6.8.2  nathanw 	splx(s);
    291  1.6.8.2  nathanw 
    292  1.6.8.2  nathanw 	if (zs_sir == 0)
    293  1.6.8.2  nathanw 		zs_sir = allocate_sir(zssoft, zsc);
    294  1.6.8.2  nathanw }
    295  1.6.8.2  nathanw 
    296  1.6.8.2  nathanw static int
    297  1.6.8.2  nathanw zs_print(aux, name)
    298  1.6.8.2  nathanw 	void *aux;
    299  1.6.8.2  nathanw 	const char *name;
    300  1.6.8.2  nathanw {
    301  1.6.8.2  nathanw 	struct zsc_attach_args *args = aux;
    302  1.6.8.2  nathanw 
    303  1.6.8.2  nathanw 	if (name != NULL)
    304  1.6.8.5  thorpej 		aprint_normal("%s: ", name);
    305  1.6.8.2  nathanw 
    306  1.6.8.2  nathanw 	if (args->channel != -1)
    307  1.6.8.5  thorpej 		aprint_normal(" channel %d", args->channel);
    308  1.6.8.2  nathanw 
    309  1.6.8.2  nathanw 	return UNCONF;
    310  1.6.8.2  nathanw }
    311  1.6.8.2  nathanw 
    312  1.6.8.2  nathanw /*
    313  1.6.8.2  nathanw  * For news68k-port, we don't use autovectored interrupt.
    314  1.6.8.2  nathanw  * We do not need to look at all of the zs chips.
    315  1.6.8.2  nathanw  */
    316  1.6.8.2  nathanw static int
    317  1.6.8.2  nathanw zshard(arg)
    318  1.6.8.2  nathanw 	void *arg;
    319  1.6.8.2  nathanw {
    320  1.6.8.2  nathanw 	struct zsc_softc *zsc = arg;
    321  1.6.8.2  nathanw 	int rval;
    322  1.6.8.2  nathanw 
    323  1.6.8.2  nathanw 	rval = zsc_intr_hard(zsc);
    324  1.6.8.2  nathanw 
    325  1.6.8.2  nathanw 	/* We are at splzs here, so no need to lock. */
    326  1.6.8.2  nathanw 	if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) {
    327  1.6.8.2  nathanw 		setsoftint(zs_sir);
    328  1.6.8.2  nathanw 	}
    329  1.6.8.2  nathanw 
    330  1.6.8.2  nathanw 	return (rval);
    331  1.6.8.2  nathanw }
    332  1.6.8.2  nathanw 
    333  1.6.8.2  nathanw /*
    334  1.6.8.2  nathanw  * Shared among the all chips. We have to look at all of them.
    335  1.6.8.2  nathanw  */
    336  1.6.8.2  nathanw void
    337  1.6.8.2  nathanw zssoft(arg)
    338  1.6.8.2  nathanw 	void *arg;
    339  1.6.8.2  nathanw {
    340  1.6.8.2  nathanw 	struct zsc_softc *zsc;
    341  1.6.8.2  nathanw 	int s, unit;
    342  1.6.8.2  nathanw 
    343  1.6.8.2  nathanw 	/* Make sure we call the tty layer at spltty. */
    344  1.6.8.2  nathanw 	s = spltty();
    345  1.6.8.2  nathanw 	for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
    346  1.6.8.2  nathanw 		zsc = zsc_cd.cd_devs[unit];
    347  1.6.8.2  nathanw 		if (zsc == NULL)
    348  1.6.8.2  nathanw 			continue;
    349  1.6.8.2  nathanw 		(void) zsc_intr_soft(zsc);
    350  1.6.8.2  nathanw 	}
    351  1.6.8.2  nathanw 	splx(s);
    352  1.6.8.2  nathanw }
    353  1.6.8.2  nathanw 
    354  1.6.8.2  nathanw /*
    355  1.6.8.2  nathanw  * Compute the current baud rate given a ZS channel.
    356  1.6.8.2  nathanw  */
    357  1.6.8.2  nathanw #if 0
    358  1.6.8.2  nathanw static int
    359  1.6.8.2  nathanw zs_get_speed(cs)
    360  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    361  1.6.8.2  nathanw {
    362  1.6.8.2  nathanw 	int tconst;
    363  1.6.8.2  nathanw 
    364  1.6.8.2  nathanw 	tconst = zs_read_reg(cs, 12);
    365  1.6.8.2  nathanw 	tconst |= zs_read_reg(cs, 13) << 8;
    366  1.6.8.2  nathanw 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
    367  1.6.8.2  nathanw }
    368  1.6.8.2  nathanw #endif
    369  1.6.8.2  nathanw 
    370  1.6.8.2  nathanw /*
    371  1.6.8.2  nathanw  * MD functions for setting the baud rate and control modes.
    372  1.6.8.2  nathanw  */
    373  1.6.8.2  nathanw int
    374  1.6.8.2  nathanw zs_set_speed(cs, bps)
    375  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    376  1.6.8.2  nathanw 	int bps;	/* bits per second */
    377  1.6.8.2  nathanw {
    378  1.6.8.2  nathanw 	int tconst, real_bps;
    379  1.6.8.2  nathanw 
    380  1.6.8.2  nathanw 	if (bps == 0)
    381  1.6.8.2  nathanw 		return (0);
    382  1.6.8.2  nathanw 
    383  1.6.8.2  nathanw #ifdef	DIAGNOSTIC
    384  1.6.8.2  nathanw 	if (cs->cs_brg_clk == 0)
    385  1.6.8.2  nathanw 		panic("zs_set_speed");
    386  1.6.8.2  nathanw #endif
    387  1.6.8.2  nathanw 
    388  1.6.8.2  nathanw 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
    389  1.6.8.2  nathanw 	if (tconst < 0)
    390  1.6.8.2  nathanw 		return (EINVAL);
    391  1.6.8.2  nathanw 
    392  1.6.8.2  nathanw 	/* Convert back to make sure we can do it. */
    393  1.6.8.2  nathanw 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
    394  1.6.8.2  nathanw 
    395  1.6.8.2  nathanw 	/* XXX - Allow some tolerance here? */
    396  1.6.8.2  nathanw 	if (real_bps != bps)
    397  1.6.8.2  nathanw 		return (EINVAL);
    398  1.6.8.2  nathanw 
    399  1.6.8.2  nathanw 	cs->cs_preg[12] = tconst;
    400  1.6.8.2  nathanw 	cs->cs_preg[13] = tconst >> 8;
    401  1.6.8.2  nathanw 
    402  1.6.8.2  nathanw 	/* Caller will stuff the pending registers. */
    403  1.6.8.2  nathanw 	return (0);
    404  1.6.8.2  nathanw }
    405  1.6.8.2  nathanw 
    406  1.6.8.2  nathanw int
    407  1.6.8.2  nathanw zs_set_modes(cs, cflag)
    408  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    409  1.6.8.2  nathanw 	int cflag;	/* bits per second */
    410  1.6.8.2  nathanw {
    411  1.6.8.2  nathanw 	int s;
    412  1.6.8.2  nathanw 
    413  1.6.8.2  nathanw 	/*
    414  1.6.8.2  nathanw 	 * Output hardware flow control on the chip is horrendous:
    415  1.6.8.2  nathanw 	 * if carrier detect drops, the receiver is disabled, and if
    416  1.6.8.2  nathanw 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
    417  1.6.8.2  nathanw 	 * Therefore, NEVER set the HFC bit, and instead use the
    418  1.6.8.2  nathanw 	 * status interrupt to detect CTS changes.
    419  1.6.8.2  nathanw 	 */
    420  1.6.8.2  nathanw 	s = splzs();
    421  1.6.8.2  nathanw 	cs->cs_rr0_pps = 0;
    422  1.6.8.2  nathanw 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
    423  1.6.8.2  nathanw 		cs->cs_rr0_dcd = 0;
    424  1.6.8.2  nathanw 		if ((cflag & MDMBUF) == 0)
    425  1.6.8.2  nathanw 			cs->cs_rr0_pps = ZSRR0_DCD;
    426  1.6.8.2  nathanw 	} else
    427  1.6.8.2  nathanw 		cs->cs_rr0_dcd = ZSRR0_DCD;
    428  1.6.8.2  nathanw 	if ((cflag & CRTSCTS) != 0) {
    429  1.6.8.2  nathanw 		cs->cs_wr5_dtr = ZSWR5_DTR;
    430  1.6.8.2  nathanw 		cs->cs_wr5_rts = ZSWR5_RTS;
    431  1.6.8.2  nathanw 		cs->cs_rr0_cts = ZSRR0_CTS;
    432  1.6.8.2  nathanw 	} else if ((cflag & MDMBUF) != 0) {
    433  1.6.8.2  nathanw 		cs->cs_wr5_dtr = 0;
    434  1.6.8.2  nathanw 		cs->cs_wr5_rts = ZSWR5_DTR;
    435  1.6.8.2  nathanw 		cs->cs_rr0_cts = ZSRR0_DCD;
    436  1.6.8.2  nathanw 	} else {
    437  1.6.8.2  nathanw 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
    438  1.6.8.2  nathanw 		cs->cs_wr5_rts = 0;
    439  1.6.8.2  nathanw 		cs->cs_rr0_cts = 0;
    440  1.6.8.2  nathanw 	}
    441  1.6.8.2  nathanw 	splx(s);
    442  1.6.8.2  nathanw 
    443  1.6.8.2  nathanw 	/* Caller will stuff the pending registers. */
    444  1.6.8.2  nathanw 	return (0);
    445  1.6.8.2  nathanw }
    446  1.6.8.2  nathanw 
    447  1.6.8.2  nathanw 
    448  1.6.8.2  nathanw /*
    449  1.6.8.2  nathanw  * Read or write the chip with suitable delays.
    450  1.6.8.2  nathanw  */
    451  1.6.8.2  nathanw 
    452  1.6.8.2  nathanw u_char
    453  1.6.8.2  nathanw zs_read_reg(cs, reg)
    454  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    455  1.6.8.2  nathanw 	u_char reg;
    456  1.6.8.2  nathanw {
    457  1.6.8.2  nathanw 	u_char val;
    458  1.6.8.2  nathanw 
    459  1.6.8.2  nathanw 	*cs->cs_reg_csr = reg;
    460  1.6.8.2  nathanw 	ZS_DELAY();
    461  1.6.8.2  nathanw 	val = *cs->cs_reg_csr;
    462  1.6.8.2  nathanw 	ZS_DELAY();
    463  1.6.8.2  nathanw 	return val;
    464  1.6.8.2  nathanw }
    465  1.6.8.2  nathanw 
    466  1.6.8.2  nathanw void
    467  1.6.8.2  nathanw zs_write_reg(cs, reg, val)
    468  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    469  1.6.8.2  nathanw 	u_char reg, val;
    470  1.6.8.2  nathanw {
    471  1.6.8.2  nathanw 	*cs->cs_reg_csr = reg;
    472  1.6.8.2  nathanw 	ZS_DELAY();
    473  1.6.8.2  nathanw 	*cs->cs_reg_csr = val;
    474  1.6.8.2  nathanw 	ZS_DELAY();
    475  1.6.8.2  nathanw }
    476  1.6.8.2  nathanw 
    477  1.6.8.2  nathanw u_char
    478  1.6.8.2  nathanw zs_read_csr(cs)
    479  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    480  1.6.8.2  nathanw {
    481  1.6.8.2  nathanw 	u_char val;
    482  1.6.8.2  nathanw 
    483  1.6.8.2  nathanw 	val = *cs->cs_reg_csr;
    484  1.6.8.2  nathanw 	ZS_DELAY();
    485  1.6.8.2  nathanw 	return val;
    486  1.6.8.2  nathanw }
    487  1.6.8.2  nathanw 
    488  1.6.8.2  nathanw void
    489  1.6.8.2  nathanw zs_write_csr(cs, val)
    490  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    491  1.6.8.2  nathanw 	u_char val;
    492  1.6.8.2  nathanw {
    493  1.6.8.2  nathanw 	*cs->cs_reg_csr = val;
    494  1.6.8.2  nathanw 	ZS_DELAY();
    495  1.6.8.2  nathanw }
    496  1.6.8.2  nathanw 
    497  1.6.8.2  nathanw u_char
    498  1.6.8.2  nathanw zs_read_data(cs)
    499  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    500  1.6.8.2  nathanw {
    501  1.6.8.2  nathanw 	u_char val;
    502  1.6.8.2  nathanw 
    503  1.6.8.2  nathanw 	val = *cs->cs_reg_data;
    504  1.6.8.2  nathanw 	ZS_DELAY();
    505  1.6.8.2  nathanw 	return val;
    506  1.6.8.2  nathanw }
    507  1.6.8.2  nathanw 
    508  1.6.8.2  nathanw void
    509  1.6.8.2  nathanw zs_write_data(cs, val)
    510  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    511  1.6.8.2  nathanw 	u_char val;
    512  1.6.8.2  nathanw {
    513  1.6.8.2  nathanw 	*cs->cs_reg_data = val;
    514  1.6.8.2  nathanw 	ZS_DELAY();
    515  1.6.8.2  nathanw }
    516  1.6.8.2  nathanw 
    517  1.6.8.2  nathanw void
    518  1.6.8.2  nathanw zs_abort(cs)
    519  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    520  1.6.8.2  nathanw {
    521  1.6.8.2  nathanw #ifdef DDB
    522  1.6.8.2  nathanw 	Debugger();
    523  1.6.8.2  nathanw #endif
    524  1.6.8.2  nathanw }
    525  1.6.8.2  nathanw 
    526  1.6.8.2  nathanw /*
    527  1.6.8.2  nathanw  * Polled input char.
    528  1.6.8.2  nathanw  */
    529  1.6.8.2  nathanw int
    530  1.6.8.2  nathanw zs_getc(arg)
    531  1.6.8.2  nathanw 	void *arg;
    532  1.6.8.2  nathanw {
    533  1.6.8.2  nathanw 	struct zs_chanstate *cs = arg;
    534  1.6.8.2  nathanw 	int s, c, rr0;
    535  1.6.8.2  nathanw 
    536  1.6.8.2  nathanw 	s = splhigh();
    537  1.6.8.2  nathanw 	/* Wait for a character to arrive. */
    538  1.6.8.2  nathanw 	do {
    539  1.6.8.2  nathanw 		rr0 = *cs->cs_reg_csr;
    540  1.6.8.2  nathanw 		ZS_DELAY();
    541  1.6.8.2  nathanw 	} while ((rr0 & ZSRR0_RX_READY) == 0);
    542  1.6.8.2  nathanw 
    543  1.6.8.2  nathanw 	c = *cs->cs_reg_data;
    544  1.6.8.2  nathanw 	ZS_DELAY();
    545  1.6.8.2  nathanw 	splx(s);
    546  1.6.8.2  nathanw 
    547  1.6.8.2  nathanw 	return c;
    548  1.6.8.2  nathanw }
    549  1.6.8.2  nathanw 
    550  1.6.8.2  nathanw /*
    551  1.6.8.2  nathanw  * Polled output char.
    552  1.6.8.2  nathanw  */
    553  1.6.8.2  nathanw void
    554  1.6.8.2  nathanw zs_putc(arg, c)
    555  1.6.8.2  nathanw 	void *arg;
    556  1.6.8.2  nathanw 	int c;
    557  1.6.8.2  nathanw {
    558  1.6.8.2  nathanw 	struct zs_chanstate *cs = arg;
    559  1.6.8.2  nathanw 	int s, rr0;
    560  1.6.8.2  nathanw 
    561  1.6.8.2  nathanw 	s = splhigh();
    562  1.6.8.2  nathanw 	/* Wait for transmitter to become ready. */
    563  1.6.8.2  nathanw 	do {
    564  1.6.8.2  nathanw 		rr0 = *cs->cs_reg_csr;
    565  1.6.8.2  nathanw 		ZS_DELAY();
    566  1.6.8.2  nathanw 	} while ((rr0 & ZSRR0_TX_READY) == 0);
    567  1.6.8.2  nathanw 
    568  1.6.8.2  nathanw 	*cs->cs_reg_data = c;
    569  1.6.8.2  nathanw 	ZS_DELAY();
    570  1.6.8.2  nathanw 	splx(s);
    571  1.6.8.2  nathanw }
    572  1.6.8.2  nathanw 
    573  1.6.8.2  nathanw /*****************************************************************/
    574  1.6.8.2  nathanw 
    575  1.6.8.4  thorpej static void zscnprobe(struct consdev *);
    576  1.6.8.4  thorpej static void zscninit(struct consdev *);
    577  1.6.8.4  thorpej static int  zscngetc(dev_t);
    578  1.6.8.4  thorpej static void zscnputc(dev_t, int);
    579  1.6.8.2  nathanw 
    580  1.6.8.2  nathanw struct consdev consdev_zs = {
    581  1.6.8.2  nathanw 	zscnprobe,
    582  1.6.8.2  nathanw 	zscninit,
    583  1.6.8.2  nathanw 	zscngetc,
    584  1.6.8.2  nathanw 	zscnputc,
    585  1.6.8.2  nathanw 	nullcnpollc,
    586  1.6.8.2  nathanw 	NULL,
    587  1.6.8.2  nathanw };
    588  1.6.8.2  nathanw 
    589  1.6.8.2  nathanw static void
    590  1.6.8.2  nathanw zscnprobe(cn)
    591  1.6.8.2  nathanw 	struct consdev *cn;
    592  1.6.8.2  nathanw {
    593  1.6.8.2  nathanw 	extern const struct cdevsw zstty_cdevsw;
    594  1.6.8.2  nathanw 	extern int tty00_is_console;
    595  1.6.8.2  nathanw 
    596  1.6.8.2  nathanw 	cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
    597  1.6.8.2  nathanw 	if (tty00_is_console)
    598  1.6.8.2  nathanw 		cn->cn_pri = CN_REMOTE;
    599  1.6.8.2  nathanw 	else
    600  1.6.8.2  nathanw 		cn->cn_pri = CN_NORMAL;
    601  1.6.8.2  nathanw }
    602  1.6.8.2  nathanw 
    603  1.6.8.2  nathanw static void
    604  1.6.8.2  nathanw zscninit(cn)
    605  1.6.8.2  nathanw 	struct consdev *cn;
    606  1.6.8.2  nathanw {
    607  1.6.8.2  nathanw 	struct zs_chanstate *cs;
    608  1.6.8.2  nathanw 
    609  1.6.8.2  nathanw 	extern volatile u_char *sccport0a;
    610  1.6.8.2  nathanw 
    611  1.6.8.2  nathanw 	zc_cons = (struct zschan *)sccport0a; /* XXX */
    612  1.6.8.2  nathanw 
    613  1.6.8.2  nathanw 	zs_conschan = cs = &zs_conschan_store;
    614  1.6.8.2  nathanw 
    615  1.6.8.2  nathanw 	/* Setup temporary chanstate. */
    616  1.6.8.2  nathanw 	cs->cs_reg_csr  = &zc_cons->zc_csr;
    617  1.6.8.2  nathanw 	cs->cs_reg_data = &zc_cons->zc_data;
    618  1.6.8.2  nathanw 
    619  1.6.8.2  nathanw 	/* Initialize the pending registers. */
    620  1.6.8.2  nathanw 	memcpy(cs->cs_preg, zs_init_reg, 16);
    621  1.6.8.2  nathanw 	cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
    622  1.6.8.2  nathanw 
    623  1.6.8.2  nathanw 	cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */
    624  1.6.8.2  nathanw 	cs->cs_preg[13] = 0;
    625  1.6.8.2  nathanw 	cs->cs_defspeed = 9600;
    626  1.6.8.2  nathanw 
    627  1.6.8.2  nathanw 	/* Clear the master interrupt enable. */
    628  1.6.8.2  nathanw 	zs_write_reg(cs, 9, 0);
    629  1.6.8.2  nathanw 
    630  1.6.8.2  nathanw 	/* Reset the whole SCC chip. */
    631  1.6.8.2  nathanw 	zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
    632  1.6.8.2  nathanw 
    633  1.6.8.2  nathanw 	/* Copy "pending" to "current" and H/W */
    634  1.6.8.2  nathanw 	zs_loadchannelregs(cs);
    635  1.6.8.2  nathanw }
    636  1.6.8.2  nathanw 
    637  1.6.8.2  nathanw static int
    638  1.6.8.2  nathanw zscngetc(dev)
    639  1.6.8.2  nathanw 	dev_t dev;
    640  1.6.8.2  nathanw {
    641  1.6.8.2  nathanw 	return zs_getc((void *)zs_conschan);
    642  1.6.8.2  nathanw }
    643  1.6.8.2  nathanw 
    644  1.6.8.2  nathanw static void
    645  1.6.8.2  nathanw zscnputc(dev, c)
    646  1.6.8.2  nathanw 	dev_t dev;
    647  1.6.8.2  nathanw 	int c;
    648  1.6.8.2  nathanw {
    649  1.6.8.2  nathanw 	zs_putc((void *)zs_conschan, c);
    650  1.6.8.2  nathanw }
    651