zs.c revision 1.1
1 /* $NetBSD: zs.c,v 1.1 1999/12/09 14:53:06 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 /* 47 * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c 48 */ 49 50 #include "opt_ddb.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/tty.h> 57 58 #include <machine/cpu.h> 59 #include <machine/z8530var.h> 60 61 #include <dev/cons.h> 62 #include <dev/ic/z8530reg.h> 63 64 #include <news68k/dev/hbvar.h> 65 66 #include "zsc.h" /* NZSC */ 67 #define NZS NZSC 68 69 /* Make life easier for the initialized arrays here. */ 70 #if NZS < 2 71 #undef NZS 72 #define NZS 2 73 #endif 74 75 struct zschan *zs_get_chan_addr __P((int, int)); 76 77 int zs_getc __P((void *)); 78 void zs_putc __P((void *, int)); 79 80 extern void Debugger __P((void)); 81 82 /* 83 * Some warts needed by z8530tty.c - 84 * The default parity REALLY needs to be the same as the PROM uses, 85 * or you can not see messages done with printf during boot-up... 86 */ 87 int zs_def_cflag = (CREAD | CS8 | HUPCL); 88 int zs_major = 1; 89 90 /* 91 * The news1700 seems to provide a 3.9936 MHz clock to the ZS chips. 92 */ 93 #define PCLK (9600 * 416) /* PCLK pin input clock rate */ 94 95 /* 96 * Define interrupt levels. 97 */ 98 #define ZSHARD_PRI 5 99 #define ZS_IVECT 64 100 101 #define ZS_DELAY() /* delay(2) */ 102 103 /* The layout of this is hardware-dependent (padding, order). */ 104 struct zschan { 105 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 106 volatile u_char zc_data; /* data */ 107 }; 108 struct zsdevice { 109 /* Yes, they are backwards. */ 110 struct zschan zs_chan_b; 111 struct zschan zs_chan_a; 112 }; 113 114 static struct zsdevice *zsaddr[NZS]; 115 static u_long zs_sir; 116 117 /* Flags from cninit() */ 118 static int zs_hwflags[NZS][2]; 119 120 /* Default speed for all channels */ 121 static int zs_defspeed = 9600; 122 123 static u_char zs_init_reg[16] = { 124 0, /* 0: CMD (reset, etc.) */ 125 0, /* 1: No interrupts yet. */ 126 ZS_IVECT, /* IVECT */ 127 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 128 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 129 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 130 0, /* 6: TXSYNC/SYNCLO */ 131 0, /* 7: RXSYNC/SYNCHI */ 132 0, /* 8: alias for data port */ 133 ZSWR9_MASTER_IE, 134 0, /*10: Misc. TX/RX control bits */ 135 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 136 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 137 0, /*13: BAUDHI (default=9600) */ 138 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 139 ZSWR15_BREAK_IE, 140 }; 141 142 struct zschan * 143 zs_get_chan_addr(zs_unit, channel) 144 int zs_unit, channel; 145 { 146 struct zsdevice *addr; 147 struct zschan *zc; 148 149 if (zs_unit >= NZS) 150 return NULL; 151 addr = zsaddr[zs_unit]; 152 if (addr == NULL) 153 return NULL; 154 if (channel == 0) { 155 zc = &addr->zs_chan_a; 156 } else { 157 zc = &addr->zs_chan_b; 158 } 159 return (zc); 160 } 161 162 163 /**************************************************************** 164 * Autoconfig 165 ****************************************************************/ 166 167 /* Definition of the driver for autoconfig. */ 168 static int zs_match __P((struct device *, struct cfdata *, void *)); 169 static void zs_attach __P((struct device *, struct device *, void *)); 170 static int zs_print __P((void *, const char *name)); 171 172 struct cfattach zsc_ca = { 173 sizeof(struct zsc_softc), zs_match, zs_attach 174 }; 175 176 extern struct cfdriver zsc_cd; 177 178 static int zshard __P((void *)); 179 int zssoft __P((void *)); 180 static int zs_get_speed __P((struct zs_chanstate *)); 181 182 /* 183 * Is the zs chip present? 184 */ 185 static int 186 zs_match(parent, cf, aux) 187 struct device *parent; 188 struct cfdata *cf; 189 void *aux; 190 { 191 struct hb_attach_args *ha = aux; 192 int addr; 193 194 if (strcmp(ha->ha_name, "zsc")) 195 return 0; 196 197 /* XXX no default address */ 198 if (ha->ha_address == -1) 199 return 0; 200 201 addr = IIOV(ha->ha_address); 202 /* This returns -1 on a fault (bus error). */ 203 if (badaddr((void *)addr, 1)) 204 return 0; 205 206 return 1; 207 } 208 209 /* 210 * Attach a found zs. 211 * 212 * Match slave number to zs unit number, so that misconfiguration will 213 * not set up the keyboard as ttya, etc. 214 */ 215 static void 216 zs_attach(parent, self, aux) 217 struct device *parent; 218 struct device *self; 219 void *aux; 220 { 221 struct zsc_softc *zsc = (void *) self; 222 struct hb_attach_args *ha = aux; 223 struct zsc_attach_args zsc_args; 224 volatile struct zschan *zc; 225 struct zs_chanstate *cs; 226 int s, zs_unit, channel; 227 228 zs_unit = zsc->zsc_dev.dv_unit; 229 zsaddr[zs_unit] = (void *)IIOV(ha->ha_address); 230 231 printf("\n"); 232 233 /* 234 * Initialize software state for each channel. 235 */ 236 for (channel = 0; channel < 2; channel++) { 237 zsc_args.channel = channel; 238 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 239 cs = &zsc->zsc_cs_store[channel]; 240 zsc->zsc_cs[channel] = cs; 241 242 cs->cs_channel = channel; 243 cs->cs_private = NULL; 244 cs->cs_ops = &zsops_null; 245 cs->cs_brg_clk = PCLK / 16; 246 247 zc = zs_get_chan_addr(zs_unit, channel); 248 cs->cs_reg_csr = &zc->zc_csr; 249 cs->cs_reg_data = &zc->zc_data; 250 251 if (ha->ha_vect != -1) 252 zs_init_reg[2] = ha->ha_vect; 253 bcopy(zs_init_reg, cs->cs_creg, 16); 254 bcopy(zs_init_reg, cs->cs_preg, 16); 255 256 /* XXX: Get these from the EEPROM instead? */ 257 /* XXX: See the mvme167 code. Better. */ 258 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 259 cs->cs_defspeed = zs_get_speed(cs); 260 else 261 cs->cs_defspeed = zs_defspeed; 262 cs->cs_defcflag = zs_def_cflag; 263 264 /* Make these correspond to cs_defcflag (-crtscts) */ 265 cs->cs_rr0_dcd = ZSRR0_DCD; 266 cs->cs_rr0_cts = 0; 267 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 268 cs->cs_wr5_rts = 0; 269 270 /* 271 * Clear the master interrupt enable. 272 * The INTENA is common to both channels, 273 * so just do it on the A channel. 274 */ 275 if (channel == 0) { 276 s = splhigh(); 277 zs_write_reg(cs, 9, 0); 278 splx(s); 279 } 280 281 /* 282 * Look for a child driver for this channel. 283 * The child attach will setup the hardware. 284 */ 285 if (!config_found(self, (void *)&zsc_args, zs_print)) { 286 /* No sub-driver. Just reset it. */ 287 u_char reset = (channel == 0) ? 288 ZSWR9_A_RESET : ZSWR9_B_RESET; 289 s = splhigh(); 290 zs_write_reg(cs, 9, reset); 291 splx(s); 292 } 293 } 294 295 /* 296 * Now safe to install interrupt handlers. 297 */ 298 hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc); 299 300 /* 301 * Set the master interrupt enable and interrupt vector. 302 * (common to both channels, do it on A) 303 */ 304 cs = zsc->zsc_cs[0]; 305 s = splhigh(); 306 /* interrupt vector */ 307 zs_write_reg(cs, 2, zs_init_reg[2]); 308 /* master interrupt control (enable) */ 309 zs_write_reg(cs, 9, zs_init_reg[9]); 310 splx(s); 311 312 if (zs_sir == 0) 313 zs_sir = allocate_sir((void (*) __P((void *)))zssoft, zsc); 314 } 315 316 static int 317 zs_print(aux, name) 318 void *aux; 319 const char *name; 320 { 321 struct zsc_attach_args *args = aux; 322 323 if (name != NULL) 324 printf("%s: ", name); 325 326 if (args->channel != -1) 327 printf(" channel %d", args->channel); 328 329 return UNCONF; 330 } 331 332 /* 333 * For news68k-port, we don't use autovectored interrupt. 334 * We do not need to look at all of the zs chips. 335 */ 336 static int 337 zshard(arg) 338 void *arg; 339 { 340 struct zsc_softc *zsc = arg; 341 int rval; 342 343 rval = zsc_intr_hard(zsc); 344 345 /* We are at splzs here, so no need to lock. */ 346 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) { 347 setsoftint(zs_sir); 348 } 349 350 return (rval); 351 } 352 353 /* 354 * Shared among the all chips. We have to look at all of them. 355 */ 356 int 357 zssoft(arg) 358 void *arg; 359 { 360 struct zsc_softc *zsc; 361 int s, unit; 362 363 /* Make sure we call the tty layer at spltty. */ 364 s = spltty(); 365 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 366 zsc = zsc_cd.cd_devs[unit]; 367 if (zsc == NULL) 368 continue; 369 (void) zsc_intr_soft(zsc); 370 } 371 splx(s); 372 373 return 1; 374 } 375 376 /* 377 * Compute the current baud rate given a ZS channel. 378 */ 379 static int 380 zs_get_speed(cs) 381 struct zs_chanstate *cs; 382 { 383 int tconst; 384 385 tconst = zs_read_reg(cs, 12); 386 tconst |= zs_read_reg(cs, 13) << 8; 387 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 388 } 389 390 /* 391 * MD functions for setting the baud rate and control modes. 392 */ 393 int 394 zs_set_speed(cs, bps) 395 struct zs_chanstate *cs; 396 int bps; /* bits per second */ 397 { 398 int tconst, real_bps; 399 400 if (bps == 0) 401 return (0); 402 403 #ifdef DIAGNOSTIC 404 if (cs->cs_brg_clk == 0) 405 panic("zs_set_speed"); 406 #endif 407 408 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 409 if (tconst < 0) 410 return (EINVAL); 411 412 /* Convert back to make sure we can do it. */ 413 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 414 415 /* XXX - Allow some tolerance here? */ 416 if (real_bps != bps) 417 return (EINVAL); 418 419 cs->cs_preg[12] = tconst; 420 cs->cs_preg[13] = tconst >> 8; 421 422 /* Caller will stuff the pending registers. */ 423 return (0); 424 } 425 426 int 427 zs_set_modes(cs, cflag) 428 struct zs_chanstate *cs; 429 int cflag; /* bits per second */ 430 { 431 int s; 432 433 /* 434 * Output hardware flow control on the chip is horrendous: 435 * if carrier detect drops, the receiver is disabled, and if 436 * CTS drops, the transmitter is stoped IN MID CHARACTER! 437 * Therefore, NEVER set the HFC bit, and instead use the 438 * status interrupt to detect CTS changes. 439 */ 440 s = splzs(); 441 cs->cs_rr0_pps = 0; 442 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 443 cs->cs_rr0_dcd = 0; 444 if ((cflag & MDMBUF) == 0) 445 cs->cs_rr0_pps = ZSRR0_DCD; 446 } else 447 cs->cs_rr0_dcd = ZSRR0_DCD; 448 if ((cflag & CRTSCTS) != 0) { 449 cs->cs_wr5_dtr = ZSWR5_DTR; 450 cs->cs_wr5_rts = ZSWR5_RTS; 451 cs->cs_rr0_cts = ZSRR0_CTS; 452 } else if ((cflag & MDMBUF) != 0) { 453 cs->cs_wr5_dtr = 0; 454 cs->cs_wr5_rts = ZSWR5_DTR; 455 cs->cs_rr0_cts = ZSRR0_DCD; 456 } else { 457 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 458 cs->cs_wr5_rts = 0; 459 cs->cs_rr0_cts = 0; 460 } 461 splx(s); 462 463 /* Caller will stuff the pending registers. */ 464 return (0); 465 } 466 467 468 /* 469 * Read or write the chip with suitable delays. 470 */ 471 472 u_char 473 zs_read_reg(cs, reg) 474 struct zs_chanstate *cs; 475 u_char reg; 476 { 477 u_char val; 478 479 *cs->cs_reg_csr = reg; 480 ZS_DELAY(); 481 val = *cs->cs_reg_csr; 482 ZS_DELAY(); 483 return val; 484 } 485 486 void 487 zs_write_reg(cs, reg, val) 488 struct zs_chanstate *cs; 489 u_char reg, val; 490 { 491 *cs->cs_reg_csr = reg; 492 ZS_DELAY(); 493 *cs->cs_reg_csr = val; 494 ZS_DELAY(); 495 } 496 497 u_char zs_read_csr(cs) 498 struct zs_chanstate *cs; 499 { 500 u_char val; 501 502 val = *cs->cs_reg_csr; 503 ZS_DELAY(); 504 return val; 505 } 506 507 void zs_write_csr(cs, val) 508 struct zs_chanstate *cs; 509 u_char val; 510 { 511 *cs->cs_reg_csr = val; 512 ZS_DELAY(); 513 } 514 515 u_char zs_read_data(cs) 516 struct zs_chanstate *cs; 517 { 518 u_char val; 519 520 val = *cs->cs_reg_data; 521 ZS_DELAY(); 522 return val; 523 } 524 525 void zs_write_data(cs, val) 526 struct zs_chanstate *cs; 527 u_char val; 528 { 529 *cs->cs_reg_data = val; 530 ZS_DELAY(); 531 } 532 533 void 534 zs_abort(cs) 535 struct zs_chanstate *cs; 536 { 537 #ifdef DDB 538 Debugger(); 539 #endif 540 } 541 542 /* 543 * Polled input char. 544 */ 545 int 546 zs_getc(arg) 547 void *arg; 548 { 549 volatile struct zschan *zc = arg; 550 int s, c, rr0; 551 552 s = splhigh(); 553 /* Wait for a character to arrive. */ 554 do { 555 rr0 = zc->zc_csr; 556 ZS_DELAY(); 557 } while ((rr0 & ZSRR0_RX_READY) == 0); 558 559 c = zc->zc_data; 560 ZS_DELAY(); 561 splx(s); 562 563 return c; 564 } 565 566 /* 567 * Polled output char. 568 */ 569 void 570 zs_putc(arg, c) 571 void *arg; 572 int c; 573 { 574 volatile struct zschan *zc = arg; 575 int s, rr0; 576 577 s = splhigh(); 578 /* Wait for transmitter to become ready. */ 579 do { 580 rr0 = zc->zc_csr; 581 ZS_DELAY(); 582 } while ((rr0 & ZSRR0_TX_READY) == 0); 583 584 zc->zc_data = c; 585 ZS_DELAY(); 586 splx(s); 587 } 588 589 /*****************************************************************/ 590 591 static void zscnprobe __P((struct consdev *)); 592 static void zscninit __P((struct consdev *)); 593 static int zscngetc __P((dev_t)); 594 static void zscnputc __P((dev_t, int)); 595 596 static void *zs_conschan; 597 598 struct consdev consdev_zs = { 599 zscnprobe, 600 zscninit, 601 zscngetc, 602 zscnputc, 603 nullcnpollc 604 }; 605 606 void 607 zscnprobe(cn) 608 struct consdev *cn; 609 { 610 } 611 612 void 613 zscninit(cn) 614 struct consdev *cn; 615 { 616 cn->cn_dev = makedev(zs_major, 0); 617 cn->cn_pri = CN_REMOTE; 618 zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE; 619 zs_conschan = (void *)SCCPORT0A; /* XXX */ 620 } 621 622 int 623 zscngetc(dev) 624 dev_t dev; 625 { 626 return zs_getc(zs_conschan); 627 } 628 629 void 630 zscnputc(dev, c) 631 dev_t dev; 632 int c; 633 { 634 zs_putc(zs_conschan, c); 635 } 636
Indexes created Mon Sep 29 03:10:08 GMT 2025