zs.c revision 1.10
1 /* $NetBSD: zs.c,v 1.10 2002/12/20 16:23:48 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 /* 47 * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c 48 */ 49 50 #include "opt_ddb.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/tty.h> 57 58 #include <machine/cpu.h> 59 #include <machine/z8530var.h> 60 61 #include <dev/cons.h> 62 #include <dev/ic/z8530reg.h> 63 64 #include <news68k/dev/hbvar.h> 65 66 int zs_getc(void *); 67 void zs_putc(void *, int); 68 69 /* 70 * Some warts needed by z8530tty.c - 71 * The default parity REALLY needs to be the same as the PROM uses, 72 * or you can not see messages done with printf during boot-up... 73 */ 74 int zs_def_cflag = (CREAD | CS8 | HUPCL); 75 76 /* 77 * The news68k machines use three different clocks for the ZS chips. 78 */ 79 #define NPCLK 3 80 #define PCLK0 (9600 * 416) /* news1700: 3.9936MHz */ 81 #define PCLK1 (9600 * 512) /* news1200: 4.9152MHz */ 82 #define PCLK2 (9600 * 384) /* external: 3.6864MHz */ 83 84 static const u_int pclk[NPCLK] = { 85 PCLK0, 86 PCLK1, 87 PCLK2, 88 }; 89 90 /* 91 * Define interrupt levels. 92 */ 93 #define ZSHARD_PRI 5 94 #define ZS_IVECT 64 95 96 #define ZS_DELAY() /* delay(2) */ 97 98 /* The layout of this is hardware-dependent (padding, order). */ 99 struct zschan { 100 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 101 volatile u_char zc_data; /* data */ 102 }; 103 struct zsdevice { 104 /* Yes, they are backwards. */ 105 struct zschan zs_chan_b; 106 struct zschan zs_chan_a; 107 }; 108 109 static u_char zs_sir; 110 111 /* Default speed for all channels */ 112 static int zs_defspeed = 9600; 113 114 /* console status from cninit */ 115 static struct zs_chanstate zs_conschan_store; 116 static struct zs_chanstate *zs_conschan; 117 static struct zschan *zc_cons; 118 119 static u_char zs_init_reg[16] = { 120 0, /* 0: CMD (reset, etc.) */ 121 0, /* 1: No interrupts yet. */ 122 ZS_IVECT, /* IVECT */ 123 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 124 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 125 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 126 0, /* 6: TXSYNC/SYNCLO */ 127 0, /* 7: RXSYNC/SYNCHI */ 128 0, /* 8: alias for data port */ 129 ZSWR9_MASTER_IE, 130 0, /*10: Misc. TX/RX control bits */ 131 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 132 BPS_TO_TCONST((PCLK0/16), 9600), /*12: BAUDLO (default=9600) */ 133 0, /*13: BAUDHI (default=9600) */ 134 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 135 ZSWR15_BREAK_IE, 136 }; 137 138 139 /**************************************************************** 140 * Autoconfig 141 ****************************************************************/ 142 143 /* Definition of the driver for autoconfig. */ 144 static int zs_match(struct device *, struct cfdata *, void *); 145 static void zs_attach(struct device *, struct device *, void *); 146 static int zs_print(void *, const char *name); 147 148 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 149 zs_match, zs_attach, NULL, NULL); 150 151 extern struct cfdriver zsc_cd; 152 153 static int zshard(void *); 154 void zssoft(void *); 155 #if 0 156 static int zs_get_speed(struct zs_chanstate *); 157 #endif 158 159 /* 160 * Is the zs chip present? 161 */ 162 static int 163 zs_match(parent, cf, aux) 164 struct device *parent; 165 struct cfdata *cf; 166 void *aux; 167 { 168 struct hb_attach_args *ha = aux; 169 u_int addr; 170 171 if (strcmp(ha->ha_name, "zsc")) 172 return 0; 173 174 /* XXX no default address */ 175 if (ha->ha_address == -1) 176 return 0; 177 178 addr = IIOV(ha->ha_address); 179 /* This returns -1 on a fault (bus error). */ 180 if (badaddr((void *)addr, 1)) 181 return 0; 182 183 return 1; 184 } 185 186 /* 187 * Attach a found zs. 188 */ 189 static void 190 zs_attach(parent, self, aux) 191 struct device *parent; 192 struct device *self; 193 void *aux; 194 { 195 struct zsc_softc *zsc = (void *) self; 196 struct cfdata *cf = self->dv_cfdata; 197 struct hb_attach_args *ha = aux; 198 struct zsc_attach_args zsc_args; 199 struct zsdevice *zs; 200 struct zschan *zc; 201 struct zs_chanstate *cs; 202 int s, channel, clk; 203 204 zs = (void *)IIOV(ha->ha_address); 205 206 clk = cf->cf_flags; 207 if (clk < 0 || clk >= NPCLK) 208 clk = 0; 209 210 printf("\n"); 211 212 /* 213 * Initialize software state for each channel. 214 */ 215 for (channel = 0; channel < 2; channel++) { 216 zsc_args.channel = channel; 217 cs = &zsc->zsc_cs_store[channel]; 218 zsc->zsc_cs[channel] = cs; 219 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 220 221 if (ha->ha_vect != -1) 222 zs_init_reg[2] = ha->ha_vect; 223 224 if (zc == zc_cons) { 225 memcpy(cs, zs_conschan, sizeof(struct zs_chanstate)); 226 zs_conschan = cs; 227 zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 228 } else { 229 cs->cs_reg_csr = &zc->zc_csr; 230 cs->cs_reg_data = &zc->zc_data; 231 memcpy(cs->cs_creg, zs_init_reg, 16); 232 memcpy(cs->cs_preg, zs_init_reg, 16); 233 cs->cs_defspeed = zs_defspeed; 234 zsc_args.hwflags = 0; 235 } 236 237 cs->cs_defcflag = zs_def_cflag; 238 239 cs->cs_channel = channel; 240 cs->cs_private = NULL; 241 cs->cs_ops = &zsops_null; 242 cs->cs_brg_clk = pclk[clk] / 16; 243 244 /* Make these correspond to cs_defcflag (-crtscts) */ 245 cs->cs_rr0_dcd = ZSRR0_DCD; 246 cs->cs_rr0_cts = 0; 247 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 248 cs->cs_wr5_rts = 0; 249 250 /* 251 * Clear the master interrupt enable. 252 * The INTENA is common to both channels, 253 * so just do it on the A channel. 254 */ 255 if (channel == 0) { 256 s = splhigh(); 257 zs_write_reg(cs, 9, 0); 258 splx(s); 259 } 260 261 /* 262 * Look for a child driver for this channel. 263 * The child attach will setup the hardware. 264 */ 265 if (!config_found(self, (void *)&zsc_args, zs_print)) { 266 /* No sub-driver. Just reset it. */ 267 u_char reset = (channel == 0) ? 268 ZSWR9_A_RESET : ZSWR9_B_RESET; 269 s = splhigh(); 270 zs_write_reg(cs, 9, reset); 271 splx(s); 272 } 273 } 274 275 /* 276 * Now safe to install interrupt handlers. 277 */ 278 hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc); 279 280 /* 281 * Set the master interrupt enable and interrupt vector. 282 * (common to both channels, do it on A) 283 */ 284 cs = zsc->zsc_cs[0]; 285 s = splhigh(); 286 /* interrupt vector */ 287 zs_write_reg(cs, 2, zs_init_reg[2]); 288 /* master interrupt control (enable) */ 289 zs_write_reg(cs, 9, zs_init_reg[9]); 290 splx(s); 291 292 if (zs_sir == 0) 293 zs_sir = allocate_sir(zssoft, zsc); 294 } 295 296 static int 297 zs_print(aux, name) 298 void *aux; 299 const char *name; 300 { 301 struct zsc_attach_args *args = aux; 302 303 if (name != NULL) 304 printf("%s: ", name); 305 306 if (args->channel != -1) 307 printf(" channel %d", args->channel); 308 309 return UNCONF; 310 } 311 312 /* 313 * For news68k-port, we don't use autovectored interrupt. 314 * We do not need to look at all of the zs chips. 315 */ 316 static int 317 zshard(arg) 318 void *arg; 319 { 320 struct zsc_softc *zsc = arg; 321 int rval; 322 323 rval = zsc_intr_hard(zsc); 324 325 /* We are at splzs here, so no need to lock. */ 326 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) { 327 setsoftint(zs_sir); 328 } 329 330 return (rval); 331 } 332 333 /* 334 * Shared among the all chips. We have to look at all of them. 335 */ 336 void 337 zssoft(arg) 338 void *arg; 339 { 340 struct zsc_softc *zsc; 341 int s, unit; 342 343 /* Make sure we call the tty layer at spltty. */ 344 s = spltty(); 345 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 346 zsc = zsc_cd.cd_devs[unit]; 347 if (zsc == NULL) 348 continue; 349 (void) zsc_intr_soft(zsc); 350 } 351 splx(s); 352 } 353 354 /* 355 * Compute the current baud rate given a ZS channel. 356 */ 357 #if 0 358 static int 359 zs_get_speed(cs) 360 struct zs_chanstate *cs; 361 { 362 int tconst; 363 364 tconst = zs_read_reg(cs, 12); 365 tconst |= zs_read_reg(cs, 13) << 8; 366 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 367 } 368 #endif 369 370 /* 371 * MD functions for setting the baud rate and control modes. 372 */ 373 int 374 zs_set_speed(cs, bps) 375 struct zs_chanstate *cs; 376 int bps; /* bits per second */ 377 { 378 int tconst, real_bps; 379 380 if (bps == 0) 381 return (0); 382 383 #ifdef DIAGNOSTIC 384 if (cs->cs_brg_clk == 0) 385 panic("zs_set_speed"); 386 #endif 387 388 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 389 if (tconst < 0) 390 return (EINVAL); 391 392 /* Convert back to make sure we can do it. */ 393 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 394 395 /* XXX - Allow some tolerance here? */ 396 if (real_bps != bps) 397 return (EINVAL); 398 399 cs->cs_preg[12] = tconst; 400 cs->cs_preg[13] = tconst >> 8; 401 402 /* Caller will stuff the pending registers. */ 403 return (0); 404 } 405 406 int 407 zs_set_modes(cs, cflag) 408 struct zs_chanstate *cs; 409 int cflag; /* bits per second */ 410 { 411 int s; 412 413 /* 414 * Output hardware flow control on the chip is horrendous: 415 * if carrier detect drops, the receiver is disabled, and if 416 * CTS drops, the transmitter is stoped IN MID CHARACTER! 417 * Therefore, NEVER set the HFC bit, and instead use the 418 * status interrupt to detect CTS changes. 419 */ 420 s = splzs(); 421 cs->cs_rr0_pps = 0; 422 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 423 cs->cs_rr0_dcd = 0; 424 if ((cflag & MDMBUF) == 0) 425 cs->cs_rr0_pps = ZSRR0_DCD; 426 } else 427 cs->cs_rr0_dcd = ZSRR0_DCD; 428 if ((cflag & CRTSCTS) != 0) { 429 cs->cs_wr5_dtr = ZSWR5_DTR; 430 cs->cs_wr5_rts = ZSWR5_RTS; 431 cs->cs_rr0_cts = ZSRR0_CTS; 432 } else if ((cflag & MDMBUF) != 0) { 433 cs->cs_wr5_dtr = 0; 434 cs->cs_wr5_rts = ZSWR5_DTR; 435 cs->cs_rr0_cts = ZSRR0_DCD; 436 } else { 437 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 438 cs->cs_wr5_rts = 0; 439 cs->cs_rr0_cts = 0; 440 } 441 splx(s); 442 443 /* Caller will stuff the pending registers. */ 444 return (0); 445 } 446 447 448 /* 449 * Read or write the chip with suitable delays. 450 */ 451 452 u_char 453 zs_read_reg(cs, reg) 454 struct zs_chanstate *cs; 455 u_char reg; 456 { 457 u_char val; 458 459 *cs->cs_reg_csr = reg; 460 ZS_DELAY(); 461 val = *cs->cs_reg_csr; 462 ZS_DELAY(); 463 return val; 464 } 465 466 void 467 zs_write_reg(cs, reg, val) 468 struct zs_chanstate *cs; 469 u_char reg, val; 470 { 471 *cs->cs_reg_csr = reg; 472 ZS_DELAY(); 473 *cs->cs_reg_csr = val; 474 ZS_DELAY(); 475 } 476 477 u_char 478 zs_read_csr(cs) 479 struct zs_chanstate *cs; 480 { 481 u_char val; 482 483 val = *cs->cs_reg_csr; 484 ZS_DELAY(); 485 return val; 486 } 487 488 void 489 zs_write_csr(cs, val) 490 struct zs_chanstate *cs; 491 u_char val; 492 { 493 *cs->cs_reg_csr = val; 494 ZS_DELAY(); 495 } 496 497 u_char 498 zs_read_data(cs) 499 struct zs_chanstate *cs; 500 { 501 u_char val; 502 503 val = *cs->cs_reg_data; 504 ZS_DELAY(); 505 return val; 506 } 507 508 void 509 zs_write_data(cs, val) 510 struct zs_chanstate *cs; 511 u_char val; 512 { 513 *cs->cs_reg_data = val; 514 ZS_DELAY(); 515 } 516 517 void 518 zs_abort(cs) 519 struct zs_chanstate *cs; 520 { 521 #ifdef DDB 522 Debugger(); 523 #endif 524 } 525 526 /* 527 * Polled input char. 528 */ 529 int 530 zs_getc(arg) 531 void *arg; 532 { 533 struct zs_chanstate *cs = arg; 534 int s, c, rr0; 535 536 s = splhigh(); 537 /* Wait for a character to arrive. */ 538 do { 539 rr0 = *cs->cs_reg_csr; 540 ZS_DELAY(); 541 } while ((rr0 & ZSRR0_RX_READY) == 0); 542 543 c = *cs->cs_reg_data; 544 ZS_DELAY(); 545 splx(s); 546 547 return c; 548 } 549 550 /* 551 * Polled output char. 552 */ 553 void 554 zs_putc(arg, c) 555 void *arg; 556 int c; 557 { 558 struct zs_chanstate *cs = arg; 559 int s, rr0; 560 561 s = splhigh(); 562 /* Wait for transmitter to become ready. */ 563 do { 564 rr0 = *cs->cs_reg_csr; 565 ZS_DELAY(); 566 } while ((rr0 & ZSRR0_TX_READY) == 0); 567 568 *cs->cs_reg_data = c; 569 ZS_DELAY(); 570 splx(s); 571 } 572 573 /*****************************************************************/ 574 575 static void zscnprobe(struct consdev *); 576 static void zscninit(struct consdev *); 577 static int zscngetc(dev_t); 578 static void zscnputc(dev_t, int); 579 580 struct consdev consdev_zs = { 581 zscnprobe, 582 zscninit, 583 zscngetc, 584 zscnputc, 585 nullcnpollc, 586 NULL, 587 }; 588 589 static void 590 zscnprobe(cn) 591 struct consdev *cn; 592 { 593 extern const struct cdevsw zstty_cdevsw; 594 extern int tty00_is_console; 595 596 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0); 597 if (tty00_is_console) 598 cn->cn_pri = CN_REMOTE; 599 else 600 cn->cn_pri = CN_NORMAL; 601 } 602 603 static void 604 zscninit(cn) 605 struct consdev *cn; 606 { 607 struct zs_chanstate *cs; 608 609 extern volatile u_char *sccport0a; 610 611 zc_cons = (struct zschan *)sccport0a; /* XXX */ 612 613 zs_conschan = cs = &zs_conschan_store; 614 615 /* Setup temporary chanstate. */ 616 cs->cs_reg_csr = &zc_cons->zc_csr; 617 cs->cs_reg_data = &zc_cons->zc_data; 618 619 /* Initialize the pending registers. */ 620 memcpy(cs->cs_preg, zs_init_reg, 16); 621 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 622 623 cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */ 624 cs->cs_preg[13] = 0; 625 cs->cs_defspeed = 9600; 626 627 /* Clear the master interrupt enable. */ 628 zs_write_reg(cs, 9, 0); 629 630 /* Reset the whole SCC chip. */ 631 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 632 633 /* Copy "pending" to "current" and H/W */ 634 zs_loadchannelregs(cs); 635 } 636 637 static int 638 zscngetc(dev) 639 dev_t dev; 640 { 641 return zs_getc((void *)zs_conschan); 642 } 643 644 static void 645 zscnputc(dev, c) 646 dev_t dev; 647 int c; 648 { 649 zs_putc((void *)zs_conschan, c); 650 } 651
Indexes created Mon Sep 29 03:10:08 GMT 2025