zs.c revision 1.13
1 /* $NetBSD: zs.c,v 1.13 2003/01/28 12:35:33 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 /* 47 * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c 48 */ 49 50 #include "opt_ddb.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/tty.h> 57 58 #include <machine/cpu.h> 59 #include <machine/z8530var.h> 60 61 #include <dev/cons.h> 62 #include <dev/ic/z8530reg.h> 63 64 #include <news68k/dev/hbvar.h> 65 66 int zs_getc(void *); 67 void zs_putc(void *, int); 68 69 /* 70 * Some warts needed by z8530tty.c - 71 * The default parity REALLY needs to be the same as the PROM uses, 72 * or you can not see messages done with printf during boot-up... 73 */ 74 int zs_def_cflag = (CREAD | CS8 | HUPCL); 75 76 /* 77 * The news68k machines use three different clocks for the ZS chips. 78 */ 79 #define NPCLK 3 80 #define PCLK0 (9600 * 416) /* news1700: 3.9936MHz */ 81 #define PCLK1 (9600 * 512) /* news1200: 4.9152MHz */ 82 #define PCLK2 (9600 * 384) /* external: 3.6864MHz */ 83 84 static const u_int pclk[NPCLK] = { 85 PCLK0, 86 PCLK1, 87 PCLK2, 88 }; 89 90 /* 91 * Define interrupt levels. 92 */ 93 #define ZSHARD_PRI 5 94 #define ZS_IVECT 64 95 96 #define ZS_DELAY() /* delay(2) */ 97 98 /* The layout of this is hardware-dependent (padding, order). */ 99 struct zschan { 100 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 101 volatile u_char zc_data; /* data */ 102 }; 103 struct zsdevice { 104 /* Yes, they are backwards. */ 105 struct zschan zs_chan_b; 106 struct zschan zs_chan_a; 107 }; 108 109 static u_char zs_sir; 110 111 /* Default speed for all channels */ 112 static int zs_defspeed = 9600; 113 114 /* console status from cninit */ 115 static struct zs_chanstate zs_conschan_store; 116 static struct zs_chanstate *zs_conschan; 117 static struct zschan *zc_cons; 118 119 static u_char zs_init_reg[16] = { 120 0, /* 0: CMD (reset, etc.) */ 121 0, /* 1: No interrupts yet. */ 122 ZS_IVECT, /* IVECT */ 123 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 124 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 125 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 126 0, /* 6: TXSYNC/SYNCLO */ 127 0, /* 7: RXSYNC/SYNCHI */ 128 0, /* 8: alias for data port */ 129 ZSWR9_MASTER_IE, 130 0, /*10: Misc. TX/RX control bits */ 131 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 132 BPS_TO_TCONST((PCLK0/16), 9600), /*12: BAUDLO (default=9600) */ 133 0, /*13: BAUDHI (default=9600) */ 134 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 135 ZSWR15_BREAK_IE, 136 }; 137 138 139 /**************************************************************** 140 * Autoconfig 141 ****************************************************************/ 142 143 /* Definition of the driver for autoconfig. */ 144 static int zs_match(struct device *, struct cfdata *, void *); 145 static void zs_attach(struct device *, struct device *, void *); 146 static int zs_print(void *, const char *name); 147 148 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 149 zs_match, zs_attach, NULL, NULL); 150 151 extern struct cfdriver zsc_cd; 152 153 static int zshard(void *); 154 void zssoft(void *); 155 #if 0 156 static int zs_get_speed(struct zs_chanstate *); 157 #endif 158 159 /* 160 * Is the zs chip present? 161 */ 162 static int 163 zs_match(parent, cf, aux) 164 struct device *parent; 165 struct cfdata *cf; 166 void *aux; 167 { 168 struct hb_attach_args *ha = aux; 169 u_int addr; 170 171 if (strcmp(ha->ha_name, "zsc")) 172 return 0; 173 174 /* XXX no default address */ 175 if (ha->ha_address == (u_int)-1) 176 return 0; 177 178 addr = IIOV(ha->ha_address); 179 /* This returns -1 on a fault (bus error). */ 180 if (badaddr((void *)addr, 1)) 181 return 0; 182 183 return 1; 184 } 185 186 /* 187 * Attach a found zs. 188 */ 189 static void 190 zs_attach(parent, self, aux) 191 struct device *parent; 192 struct device *self; 193 void *aux; 194 { 195 struct zsc_softc *zsc = (void *) self; 196 struct cfdata *cf = self->dv_cfdata; 197 struct hb_attach_args *ha = aux; 198 struct zsc_attach_args zsc_args; 199 struct zsdevice *zs; 200 struct zschan *zc; 201 struct zs_chanstate *cs; 202 int s, channel, clk; 203 204 zs = (void *)IIOV(ha->ha_address); 205 206 clk = cf->cf_flags; 207 if (clk < 0 || clk >= NPCLK) 208 clk = 0; 209 210 printf("\n"); 211 212 /* 213 * Initialize software state for each channel. 214 */ 215 for (channel = 0; channel < 2; channel++) { 216 zsc_args.channel = channel; 217 cs = &zsc->zsc_cs_store[channel]; 218 simple_lock_init(&cs->cs_lock); 219 220 zsc->zsc_cs[channel] = cs; 221 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 222 223 if (ha->ha_vect != -1) 224 zs_init_reg[2] = ha->ha_vect; 225 226 if (zc == zc_cons) { 227 memcpy(cs, zs_conschan, sizeof(struct zs_chanstate)); 228 zs_conschan = cs; 229 zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 230 } else { 231 cs->cs_reg_csr = &zc->zc_csr; 232 cs->cs_reg_data = &zc->zc_data; 233 memcpy(cs->cs_creg, zs_init_reg, 16); 234 memcpy(cs->cs_preg, zs_init_reg, 16); 235 cs->cs_defspeed = zs_defspeed; 236 zsc_args.hwflags = 0; 237 } 238 239 cs->cs_defcflag = zs_def_cflag; 240 241 cs->cs_channel = channel; 242 cs->cs_private = NULL; 243 cs->cs_ops = &zsops_null; 244 cs->cs_brg_clk = pclk[clk] / 16; 245 246 /* Make these correspond to cs_defcflag (-crtscts) */ 247 cs->cs_rr0_dcd = ZSRR0_DCD; 248 cs->cs_rr0_cts = 0; 249 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 250 cs->cs_wr5_rts = 0; 251 252 /* 253 * Clear the master interrupt enable. 254 * The INTENA is common to both channels, 255 * so just do it on the A channel. 256 */ 257 if (channel == 0) { 258 s = splhigh(); 259 zs_write_reg(cs, 9, 0); 260 splx(s); 261 } 262 263 /* 264 * Look for a child driver for this channel. 265 * The child attach will setup the hardware. 266 */ 267 if (!config_found(self, (void *)&zsc_args, zs_print)) { 268 /* No sub-driver. Just reset it. */ 269 u_char reset = (channel == 0) ? 270 ZSWR9_A_RESET : ZSWR9_B_RESET; 271 s = splhigh(); 272 zs_write_reg(cs, 9, reset); 273 splx(s); 274 } 275 } 276 277 /* 278 * Now safe to install interrupt handlers. 279 */ 280 hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc); 281 282 /* 283 * Set the master interrupt enable and interrupt vector. 284 * (common to both channels, do it on A) 285 */ 286 cs = zsc->zsc_cs[0]; 287 s = splhigh(); 288 /* interrupt vector */ 289 zs_write_reg(cs, 2, zs_init_reg[2]); 290 /* master interrupt control (enable) */ 291 zs_write_reg(cs, 9, zs_init_reg[9]); 292 splx(s); 293 294 if (zs_sir == 0) 295 zs_sir = allocate_sir(zssoft, zsc); 296 } 297 298 static int 299 zs_print(aux, name) 300 void *aux; 301 const char *name; 302 { 303 struct zsc_attach_args *args = aux; 304 305 if (name != NULL) 306 aprint_normal("%s: ", name); 307 308 if (args->channel != -1) 309 aprint_normal(" channel %d", args->channel); 310 311 return UNCONF; 312 } 313 314 /* 315 * For news68k-port, we don't use autovectored interrupt. 316 * We do not need to look at all of the zs chips. 317 */ 318 static int 319 zshard(arg) 320 void *arg; 321 { 322 struct zsc_softc *zsc = arg; 323 int rval; 324 325 rval = zsc_intr_hard(zsc); 326 327 /* We are at splzs here, so no need to lock. */ 328 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) { 329 setsoftint(zs_sir); 330 } 331 332 return (rval); 333 } 334 335 /* 336 * Shared among the all chips. We have to look at all of them. 337 */ 338 void 339 zssoft(arg) 340 void *arg; 341 { 342 struct zsc_softc *zsc; 343 int s, unit; 344 345 /* Make sure we call the tty layer at spltty. */ 346 s = spltty(); 347 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 348 zsc = zsc_cd.cd_devs[unit]; 349 if (zsc == NULL) 350 continue; 351 (void) zsc_intr_soft(zsc); 352 } 353 splx(s); 354 } 355 356 /* 357 * Compute the current baud rate given a ZS channel. 358 */ 359 #if 0 360 static int 361 zs_get_speed(cs) 362 struct zs_chanstate *cs; 363 { 364 int tconst; 365 366 tconst = zs_read_reg(cs, 12); 367 tconst |= zs_read_reg(cs, 13) << 8; 368 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 369 } 370 #endif 371 372 /* 373 * MD functions for setting the baud rate and control modes. 374 */ 375 int 376 zs_set_speed(cs, bps) 377 struct zs_chanstate *cs; 378 int bps; /* bits per second */ 379 { 380 int tconst, real_bps; 381 382 if (bps == 0) 383 return (0); 384 385 #ifdef DIAGNOSTIC 386 if (cs->cs_brg_clk == 0) 387 panic("zs_set_speed"); 388 #endif 389 390 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 391 if (tconst < 0) 392 return (EINVAL); 393 394 /* Convert back to make sure we can do it. */ 395 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 396 397 /* XXX - Allow some tolerance here? */ 398 if (real_bps != bps) 399 return (EINVAL); 400 401 cs->cs_preg[12] = tconst; 402 cs->cs_preg[13] = tconst >> 8; 403 404 /* Caller will stuff the pending registers. */ 405 return (0); 406 } 407 408 int 409 zs_set_modes(cs, cflag) 410 struct zs_chanstate *cs; 411 int cflag; /* bits per second */ 412 { 413 int s; 414 415 /* 416 * Output hardware flow control on the chip is horrendous: 417 * if carrier detect drops, the receiver is disabled, and if 418 * CTS drops, the transmitter is stoped IN MID CHARACTER! 419 * Therefore, NEVER set the HFC bit, and instead use the 420 * status interrupt to detect CTS changes. 421 */ 422 s = splzs(); 423 cs->cs_rr0_pps = 0; 424 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 425 cs->cs_rr0_dcd = 0; 426 if ((cflag & MDMBUF) == 0) 427 cs->cs_rr0_pps = ZSRR0_DCD; 428 } else 429 cs->cs_rr0_dcd = ZSRR0_DCD; 430 if ((cflag & CRTSCTS) != 0) { 431 cs->cs_wr5_dtr = ZSWR5_DTR; 432 cs->cs_wr5_rts = ZSWR5_RTS; 433 cs->cs_rr0_cts = ZSRR0_CTS; 434 } else if ((cflag & MDMBUF) != 0) { 435 cs->cs_wr5_dtr = 0; 436 cs->cs_wr5_rts = ZSWR5_DTR; 437 cs->cs_rr0_cts = ZSRR0_DCD; 438 } else { 439 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 440 cs->cs_wr5_rts = 0; 441 cs->cs_rr0_cts = 0; 442 } 443 splx(s); 444 445 /* Caller will stuff the pending registers. */ 446 return (0); 447 } 448 449 450 /* 451 * Read or write the chip with suitable delays. 452 */ 453 454 u_char 455 zs_read_reg(cs, reg) 456 struct zs_chanstate *cs; 457 u_char reg; 458 { 459 u_char val; 460 461 *cs->cs_reg_csr = reg; 462 ZS_DELAY(); 463 val = *cs->cs_reg_csr; 464 ZS_DELAY(); 465 return val; 466 } 467 468 void 469 zs_write_reg(cs, reg, val) 470 struct zs_chanstate *cs; 471 u_char reg, val; 472 { 473 *cs->cs_reg_csr = reg; 474 ZS_DELAY(); 475 *cs->cs_reg_csr = val; 476 ZS_DELAY(); 477 } 478 479 u_char 480 zs_read_csr(cs) 481 struct zs_chanstate *cs; 482 { 483 u_char val; 484 485 val = *cs->cs_reg_csr; 486 ZS_DELAY(); 487 return val; 488 } 489 490 void 491 zs_write_csr(cs, val) 492 struct zs_chanstate *cs; 493 u_char val; 494 { 495 *cs->cs_reg_csr = val; 496 ZS_DELAY(); 497 } 498 499 u_char 500 zs_read_data(cs) 501 struct zs_chanstate *cs; 502 { 503 u_char val; 504 505 val = *cs->cs_reg_data; 506 ZS_DELAY(); 507 return val; 508 } 509 510 void 511 zs_write_data(cs, val) 512 struct zs_chanstate *cs; 513 u_char val; 514 { 515 *cs->cs_reg_data = val; 516 ZS_DELAY(); 517 } 518 519 void 520 zs_abort(cs) 521 struct zs_chanstate *cs; 522 { 523 #ifdef DDB 524 Debugger(); 525 #endif 526 } 527 528 /* 529 * Polled input char. 530 */ 531 int 532 zs_getc(arg) 533 void *arg; 534 { 535 struct zs_chanstate *cs = arg; 536 int s, c, rr0; 537 538 s = splhigh(); 539 /* Wait for a character to arrive. */ 540 do { 541 rr0 = *cs->cs_reg_csr; 542 ZS_DELAY(); 543 } while ((rr0 & ZSRR0_RX_READY) == 0); 544 545 c = *cs->cs_reg_data; 546 ZS_DELAY(); 547 splx(s); 548 549 return c; 550 } 551 552 /* 553 * Polled output char. 554 */ 555 void 556 zs_putc(arg, c) 557 void *arg; 558 int c; 559 { 560 struct zs_chanstate *cs = arg; 561 int s, rr0; 562 563 s = splhigh(); 564 /* Wait for transmitter to become ready. */ 565 do { 566 rr0 = *cs->cs_reg_csr; 567 ZS_DELAY(); 568 } while ((rr0 & ZSRR0_TX_READY) == 0); 569 570 *cs->cs_reg_data = c; 571 ZS_DELAY(); 572 splx(s); 573 } 574 575 /*****************************************************************/ 576 577 static void zscnprobe(struct consdev *); 578 static void zscninit(struct consdev *); 579 static int zscngetc(dev_t); 580 static void zscnputc(dev_t, int); 581 582 struct consdev consdev_zs = { 583 zscnprobe, 584 zscninit, 585 zscngetc, 586 zscnputc, 587 nullcnpollc, 588 NULL, 589 }; 590 591 static void 592 zscnprobe(cn) 593 struct consdev *cn; 594 { 595 extern const struct cdevsw zstty_cdevsw; 596 extern int tty00_is_console; 597 598 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0); 599 if (tty00_is_console) 600 cn->cn_pri = CN_REMOTE; 601 else 602 cn->cn_pri = CN_NORMAL; 603 } 604 605 static void 606 zscninit(cn) 607 struct consdev *cn; 608 { 609 struct zs_chanstate *cs; 610 611 extern volatile u_char *sccport0a; 612 613 zc_cons = (struct zschan *)sccport0a; /* XXX */ 614 615 zs_conschan = cs = &zs_conschan_store; 616 617 /* Setup temporary chanstate. */ 618 cs->cs_reg_csr = &zc_cons->zc_csr; 619 cs->cs_reg_data = &zc_cons->zc_data; 620 621 /* Initialize the pending registers. */ 622 memcpy(cs->cs_preg, zs_init_reg, 16); 623 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 624 625 cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */ 626 cs->cs_preg[13] = 0; 627 cs->cs_defspeed = 9600; 628 629 /* Clear the master interrupt enable. */ 630 zs_write_reg(cs, 9, 0); 631 632 /* Reset the whole SCC chip. */ 633 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 634 635 /* Copy "pending" to "current" and H/W */ 636 zs_loadchannelregs(cs); 637 } 638 639 static int 640 zscngetc(dev) 641 dev_t dev; 642 { 643 return zs_getc((void *)zs_conschan); 644 } 645 646 static void 647 zscnputc(dev, c) 648 dev_t dev; 649 int c; 650 { 651 zs_putc((void *)zs_conschan, c); 652 } 653
Indexes created Sun Sep 28 16:09:52 GMT 2025