zs.c revision 1.18
1 /* $NetBSD: zs.c,v 1.18 2003/07/15 02:59:26 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 /* 47 * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c 48 */ 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.18 2003/07/15 02:59:26 lukem Exp $"); 52 53 #include "opt_ddb.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/conf.h> 58 #include <sys/device.h> 59 #include <sys/tty.h> 60 61 #include <machine/cpu.h> 62 #include <machine/z8530var.h> 63 64 #include <dev/cons.h> 65 #include <dev/ic/z8530reg.h> 66 67 #include <news68k/dev/hbvar.h> 68 69 int zs_getc(void *); 70 void zs_putc(void *, int); 71 72 /* 73 * Some warts needed by z8530tty.c - 74 * The default parity REALLY needs to be the same as the PROM uses, 75 * or you can not see messages done with printf during boot-up... 76 */ 77 int zs_def_cflag = (CREAD | CS8 | HUPCL); 78 79 /* 80 * The news68k machines use three different clocks for the ZS chips. 81 */ 82 #define NPCLK 3 83 #define PCLK0 (9600 * 416) /* news1700: 3.9936MHz */ 84 #define PCLK1 (9600 * 512) /* news1200: 4.9152MHz */ 85 #define PCLK2 (9600 * 384) /* external: 3.6864MHz */ 86 87 static const u_int pclk[NPCLK] = { 88 PCLK0, 89 PCLK1, 90 PCLK2, 91 }; 92 93 /* 94 * Define interrupt levels. 95 */ 96 #define ZSHARD_PRI 5 97 #define ZS_IVECT 64 98 99 #define ZS_DELAY() /* delay(2) */ 100 101 /* The layout of this is hardware-dependent (padding, order). */ 102 struct zschan { 103 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 104 volatile u_char zc_data; /* data */ 105 }; 106 struct zsdevice { 107 /* Yes, they are backwards. */ 108 struct zschan zs_chan_b; 109 struct zschan zs_chan_a; 110 }; 111 112 static u_char zs_sir; 113 114 /* Default speed for all channels */ 115 static int zs_defspeed = 9600; 116 117 /* console status from cninit */ 118 static struct zs_chanstate zs_conschan_store; 119 static struct zs_chanstate *zs_conschan; 120 static struct zschan *zc_cons; 121 122 static u_char zs_init_reg[16] = { 123 0, /* 0: CMD (reset, etc.) */ 124 0, /* 1: No interrupts yet. */ 125 ZS_IVECT, /* IVECT */ 126 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 127 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 128 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 129 0, /* 6: TXSYNC/SYNCLO */ 130 0, /* 7: RXSYNC/SYNCHI */ 131 0, /* 8: alias for data port */ 132 ZSWR9_MASTER_IE, 133 0, /*10: Misc. TX/RX control bits */ 134 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 135 BPS_TO_TCONST((PCLK0/16), 9600), /*12: BAUDLO (default=9600) */ 136 0, /*13: BAUDHI (default=9600) */ 137 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 138 ZSWR15_BREAK_IE, 139 }; 140 141 142 /**************************************************************** 143 * Autoconfig 144 ****************************************************************/ 145 146 /* Definition of the driver for autoconfig. */ 147 static int zs_match(struct device *, struct cfdata *, void *); 148 static void zs_attach(struct device *, struct device *, void *); 149 static int zs_print(void *, const char *name); 150 151 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 152 zs_match, zs_attach, NULL, NULL); 153 154 extern struct cfdriver zsc_cd; 155 156 static int zshard(void *); 157 void zssoft(void *); 158 #if 0 159 static int zs_get_speed(struct zs_chanstate *); 160 #endif 161 162 /* 163 * Is the zs chip present? 164 */ 165 static int 166 zs_match(parent, cf, aux) 167 struct device *parent; 168 struct cfdata *cf; 169 void *aux; 170 { 171 struct hb_attach_args *ha = aux; 172 u_int addr; 173 174 if (strcmp(ha->ha_name, "zsc")) 175 return 0; 176 177 /* XXX no default address */ 178 if (ha->ha_address == (u_int)-1) 179 return 0; 180 181 addr = IIOV(ha->ha_address); 182 /* This returns -1 on a fault (bus error). */ 183 if (badaddr((void *)addr, 1)) 184 return 0; 185 186 return 1; 187 } 188 189 /* 190 * Attach a found zs. 191 */ 192 static void 193 zs_attach(parent, self, aux) 194 struct device *parent; 195 struct device *self; 196 void *aux; 197 { 198 struct zsc_softc *zsc = (void *) self; 199 struct cfdata *cf = self->dv_cfdata; 200 struct hb_attach_args *ha = aux; 201 struct zsc_attach_args zsc_args; 202 struct zsdevice *zs; 203 struct zschan *zc; 204 struct zs_chanstate *cs; 205 int s, channel, clk; 206 207 zs = (void *)IIOV(ha->ha_address); 208 209 clk = cf->cf_flags; 210 if (clk < 0 || clk >= NPCLK) 211 clk = 0; 212 213 printf("\n"); 214 215 /* 216 * Initialize software state for each channel. 217 */ 218 for (channel = 0; channel < 2; channel++) { 219 zsc_args.channel = channel; 220 cs = &zsc->zsc_cs_store[channel]; 221 simple_lock_init(&cs->cs_lock); 222 223 zsc->zsc_cs[channel] = cs; 224 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 225 226 if (ha->ha_vect != -1) 227 zs_init_reg[2] = ha->ha_vect; 228 229 if (zc == zc_cons) { 230 memcpy(cs, zs_conschan, sizeof(struct zs_chanstate)); 231 zs_conschan = cs; 232 zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 233 } else { 234 cs->cs_reg_csr = &zc->zc_csr; 235 cs->cs_reg_data = &zc->zc_data; 236 memcpy(cs->cs_creg, zs_init_reg, 16); 237 memcpy(cs->cs_preg, zs_init_reg, 16); 238 cs->cs_defspeed = zs_defspeed; 239 zsc_args.hwflags = 0; 240 } 241 242 cs->cs_defcflag = zs_def_cflag; 243 244 cs->cs_channel = channel; 245 cs->cs_private = NULL; 246 cs->cs_ops = &zsops_null; 247 cs->cs_brg_clk = pclk[clk] / 16; 248 249 /* Make these correspond to cs_defcflag (-crtscts) */ 250 cs->cs_rr0_dcd = ZSRR0_DCD; 251 cs->cs_rr0_cts = 0; 252 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 253 cs->cs_wr5_rts = 0; 254 255 /* 256 * Clear the master interrupt enable. 257 * The INTENA is common to both channels, 258 * so just do it on the A channel. 259 */ 260 if (channel == 0) { 261 s = splhigh(); 262 zs_write_reg(cs, 9, 0); 263 splx(s); 264 } 265 266 /* 267 * Look for a child driver for this channel. 268 * The child attach will setup the hardware. 269 */ 270 if (!config_found(self, (void *)&zsc_args, zs_print)) { 271 /* No sub-driver. Just reset it. */ 272 u_char reset = (channel == 0) ? 273 ZSWR9_A_RESET : ZSWR9_B_RESET; 274 s = splhigh(); 275 zs_write_reg(cs, 9, reset); 276 splx(s); 277 } 278 } 279 280 /* 281 * Now safe to install interrupt handlers. 282 */ 283 hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc); 284 285 /* 286 * Set the master interrupt enable and interrupt vector. 287 * (common to both channels, do it on A) 288 */ 289 cs = zsc->zsc_cs[0]; 290 s = splhigh(); 291 /* interrupt vector */ 292 zs_write_reg(cs, 2, zs_init_reg[2]); 293 /* master interrupt control (enable) */ 294 zs_write_reg(cs, 9, zs_init_reg[9]); 295 splx(s); 296 297 if (zs_sir == 0) 298 zs_sir = allocate_sir(zssoft, zsc); 299 } 300 301 static int 302 zs_print(aux, name) 303 void *aux; 304 const char *name; 305 { 306 struct zsc_attach_args *args = aux; 307 308 if (name != NULL) 309 aprint_normal("%s: ", name); 310 311 if (args->channel != -1) 312 aprint_normal(" channel %d", args->channel); 313 314 return UNCONF; 315 } 316 317 /* 318 * For news68k-port, we don't use autovectored interrupt. 319 * We do not need to look at all of the zs chips. 320 */ 321 static int 322 zshard(arg) 323 void *arg; 324 { 325 struct zsc_softc *zsc = arg; 326 int rval; 327 328 rval = zsc_intr_hard(zsc); 329 330 /* We are at splzs here, so no need to lock. */ 331 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) { 332 setsoftint(zs_sir); 333 } 334 335 return rval; 336 } 337 338 /* 339 * Shared among the all chips. We have to look at all of them. 340 */ 341 void 342 zssoft(arg) 343 void *arg; 344 { 345 struct zsc_softc *zsc; 346 int s, unit; 347 348 /* Make sure we call the tty layer at spltty. */ 349 s = spltty(); 350 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 351 zsc = zsc_cd.cd_devs[unit]; 352 if (zsc == NULL) 353 continue; 354 (void) zsc_intr_soft(zsc); 355 } 356 splx(s); 357 } 358 359 /* 360 * Compute the current baud rate given a ZS channel. 361 */ 362 #if 0 363 static int 364 zs_get_speed(cs) 365 struct zs_chanstate *cs; 366 { 367 int tconst; 368 369 tconst = zs_read_reg(cs, 12); 370 tconst |= zs_read_reg(cs, 13) << 8; 371 return TCONST_TO_BPS(cs->cs_brg_clk, tconst); 372 } 373 #endif 374 375 /* 376 * MD functions for setting the baud rate and control modes. 377 */ 378 int 379 zs_set_speed(cs, bps) 380 struct zs_chanstate *cs; 381 int bps; /* bits per second */ 382 { 383 int tconst, real_bps; 384 385 if (bps == 0) 386 return 0; 387 388 #ifdef DIAGNOSTIC 389 if (cs->cs_brg_clk == 0) 390 panic("zs_set_speed"); 391 #endif 392 393 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 394 if (tconst < 0) 395 return EINVAL; 396 397 /* Convert back to make sure we can do it. */ 398 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 399 400 /* XXX - Allow some tolerance here? */ 401 if (real_bps != bps) 402 return EINVAL; 403 404 cs->cs_preg[12] = tconst; 405 cs->cs_preg[13] = tconst >> 8; 406 407 /* Caller will stuff the pending registers. */ 408 return 0; 409 } 410 411 int 412 zs_set_modes(cs, cflag) 413 struct zs_chanstate *cs; 414 int cflag; /* bits per second */ 415 { 416 int s; 417 418 /* 419 * Output hardware flow control on the chip is horrendous: 420 * if carrier detect drops, the receiver is disabled, and if 421 * CTS drops, the transmitter is stoped IN MID CHARACTER! 422 * Therefore, NEVER set the HFC bit, and instead use the 423 * status interrupt to detect CTS changes. 424 */ 425 s = splzs(); 426 cs->cs_rr0_pps = 0; 427 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 428 cs->cs_rr0_dcd = 0; 429 if ((cflag & MDMBUF) == 0) 430 cs->cs_rr0_pps = ZSRR0_DCD; 431 } else 432 cs->cs_rr0_dcd = ZSRR0_DCD; 433 if ((cflag & CRTSCTS) != 0) { 434 cs->cs_wr5_dtr = ZSWR5_DTR; 435 cs->cs_wr5_rts = ZSWR5_RTS; 436 cs->cs_rr0_cts = ZSRR0_CTS; 437 } else if ((cflag & MDMBUF) != 0) { 438 cs->cs_wr5_dtr = 0; 439 cs->cs_wr5_rts = ZSWR5_DTR; 440 cs->cs_rr0_cts = ZSRR0_DCD; 441 } else { 442 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 443 cs->cs_wr5_rts = 0; 444 cs->cs_rr0_cts = 0; 445 } 446 splx(s); 447 448 /* Caller will stuff the pending registers. */ 449 return 0; 450 } 451 452 453 /* 454 * Read or write the chip with suitable delays. 455 */ 456 457 u_char 458 zs_read_reg(cs, reg) 459 struct zs_chanstate *cs; 460 u_char reg; 461 { 462 u_char val; 463 464 *cs->cs_reg_csr = reg; 465 ZS_DELAY(); 466 val = *cs->cs_reg_csr; 467 ZS_DELAY(); 468 return val; 469 } 470 471 void 472 zs_write_reg(cs, reg, val) 473 struct zs_chanstate *cs; 474 u_char reg, val; 475 { 476 477 *cs->cs_reg_csr = reg; 478 ZS_DELAY(); 479 *cs->cs_reg_csr = val; 480 ZS_DELAY(); 481 } 482 483 u_char 484 zs_read_csr(cs) 485 struct zs_chanstate *cs; 486 { 487 u_char val; 488 489 val = *cs->cs_reg_csr; 490 ZS_DELAY(); 491 return val; 492 } 493 494 void 495 zs_write_csr(cs, val) 496 struct zs_chanstate *cs; 497 u_char val; 498 { 499 500 *cs->cs_reg_csr = val; 501 ZS_DELAY(); 502 } 503 504 u_char 505 zs_read_data(cs) 506 struct zs_chanstate *cs; 507 { 508 u_char val; 509 510 val = *cs->cs_reg_data; 511 ZS_DELAY(); 512 return val; 513 } 514 515 void 516 zs_write_data(cs, val) 517 struct zs_chanstate *cs; 518 u_char val; 519 { 520 521 *cs->cs_reg_data = val; 522 ZS_DELAY(); 523 } 524 525 void 526 zs_abort(cs) 527 struct zs_chanstate *cs; 528 { 529 530 #ifdef DDB 531 Debugger(); 532 #endif 533 } 534 535 /* 536 * Polled input char. 537 */ 538 int 539 zs_getc(arg) 540 void *arg; 541 { 542 struct zs_chanstate *cs = arg; 543 int s, c, rr0; 544 545 s = splhigh(); 546 /* Wait for a character to arrive. */ 547 do { 548 rr0 = *cs->cs_reg_csr; 549 ZS_DELAY(); 550 } while ((rr0 & ZSRR0_RX_READY) == 0); 551 552 c = *cs->cs_reg_data; 553 ZS_DELAY(); 554 splx(s); 555 556 return c; 557 } 558 559 /* 560 * Polled output char. 561 */ 562 void 563 zs_putc(arg, c) 564 void *arg; 565 int c; 566 { 567 struct zs_chanstate *cs = arg; 568 int s, rr0; 569 570 s = splhigh(); 571 /* Wait for transmitter to become ready. */ 572 do { 573 rr0 = *cs->cs_reg_csr; 574 ZS_DELAY(); 575 } while ((rr0 & ZSRR0_TX_READY) == 0); 576 577 *cs->cs_reg_data = c; 578 ZS_DELAY(); 579 splx(s); 580 } 581 582 /*****************************************************************/ 583 584 static void zscnprobe(struct consdev *); 585 static void zscninit(struct consdev *); 586 static int zscngetc(dev_t); 587 static void zscnputc(dev_t, int); 588 589 struct consdev consdev_zs = { 590 zscnprobe, 591 zscninit, 592 zscngetc, 593 zscnputc, 594 nullcnpollc, 595 NULL, 596 NULL, 597 NULL, 598 NODEV, 599 CN_DEAD 600 }; 601 602 static void 603 zscnprobe(cn) 604 struct consdev *cn; 605 { 606 } 607 608 static void 609 zscninit(cn) 610 struct consdev *cn; 611 { 612 struct zs_chanstate *cs; 613 614 extern const struct cdevsw zstty_cdevsw; 615 extern int tty00_is_console; 616 extern volatile u_char *sccport0a; 617 618 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0); 619 if (tty00_is_console) 620 cn->cn_pri = CN_REMOTE; 621 else 622 cn->cn_pri = CN_NORMAL; 623 624 zc_cons = (struct zschan *)sccport0a; /* XXX */ 625 626 zs_conschan = cs = &zs_conschan_store; 627 628 /* Setup temporary chanstate. */ 629 cs->cs_reg_csr = &zc_cons->zc_csr; 630 cs->cs_reg_data = &zc_cons->zc_data; 631 632 /* Initialize the pending registers. */ 633 memcpy(cs->cs_preg, zs_init_reg, 16); 634 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 635 636 cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */ 637 cs->cs_preg[13] = 0; 638 cs->cs_defspeed = 9600; 639 640 /* Clear the master interrupt enable. */ 641 zs_write_reg(cs, 9, 0); 642 643 /* Reset the whole SCC chip. */ 644 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 645 646 /* Copy "pending" to "current" and H/W */ 647 zs_loadchannelregs(cs); 648 } 649 650 static int 651 zscngetc(dev) 652 dev_t dev; 653 { 654 655 return zs_getc((void *)zs_conschan); 656 } 657 658 static void 659 zscnputc(dev, c) 660 dev_t dev; 661 int c; 662 { 663 664 zs_putc((void *)zs_conschan, c); 665 } 666
Indexes created Tue Sep 30 07:10:03 GMT 2025